Timing Messages

Report Title Timing Analysis Report
Design File C:\Users\ADMIN\OneDrive\Documents\OneKiwi-GW1AN-1S\impl\gwsynthesis\Led_project.vg
Physical Constraints File C:\Users\ADMIN\OneDrive\Documents\OneKiwi-GW1AN-1S\src\LED_test.cst
Timing Constraint File C:\Users\ADMIN\OneDrive\Documents\OneKiwi-GW1AN-1S\src\LED_test.sdc
Tool Version V1.9.12.02 (64-bit)
Part Number GW1AN-LV1SFN32C6/I5
Device GW1AN-1S
Device Version A
Created Time Mon Jul 27 03:59:49 2026
Legal Announcement Copyright (C)2014-2026 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 1.14V 85C C6/I5
Hold Delay Model Fast 1.26V 0C C6/I5
Numbers of Paths Analyzed 101
Numbers of Endpoints Analyzed 68
Numbers of Falling Endpoints 0
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
1 sys_clk Base 37.037 27.000 0.000 18.518 clk

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 sys_clk 27.000(MHz) 109.133(MHz) 5 TOP

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
sys_clk Setup 0.000 0
sys_clk Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 27.874 clk_cnt_12_s0/Q clk_cnt_31_s0/RESET sys_clk:[R] sys_clk:[R] 37.037 0.000 9.120
2 27.874 clk_cnt_12_s0/Q clk_cnt_30_s0/RESET sys_clk:[R] sys_clk:[R] 37.037 0.000 9.120
3 27.937 clk_cnt_12_s0/Q clk_cnt_0_s0/RESET sys_clk:[R] sys_clk:[R] 37.037 0.000 9.057
4 28.242 clk_cnt_12_s0/Q clk_cnt_24_s0/RESET sys_clk:[R] sys_clk:[R] 37.037 0.000 8.752
5 28.242 clk_cnt_12_s0/Q clk_cnt_25_s0/RESET sys_clk:[R] sys_clk:[R] 37.037 0.000 8.752
6 28.242 clk_cnt_12_s0/Q clk_cnt_26_s0/RESET sys_clk:[R] sys_clk:[R] 37.037 0.000 8.752
7 28.242 clk_cnt_12_s0/Q clk_cnt_27_s0/RESET sys_clk:[R] sys_clk:[R] 37.037 0.000 8.752
8 28.242 clk_cnt_12_s0/Q clk_cnt_28_s0/RESET sys_clk:[R] sys_clk:[R] 37.037 0.000 8.752
9 28.242 clk_cnt_12_s0/Q clk_cnt_29_s0/RESET sys_clk:[R] sys_clk:[R] 37.037 0.000 8.752
10 28.246 clk_cnt_12_s0/Q clk_cnt_18_s0/RESET sys_clk:[R] sys_clk:[R] 37.037 0.000 8.748
11 28.246 clk_cnt_12_s0/Q clk_cnt_19_s0/RESET sys_clk:[R] sys_clk:[R] 37.037 0.000 8.748
12 28.246 clk_cnt_12_s0/Q clk_cnt_20_s0/RESET sys_clk:[R] sys_clk:[R] 37.037 0.000 8.748
13 28.246 clk_cnt_12_s0/Q clk_cnt_21_s0/RESET sys_clk:[R] sys_clk:[R] 37.037 0.000 8.748
14 28.246 clk_cnt_12_s0/Q clk_cnt_22_s0/RESET sys_clk:[R] sys_clk:[R] 37.037 0.000 8.748
15 28.246 clk_cnt_12_s0/Q clk_cnt_23_s0/RESET sys_clk:[R] sys_clk:[R] 37.037 0.000 8.748
16 28.623 clk_cnt_12_s0/Q clk_cnt_12_s0/RESET sys_clk:[R] sys_clk:[R] 37.037 0.000 8.371
17 28.623 clk_cnt_12_s0/Q clk_cnt_13_s0/RESET sys_clk:[R] sys_clk:[R] 37.037 0.000 8.371
18 28.623 clk_cnt_12_s0/Q clk_cnt_14_s0/RESET sys_clk:[R] sys_clk:[R] 37.037 0.000 8.371
19 28.623 clk_cnt_12_s0/Q clk_cnt_15_s0/RESET sys_clk:[R] sys_clk:[R] 37.037 0.000 8.371
20 28.623 clk_cnt_12_s0/Q clk_cnt_16_s0/RESET sys_clk:[R] sys_clk:[R] 37.037 0.000 8.371
21 28.623 clk_cnt_12_s0/Q clk_cnt_17_s0/RESET sys_clk:[R] sys_clk:[R] 37.037 0.000 8.371
22 28.672 clk_cnt_12_s0/Q clk_cnt_1_s0/RESET sys_clk:[R] sys_clk:[R] 37.037 0.000 8.321
23 28.672 clk_cnt_12_s0/Q clk_cnt_2_s0/RESET sys_clk:[R] sys_clk:[R] 37.037 0.000 8.321
24 28.672 clk_cnt_12_s0/Q clk_cnt_3_s0/RESET sys_clk:[R] sys_clk:[R] 37.037 0.000 8.321
25 28.672 clk_cnt_12_s0/Q clk_cnt_4_s0/RESET sys_clk:[R] sys_clk:[R] 37.037 0.000 8.321

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.708 led_0_s3/Q led_0_s3/D sys_clk:[R] sys_clk:[R] 0.000 0.000 0.708
2 0.708 clk_cnt_0_s0/Q clk_cnt_0_s0/D sys_clk:[R] sys_clk:[R] 0.000 0.000 0.708
3 0.730 clk_cnt_2_s0/Q clk_cnt_2_s0/D sys_clk:[R] sys_clk:[R] 0.000 0.000 0.730
4 0.730 clk_cnt_6_s0/Q clk_cnt_6_s0/D sys_clk:[R] sys_clk:[R] 0.000 0.000 0.730
5 0.730 clk_cnt_8_s0/Q clk_cnt_8_s0/D sys_clk:[R] sys_clk:[R] 0.000 0.000 0.730
6 0.730 clk_cnt_12_s0/Q clk_cnt_12_s0/D sys_clk:[R] sys_clk:[R] 0.000 0.000 0.730
7 0.730 clk_cnt_14_s0/Q clk_cnt_14_s0/D sys_clk:[R] sys_clk:[R] 0.000 0.000 0.730
8 0.730 clk_cnt_18_s0/Q clk_cnt_18_s0/D sys_clk:[R] sys_clk:[R] 0.000 0.000 0.730
9 0.730 clk_cnt_20_s0/Q clk_cnt_20_s0/D sys_clk:[R] sys_clk:[R] 0.000 0.000 0.730
10 0.730 clk_cnt_24_s0/Q clk_cnt_24_s0/D sys_clk:[R] sys_clk:[R] 0.000 0.000 0.730
11 0.730 clk_cnt_26_s0/Q clk_cnt_26_s0/D sys_clk:[R] sys_clk:[R] 0.000 0.000 0.730
12 0.730 clk_cnt_30_s0/Q clk_cnt_30_s0/D sys_clk:[R] sys_clk:[R] 0.000 0.000 0.730
13 0.853 clk_cnt_1_s0/Q clk_cnt_1_s0/D sys_clk:[R] sys_clk:[R] 0.000 0.000 0.853
14 0.959 clk_cnt_31_s0/Q clk_cnt_31_s0/D sys_clk:[R] sys_clk:[R] 0.000 0.000 0.959
15 0.962 clk_cnt_5_s0/Q clk_cnt_5_s0/D sys_clk:[R] sys_clk:[R] 0.000 0.000 0.962
16 0.962 clk_cnt_9_s0/Q clk_cnt_9_s0/D sys_clk:[R] sys_clk:[R] 0.000 0.000 0.962
17 0.962 clk_cnt_15_s0/Q clk_cnt_15_s0/D sys_clk:[R] sys_clk:[R] 0.000 0.000 0.962
18 0.962 clk_cnt_21_s0/Q clk_cnt_21_s0/D sys_clk:[R] sys_clk:[R] 0.000 0.000 0.962
19 0.962 clk_cnt_27_s0/Q clk_cnt_27_s0/D sys_clk:[R] sys_clk:[R] 0.000 0.000 0.962
20 0.965 clk_cnt_10_s0/Q clk_cnt_10_s0/D sys_clk:[R] sys_clk:[R] 0.000 0.000 0.965
21 0.965 clk_cnt_11_s0/Q clk_cnt_11_s0/D sys_clk:[R] sys_clk:[R] 0.000 0.000 0.965
22 0.965 clk_cnt_16_s0/Q clk_cnt_16_s0/D sys_clk:[R] sys_clk:[R] 0.000 0.000 0.965
23 0.965 clk_cnt_17_s0/Q clk_cnt_17_s0/D sys_clk:[R] sys_clk:[R] 0.000 0.000 0.965
24 0.965 clk_cnt_22_s0/Q clk_cnt_22_s0/D sys_clk:[R] sys_clk:[R] 0.000 0.000 0.965
25 0.965 clk_cnt_23_s0/Q clk_cnt_23_s0/D sys_clk:[R] sys_clk:[R] 0.000 0.000 0.965

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 16.343 17.593 1.250 Low Pulse Width sys_clk clk_cnt_30_s0
2 16.343 17.593 1.250 Low Pulse Width sys_clk clk_cnt_28_s0
3 16.343 17.593 1.250 Low Pulse Width sys_clk clk_cnt_24_s0
4 16.343 17.593 1.250 Low Pulse Width sys_clk clk_cnt_16_s0
5 16.343 17.593 1.250 Low Pulse Width sys_clk clk_cnt_0_s0
6 16.343 17.593 1.250 Low Pulse Width sys_clk clk_cnt_1_s0
7 16.343 17.593 1.250 Low Pulse Width sys_clk clk_cnt_17_s0
8 16.343 17.593 1.250 Low Pulse Width sys_clk clk_cnt_2_s0
9 16.343 17.593 1.250 Low Pulse Width sys_clk clk_cnt_3_s0
10 16.343 17.593 1.250 Low Pulse Width sys_clk clk_cnt_25_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 27.874
Data Arrival Time 11.210
Data Required Time 39.084
From clk_cnt_12_s0
To clk_cnt_31_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
2.088 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
2.090 0.002 tNET RR 1 R7C16[0][A] clk_cnt_12_s0/CLK
2.548 0.458 tC2Q RF 2 R7C16[0][A] clk_cnt_12_s0/Q
2.887 0.339 tNET FF 1 R7C16[3][A] n73_s10/I0
3.986 1.099 tINS FF 2 R7C16[3][A] n73_s10/F
5.611 1.624 tNET FF 1 R8C15[1][B] n73_s4/I1
6.637 1.026 tINS FR 1 R8C15[1][B] n73_s4/F
7.055 0.419 tNET RR 1 R7C15[3][A] n73_s2/I0
7.877 0.822 tINS RF 2 R7C15[3][A] n73_s2/F
8.857 0.979 tNET FF 1 R5C16[0][B] n73_s1/I0
9.659 0.802 tINS FR 32 R5C16[0][B] n73_s1/F
11.210 1.551 tNET RR 1 R7C19[0][B] clk_cnt_31_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 sys_clk
37.037 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
39.125 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
39.127 0.002 tNET RR 1 R7C19[0][B] clk_cnt_31_s0/CLK
39.084 -0.043 tSu 1 R7C19[0][B] clk_cnt_31_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%
Arrival Data Path Delay cell: 3.749, 41.109%; route: 4.912, 53.866%; tC2Q: 0.458, 5.026%
Required Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%

Path2

Path Summary:

Slack 27.874
Data Arrival Time 11.210
Data Required Time 39.084
From clk_cnt_12_s0
To clk_cnt_30_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
2.088 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
2.090 0.002 tNET RR 1 R7C16[0][A] clk_cnt_12_s0/CLK
2.548 0.458 tC2Q RF 2 R7C16[0][A] clk_cnt_12_s0/Q
2.887 0.339 tNET FF 1 R7C16[3][A] n73_s10/I0
3.986 1.099 tINS FF 2 R7C16[3][A] n73_s10/F
5.611 1.624 tNET FF 1 R8C15[1][B] n73_s4/I1
6.637 1.026 tINS FR 1 R8C15[1][B] n73_s4/F
7.055 0.419 tNET RR 1 R7C15[3][A] n73_s2/I0
7.877 0.822 tINS RF 2 R7C15[3][A] n73_s2/F
8.857 0.979 tNET FF 1 R5C16[0][B] n73_s1/I0
9.659 0.802 tINS FR 32 R5C16[0][B] n73_s1/F
11.210 1.551 tNET RR 1 R7C19[0][A] clk_cnt_30_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 sys_clk
37.037 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
39.125 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
39.127 0.002 tNET RR 1 R7C19[0][A] clk_cnt_30_s0/CLK
39.084 -0.043 tSu 1 R7C19[0][A] clk_cnt_30_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%
Arrival Data Path Delay cell: 3.749, 41.109%; route: 4.912, 53.866%; tC2Q: 0.458, 5.026%
Required Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%

Path3

Path Summary:

Slack 27.937
Data Arrival Time 11.147
Data Required Time 39.084
From clk_cnt_12_s0
To clk_cnt_0_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
2.088 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
2.090 0.002 tNET RR 1 R7C16[0][A] clk_cnt_12_s0/CLK
2.548 0.458 tC2Q RF 2 R7C16[0][A] clk_cnt_12_s0/Q
2.887 0.339 tNET FF 1 R7C16[3][A] n73_s10/I0
3.986 1.099 tINS FF 2 R7C16[3][A] n73_s10/F
5.611 1.624 tNET FF 1 R8C15[1][B] n73_s4/I1
6.637 1.026 tINS FR 1 R8C15[1][B] n73_s4/F
7.055 0.419 tNET RR 1 R7C15[3][A] n73_s2/I0
7.877 0.822 tINS RF 2 R7C15[3][A] n73_s2/F
8.857 0.979 tNET FF 1 R5C16[0][B] n73_s1/I0
9.659 0.802 tINS FR 32 R5C16[0][B] n73_s1/F
11.147 1.488 tNET RR 1 R5C12[0][A] clk_cnt_0_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 sys_clk
37.037 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
39.125 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
39.127 0.002 tNET RR 1 R5C12[0][A] clk_cnt_0_s0/CLK
39.084 -0.043 tSu 1 R5C12[0][A] clk_cnt_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%
Arrival Data Path Delay cell: 3.749, 41.395%; route: 4.849, 53.544%; tC2Q: 0.458, 5.061%
Required Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%

Path4

Path Summary:

Slack 28.242
Data Arrival Time 10.842
Data Required Time 39.084
From clk_cnt_12_s0
To clk_cnt_24_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
2.088 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
2.090 0.002 tNET RR 1 R7C16[0][A] clk_cnt_12_s0/CLK
2.548 0.458 tC2Q RF 2 R7C16[0][A] clk_cnt_12_s0/Q
2.887 0.339 tNET FF 1 R7C16[3][A] n73_s10/I0
3.986 1.099 tINS FF 2 R7C16[3][A] n73_s10/F
5.611 1.624 tNET FF 1 R8C15[1][B] n73_s4/I1
6.637 1.026 tINS FR 1 R8C15[1][B] n73_s4/F
7.055 0.419 tNET RR 1 R7C15[3][A] n73_s2/I0
7.877 0.822 tINS RF 2 R7C15[3][A] n73_s2/F
8.857 0.979 tNET FF 1 R5C16[0][B] n73_s1/I0
9.659 0.802 tINS FR 32 R5C16[0][B] n73_s1/F
10.842 1.183 tNET RR 1 R7C18[0][A] clk_cnt_24_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 sys_clk
37.037 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
39.125 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
39.127 0.002 tNET RR 1 R7C18[0][A] clk_cnt_24_s0/CLK
39.084 -0.043 tSu 1 R7C18[0][A] clk_cnt_24_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%
Arrival Data Path Delay cell: 3.749, 42.835%; route: 4.545, 51.928%; tC2Q: 0.458, 5.237%
Required Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%

Path5

Path Summary:

Slack 28.242
Data Arrival Time 10.842
Data Required Time 39.084
From clk_cnt_12_s0
To clk_cnt_25_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
2.088 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
2.090 0.002 tNET RR 1 R7C16[0][A] clk_cnt_12_s0/CLK
2.548 0.458 tC2Q RF 2 R7C16[0][A] clk_cnt_12_s0/Q
2.887 0.339 tNET FF 1 R7C16[3][A] n73_s10/I0
3.986 1.099 tINS FF 2 R7C16[3][A] n73_s10/F
5.611 1.624 tNET FF 1 R8C15[1][B] n73_s4/I1
6.637 1.026 tINS FR 1 R8C15[1][B] n73_s4/F
7.055 0.419 tNET RR 1 R7C15[3][A] n73_s2/I0
7.877 0.822 tINS RF 2 R7C15[3][A] n73_s2/F
8.857 0.979 tNET FF 1 R5C16[0][B] n73_s1/I0
9.659 0.802 tINS FR 32 R5C16[0][B] n73_s1/F
10.842 1.183 tNET RR 1 R7C18[0][B] clk_cnt_25_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 sys_clk
37.037 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
39.125 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
39.127 0.002 tNET RR 1 R7C18[0][B] clk_cnt_25_s0/CLK
39.084 -0.043 tSu 1 R7C18[0][B] clk_cnt_25_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%
Arrival Data Path Delay cell: 3.749, 42.835%; route: 4.545, 51.928%; tC2Q: 0.458, 5.237%
Required Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%

Path6

Path Summary:

Slack 28.242
Data Arrival Time 10.842
Data Required Time 39.084
From clk_cnt_12_s0
To clk_cnt_26_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
2.088 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
2.090 0.002 tNET RR 1 R7C16[0][A] clk_cnt_12_s0/CLK
2.548 0.458 tC2Q RF 2 R7C16[0][A] clk_cnt_12_s0/Q
2.887 0.339 tNET FF 1 R7C16[3][A] n73_s10/I0
3.986 1.099 tINS FF 2 R7C16[3][A] n73_s10/F
5.611 1.624 tNET FF 1 R8C15[1][B] n73_s4/I1
6.637 1.026 tINS FR 1 R8C15[1][B] n73_s4/F
7.055 0.419 tNET RR 1 R7C15[3][A] n73_s2/I0
7.877 0.822 tINS RF 2 R7C15[3][A] n73_s2/F
8.857 0.979 tNET FF 1 R5C16[0][B] n73_s1/I0
9.659 0.802 tINS FR 32 R5C16[0][B] n73_s1/F
10.842 1.183 tNET RR 1 R7C18[1][A] clk_cnt_26_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 sys_clk
37.037 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
39.125 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
39.127 0.002 tNET RR 1 R7C18[1][A] clk_cnt_26_s0/CLK
39.084 -0.043 tSu 1 R7C18[1][A] clk_cnt_26_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%
Arrival Data Path Delay cell: 3.749, 42.835%; route: 4.545, 51.928%; tC2Q: 0.458, 5.237%
Required Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%

Path7

Path Summary:

Slack 28.242
Data Arrival Time 10.842
Data Required Time 39.084
From clk_cnt_12_s0
To clk_cnt_27_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
2.088 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
2.090 0.002 tNET RR 1 R7C16[0][A] clk_cnt_12_s0/CLK
2.548 0.458 tC2Q RF 2 R7C16[0][A] clk_cnt_12_s0/Q
2.887 0.339 tNET FF 1 R7C16[3][A] n73_s10/I0
3.986 1.099 tINS FF 2 R7C16[3][A] n73_s10/F
5.611 1.624 tNET FF 1 R8C15[1][B] n73_s4/I1
6.637 1.026 tINS FR 1 R8C15[1][B] n73_s4/F
7.055 0.419 tNET RR 1 R7C15[3][A] n73_s2/I0
7.877 0.822 tINS RF 2 R7C15[3][A] n73_s2/F
8.857 0.979 tNET FF 1 R5C16[0][B] n73_s1/I0
9.659 0.802 tINS FR 32 R5C16[0][B] n73_s1/F
10.842 1.183 tNET RR 1 R7C18[1][B] clk_cnt_27_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 sys_clk
37.037 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
39.125 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
39.127 0.002 tNET RR 1 R7C18[1][B] clk_cnt_27_s0/CLK
39.084 -0.043 tSu 1 R7C18[1][B] clk_cnt_27_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%
Arrival Data Path Delay cell: 3.749, 42.835%; route: 4.545, 51.928%; tC2Q: 0.458, 5.237%
Required Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%

Path8

Path Summary:

Slack 28.242
Data Arrival Time 10.842
Data Required Time 39.084
From clk_cnt_12_s0
To clk_cnt_28_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
2.088 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
2.090 0.002 tNET RR 1 R7C16[0][A] clk_cnt_12_s0/CLK
2.548 0.458 tC2Q RF 2 R7C16[0][A] clk_cnt_12_s0/Q
2.887 0.339 tNET FF 1 R7C16[3][A] n73_s10/I0
3.986 1.099 tINS FF 2 R7C16[3][A] n73_s10/F
5.611 1.624 tNET FF 1 R8C15[1][B] n73_s4/I1
6.637 1.026 tINS FR 1 R8C15[1][B] n73_s4/F
7.055 0.419 tNET RR 1 R7C15[3][A] n73_s2/I0
7.877 0.822 tINS RF 2 R7C15[3][A] n73_s2/F
8.857 0.979 tNET FF 1 R5C16[0][B] n73_s1/I0
9.659 0.802 tINS FR 32 R5C16[0][B] n73_s1/F
10.842 1.183 tNET RR 1 R7C18[2][A] clk_cnt_28_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 sys_clk
37.037 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
39.125 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
39.127 0.002 tNET RR 1 R7C18[2][A] clk_cnt_28_s0/CLK
39.084 -0.043 tSu 1 R7C18[2][A] clk_cnt_28_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%
Arrival Data Path Delay cell: 3.749, 42.835%; route: 4.545, 51.928%; tC2Q: 0.458, 5.237%
Required Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%

Path9

Path Summary:

Slack 28.242
Data Arrival Time 10.842
Data Required Time 39.084
From clk_cnt_12_s0
To clk_cnt_29_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
2.088 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
2.090 0.002 tNET RR 1 R7C16[0][A] clk_cnt_12_s0/CLK
2.548 0.458 tC2Q RF 2 R7C16[0][A] clk_cnt_12_s0/Q
2.887 0.339 tNET FF 1 R7C16[3][A] n73_s10/I0
3.986 1.099 tINS FF 2 R7C16[3][A] n73_s10/F
5.611 1.624 tNET FF 1 R8C15[1][B] n73_s4/I1
6.637 1.026 tINS FR 1 R8C15[1][B] n73_s4/F
7.055 0.419 tNET RR 1 R7C15[3][A] n73_s2/I0
7.877 0.822 tINS RF 2 R7C15[3][A] n73_s2/F
8.857 0.979 tNET FF 1 R5C16[0][B] n73_s1/I0
9.659 0.802 tINS FR 32 R5C16[0][B] n73_s1/F
10.842 1.183 tNET RR 1 R7C18[2][B] clk_cnt_29_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 sys_clk
37.037 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
39.125 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
39.127 0.002 tNET RR 1 R7C18[2][B] clk_cnt_29_s0/CLK
39.084 -0.043 tSu 1 R7C18[2][B] clk_cnt_29_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%
Arrival Data Path Delay cell: 3.749, 42.835%; route: 4.545, 51.928%; tC2Q: 0.458, 5.237%
Required Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%

Path10

Path Summary:

Slack 28.246
Data Arrival Time 10.838
Data Required Time 39.084
From clk_cnt_12_s0
To clk_cnt_18_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
2.088 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
2.090 0.002 tNET RR 1 R7C16[0][A] clk_cnt_12_s0/CLK
2.548 0.458 tC2Q RF 2 R7C16[0][A] clk_cnt_12_s0/Q
2.887 0.339 tNET FF 1 R7C16[3][A] n73_s10/I0
3.986 1.099 tINS FF 2 R7C16[3][A] n73_s10/F
5.611 1.624 tNET FF 1 R8C15[1][B] n73_s4/I1
6.637 1.026 tINS FR 1 R8C15[1][B] n73_s4/F
7.055 0.419 tNET RR 1 R7C15[3][A] n73_s2/I0
7.877 0.822 tINS RF 2 R7C15[3][A] n73_s2/F
8.857 0.979 tNET FF 1 R5C16[0][B] n73_s1/I0
9.659 0.802 tINS FR 32 R5C16[0][B] n73_s1/F
10.838 1.179 tNET RR 1 R7C17[0][A] clk_cnt_18_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 sys_clk
37.037 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
39.125 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
39.127 0.002 tNET RR 1 R7C17[0][A] clk_cnt_18_s0/CLK
39.084 -0.043 tSu 1 R7C17[0][A] clk_cnt_18_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%
Arrival Data Path Delay cell: 3.749, 42.858%; route: 4.540, 51.903%; tC2Q: 0.458, 5.240%
Required Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%

Path11

Path Summary:

Slack 28.246
Data Arrival Time 10.838
Data Required Time 39.084
From clk_cnt_12_s0
To clk_cnt_19_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
2.088 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
2.090 0.002 tNET RR 1 R7C16[0][A] clk_cnt_12_s0/CLK
2.548 0.458 tC2Q RF 2 R7C16[0][A] clk_cnt_12_s0/Q
2.887 0.339 tNET FF 1 R7C16[3][A] n73_s10/I0
3.986 1.099 tINS FF 2 R7C16[3][A] n73_s10/F
5.611 1.624 tNET FF 1 R8C15[1][B] n73_s4/I1
6.637 1.026 tINS FR 1 R8C15[1][B] n73_s4/F
7.055 0.419 tNET RR 1 R7C15[3][A] n73_s2/I0
7.877 0.822 tINS RF 2 R7C15[3][A] n73_s2/F
8.857 0.979 tNET FF 1 R5C16[0][B] n73_s1/I0
9.659 0.802 tINS FR 32 R5C16[0][B] n73_s1/F
10.838 1.179 tNET RR 1 R7C17[0][B] clk_cnt_19_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 sys_clk
37.037 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
39.125 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
39.127 0.002 tNET RR 1 R7C17[0][B] clk_cnt_19_s0/CLK
39.084 -0.043 tSu 1 R7C17[0][B] clk_cnt_19_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%
Arrival Data Path Delay cell: 3.749, 42.858%; route: 4.540, 51.903%; tC2Q: 0.458, 5.240%
Required Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%

Path12

Path Summary:

Slack 28.246
Data Arrival Time 10.838
Data Required Time 39.084
From clk_cnt_12_s0
To clk_cnt_20_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
2.088 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
2.090 0.002 tNET RR 1 R7C16[0][A] clk_cnt_12_s0/CLK
2.548 0.458 tC2Q RF 2 R7C16[0][A] clk_cnt_12_s0/Q
2.887 0.339 tNET FF 1 R7C16[3][A] n73_s10/I0
3.986 1.099 tINS FF 2 R7C16[3][A] n73_s10/F
5.611 1.624 tNET FF 1 R8C15[1][B] n73_s4/I1
6.637 1.026 tINS FR 1 R8C15[1][B] n73_s4/F
7.055 0.419 tNET RR 1 R7C15[3][A] n73_s2/I0
7.877 0.822 tINS RF 2 R7C15[3][A] n73_s2/F
8.857 0.979 tNET FF 1 R5C16[0][B] n73_s1/I0
9.659 0.802 tINS FR 32 R5C16[0][B] n73_s1/F
10.838 1.179 tNET RR 1 R7C17[1][A] clk_cnt_20_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 sys_clk
37.037 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
39.125 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
39.127 0.002 tNET RR 1 R7C17[1][A] clk_cnt_20_s0/CLK
39.084 -0.043 tSu 1 R7C17[1][A] clk_cnt_20_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%
Arrival Data Path Delay cell: 3.749, 42.858%; route: 4.540, 51.903%; tC2Q: 0.458, 5.240%
Required Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%

Path13

Path Summary:

Slack 28.246
Data Arrival Time 10.838
Data Required Time 39.084
From clk_cnt_12_s0
To clk_cnt_21_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
2.088 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
2.090 0.002 tNET RR 1 R7C16[0][A] clk_cnt_12_s0/CLK
2.548 0.458 tC2Q RF 2 R7C16[0][A] clk_cnt_12_s0/Q
2.887 0.339 tNET FF 1 R7C16[3][A] n73_s10/I0
3.986 1.099 tINS FF 2 R7C16[3][A] n73_s10/F
5.611 1.624 tNET FF 1 R8C15[1][B] n73_s4/I1
6.637 1.026 tINS FR 1 R8C15[1][B] n73_s4/F
7.055 0.419 tNET RR 1 R7C15[3][A] n73_s2/I0
7.877 0.822 tINS RF 2 R7C15[3][A] n73_s2/F
8.857 0.979 tNET FF 1 R5C16[0][B] n73_s1/I0
9.659 0.802 tINS FR 32 R5C16[0][B] n73_s1/F
10.838 1.179 tNET RR 1 R7C17[1][B] clk_cnt_21_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 sys_clk
37.037 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
39.125 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
39.127 0.002 tNET RR 1 R7C17[1][B] clk_cnt_21_s0/CLK
39.084 -0.043 tSu 1 R7C17[1][B] clk_cnt_21_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%
Arrival Data Path Delay cell: 3.749, 42.858%; route: 4.540, 51.903%; tC2Q: 0.458, 5.240%
Required Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%

Path14

Path Summary:

Slack 28.246
Data Arrival Time 10.838
Data Required Time 39.084
From clk_cnt_12_s0
To clk_cnt_22_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
2.088 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
2.090 0.002 tNET RR 1 R7C16[0][A] clk_cnt_12_s0/CLK
2.548 0.458 tC2Q RF 2 R7C16[0][A] clk_cnt_12_s0/Q
2.887 0.339 tNET FF 1 R7C16[3][A] n73_s10/I0
3.986 1.099 tINS FF 2 R7C16[3][A] n73_s10/F
5.611 1.624 tNET FF 1 R8C15[1][B] n73_s4/I1
6.637 1.026 tINS FR 1 R8C15[1][B] n73_s4/F
7.055 0.419 tNET RR 1 R7C15[3][A] n73_s2/I0
7.877 0.822 tINS RF 2 R7C15[3][A] n73_s2/F
8.857 0.979 tNET FF 1 R5C16[0][B] n73_s1/I0
9.659 0.802 tINS FR 32 R5C16[0][B] n73_s1/F
10.838 1.179 tNET RR 1 R7C17[2][A] clk_cnt_22_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 sys_clk
37.037 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
39.125 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
39.127 0.002 tNET RR 1 R7C17[2][A] clk_cnt_22_s0/CLK
39.084 -0.043 tSu 1 R7C17[2][A] clk_cnt_22_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%
Arrival Data Path Delay cell: 3.749, 42.858%; route: 4.540, 51.903%; tC2Q: 0.458, 5.240%
Required Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%

Path15

Path Summary:

Slack 28.246
Data Arrival Time 10.838
Data Required Time 39.084
From clk_cnt_12_s0
To clk_cnt_23_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
2.088 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
2.090 0.002 tNET RR 1 R7C16[0][A] clk_cnt_12_s0/CLK
2.548 0.458 tC2Q RF 2 R7C16[0][A] clk_cnt_12_s0/Q
2.887 0.339 tNET FF 1 R7C16[3][A] n73_s10/I0
3.986 1.099 tINS FF 2 R7C16[3][A] n73_s10/F
5.611 1.624 tNET FF 1 R8C15[1][B] n73_s4/I1
6.637 1.026 tINS FR 1 R8C15[1][B] n73_s4/F
7.055 0.419 tNET RR 1 R7C15[3][A] n73_s2/I0
7.877 0.822 tINS RF 2 R7C15[3][A] n73_s2/F
8.857 0.979 tNET FF 1 R5C16[0][B] n73_s1/I0
9.659 0.802 tINS FR 32 R5C16[0][B] n73_s1/F
10.838 1.179 tNET RR 1 R7C17[2][B] clk_cnt_23_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 sys_clk
37.037 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
39.125 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
39.127 0.002 tNET RR 1 R7C17[2][B] clk_cnt_23_s0/CLK
39.084 -0.043 tSu 1 R7C17[2][B] clk_cnt_23_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%
Arrival Data Path Delay cell: 3.749, 42.858%; route: 4.540, 51.903%; tC2Q: 0.458, 5.240%
Required Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%

Path16

Path Summary:

Slack 28.623
Data Arrival Time 10.461
Data Required Time 39.084
From clk_cnt_12_s0
To clk_cnt_12_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
2.088 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
2.090 0.002 tNET RR 1 R7C16[0][A] clk_cnt_12_s0/CLK
2.548 0.458 tC2Q RF 2 R7C16[0][A] clk_cnt_12_s0/Q
2.887 0.339 tNET FF 1 R7C16[3][A] n73_s10/I0
3.986 1.099 tINS FF 2 R7C16[3][A] n73_s10/F
5.611 1.624 tNET FF 1 R8C15[1][B] n73_s4/I1
6.637 1.026 tINS FR 1 R8C15[1][B] n73_s4/F
7.055 0.419 tNET RR 1 R7C15[3][A] n73_s2/I0
7.877 0.822 tINS RF 2 R7C15[3][A] n73_s2/F
8.857 0.979 tNET FF 1 R5C16[0][B] n73_s1/I0
9.659 0.802 tINS FR 32 R5C16[0][B] n73_s1/F
10.461 0.802 tNET RR 1 R7C16[0][A] clk_cnt_12_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 sys_clk
37.037 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
39.125 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
39.127 0.002 tNET RR 1 R7C16[0][A] clk_cnt_12_s0/CLK
39.084 -0.043 tSu 1 R7C16[0][A] clk_cnt_12_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%
Arrival Data Path Delay cell: 3.749, 44.786%; route: 4.163, 49.738%; tC2Q: 0.458, 5.475%
Required Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%

Path17

Path Summary:

Slack 28.623
Data Arrival Time 10.461
Data Required Time 39.084
From clk_cnt_12_s0
To clk_cnt_13_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
2.088 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
2.090 0.002 tNET RR 1 R7C16[0][A] clk_cnt_12_s0/CLK
2.548 0.458 tC2Q RF 2 R7C16[0][A] clk_cnt_12_s0/Q
2.887 0.339 tNET FF 1 R7C16[3][A] n73_s10/I0
3.986 1.099 tINS FF 2 R7C16[3][A] n73_s10/F
5.611 1.624 tNET FF 1 R8C15[1][B] n73_s4/I1
6.637 1.026 tINS FR 1 R8C15[1][B] n73_s4/F
7.055 0.419 tNET RR 1 R7C15[3][A] n73_s2/I0
7.877 0.822 tINS RF 2 R7C15[3][A] n73_s2/F
8.857 0.979 tNET FF 1 R5C16[0][B] n73_s1/I0
9.659 0.802 tINS FR 32 R5C16[0][B] n73_s1/F
10.461 0.802 tNET RR 1 R7C16[0][B] clk_cnt_13_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 sys_clk
37.037 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
39.125 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
39.127 0.002 tNET RR 1 R7C16[0][B] clk_cnt_13_s0/CLK
39.084 -0.043 tSu 1 R7C16[0][B] clk_cnt_13_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%
Arrival Data Path Delay cell: 3.749, 44.786%; route: 4.163, 49.738%; tC2Q: 0.458, 5.475%
Required Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%

Path18

Path Summary:

Slack 28.623
Data Arrival Time 10.461
Data Required Time 39.084
From clk_cnt_12_s0
To clk_cnt_14_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
2.088 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
2.090 0.002 tNET RR 1 R7C16[0][A] clk_cnt_12_s0/CLK
2.548 0.458 tC2Q RF 2 R7C16[0][A] clk_cnt_12_s0/Q
2.887 0.339 tNET FF 1 R7C16[3][A] n73_s10/I0
3.986 1.099 tINS FF 2 R7C16[3][A] n73_s10/F
5.611 1.624 tNET FF 1 R8C15[1][B] n73_s4/I1
6.637 1.026 tINS FR 1 R8C15[1][B] n73_s4/F
7.055 0.419 tNET RR 1 R7C15[3][A] n73_s2/I0
7.877 0.822 tINS RF 2 R7C15[3][A] n73_s2/F
8.857 0.979 tNET FF 1 R5C16[0][B] n73_s1/I0
9.659 0.802 tINS FR 32 R5C16[0][B] n73_s1/F
10.461 0.802 tNET RR 1 R7C16[1][A] clk_cnt_14_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 sys_clk
37.037 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
39.125 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
39.127 0.002 tNET RR 1 R7C16[1][A] clk_cnt_14_s0/CLK
39.084 -0.043 tSu 1 R7C16[1][A] clk_cnt_14_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%
Arrival Data Path Delay cell: 3.749, 44.786%; route: 4.163, 49.738%; tC2Q: 0.458, 5.475%
Required Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%

Path19

Path Summary:

Slack 28.623
Data Arrival Time 10.461
Data Required Time 39.084
From clk_cnt_12_s0
To clk_cnt_15_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
2.088 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
2.090 0.002 tNET RR 1 R7C16[0][A] clk_cnt_12_s0/CLK
2.548 0.458 tC2Q RF 2 R7C16[0][A] clk_cnt_12_s0/Q
2.887 0.339 tNET FF 1 R7C16[3][A] n73_s10/I0
3.986 1.099 tINS FF 2 R7C16[3][A] n73_s10/F
5.611 1.624 tNET FF 1 R8C15[1][B] n73_s4/I1
6.637 1.026 tINS FR 1 R8C15[1][B] n73_s4/F
7.055 0.419 tNET RR 1 R7C15[3][A] n73_s2/I0
7.877 0.822 tINS RF 2 R7C15[3][A] n73_s2/F
8.857 0.979 tNET FF 1 R5C16[0][B] n73_s1/I0
9.659 0.802 tINS FR 32 R5C16[0][B] n73_s1/F
10.461 0.802 tNET RR 1 R7C16[1][B] clk_cnt_15_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 sys_clk
37.037 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
39.125 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
39.127 0.002 tNET RR 1 R7C16[1][B] clk_cnt_15_s0/CLK
39.084 -0.043 tSu 1 R7C16[1][B] clk_cnt_15_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%
Arrival Data Path Delay cell: 3.749, 44.786%; route: 4.163, 49.738%; tC2Q: 0.458, 5.475%
Required Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%

Path20

Path Summary:

Slack 28.623
Data Arrival Time 10.461
Data Required Time 39.084
From clk_cnt_12_s0
To clk_cnt_16_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
2.088 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
2.090 0.002 tNET RR 1 R7C16[0][A] clk_cnt_12_s0/CLK
2.548 0.458 tC2Q RF 2 R7C16[0][A] clk_cnt_12_s0/Q
2.887 0.339 tNET FF 1 R7C16[3][A] n73_s10/I0
3.986 1.099 tINS FF 2 R7C16[3][A] n73_s10/F
5.611 1.624 tNET FF 1 R8C15[1][B] n73_s4/I1
6.637 1.026 tINS FR 1 R8C15[1][B] n73_s4/F
7.055 0.419 tNET RR 1 R7C15[3][A] n73_s2/I0
7.877 0.822 tINS RF 2 R7C15[3][A] n73_s2/F
8.857 0.979 tNET FF 1 R5C16[0][B] n73_s1/I0
9.659 0.802 tINS FR 32 R5C16[0][B] n73_s1/F
10.461 0.802 tNET RR 1 R7C16[2][A] clk_cnt_16_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 sys_clk
37.037 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
39.125 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
39.127 0.002 tNET RR 1 R7C16[2][A] clk_cnt_16_s0/CLK
39.084 -0.043 tSu 1 R7C16[2][A] clk_cnt_16_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%
Arrival Data Path Delay cell: 3.749, 44.786%; route: 4.163, 49.738%; tC2Q: 0.458, 5.475%
Required Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%

Path21

Path Summary:

Slack 28.623
Data Arrival Time 10.461
Data Required Time 39.084
From clk_cnt_12_s0
To clk_cnt_17_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
2.088 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
2.090 0.002 tNET RR 1 R7C16[0][A] clk_cnt_12_s0/CLK
2.548 0.458 tC2Q RF 2 R7C16[0][A] clk_cnt_12_s0/Q
2.887 0.339 tNET FF 1 R7C16[3][A] n73_s10/I0
3.986 1.099 tINS FF 2 R7C16[3][A] n73_s10/F
5.611 1.624 tNET FF 1 R8C15[1][B] n73_s4/I1
6.637 1.026 tINS FR 1 R8C15[1][B] n73_s4/F
7.055 0.419 tNET RR 1 R7C15[3][A] n73_s2/I0
7.877 0.822 tINS RF 2 R7C15[3][A] n73_s2/F
8.857 0.979 tNET FF 1 R5C16[0][B] n73_s1/I0
9.659 0.802 tINS FR 32 R5C16[0][B] n73_s1/F
10.461 0.802 tNET RR 1 R7C16[2][B] clk_cnt_17_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 sys_clk
37.037 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
39.125 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
39.127 0.002 tNET RR 1 R7C16[2][B] clk_cnt_17_s0/CLK
39.084 -0.043 tSu 1 R7C16[2][B] clk_cnt_17_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%
Arrival Data Path Delay cell: 3.749, 44.786%; route: 4.163, 49.738%; tC2Q: 0.458, 5.475%
Required Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%

Path22

Path Summary:

Slack 28.672
Data Arrival Time 10.411
Data Required Time 39.084
From clk_cnt_12_s0
To clk_cnt_1_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
2.088 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
2.090 0.002 tNET RR 1 R7C16[0][A] clk_cnt_12_s0/CLK
2.548 0.458 tC2Q RF 2 R7C16[0][A] clk_cnt_12_s0/Q
2.887 0.339 tNET FF 1 R7C16[3][A] n73_s10/I0
3.986 1.099 tINS FF 2 R7C16[3][A] n73_s10/F
5.611 1.624 tNET FF 1 R8C15[1][B] n73_s4/I1
6.637 1.026 tINS FR 1 R8C15[1][B] n73_s4/F
7.055 0.419 tNET RR 1 R7C15[3][A] n73_s2/I0
7.877 0.822 tINS RF 2 R7C15[3][A] n73_s2/F
8.857 0.979 tNET FF 1 R5C16[0][B] n73_s1/I0
9.659 0.802 tINS FR 32 R5C16[0][B] n73_s1/F
10.411 0.753 tNET RR 1 R7C14[0][B] clk_cnt_1_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 sys_clk
37.037 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
39.125 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
39.127 0.002 tNET RR 1 R7C14[0][B] clk_cnt_1_s0/CLK
39.084 -0.043 tSu 1 R7C14[0][B] clk_cnt_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%
Arrival Data Path Delay cell: 3.749, 45.052%; route: 4.114, 49.440%; tC2Q: 0.458, 5.508%
Required Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%

Path23

Path Summary:

Slack 28.672
Data Arrival Time 10.411
Data Required Time 39.084
From clk_cnt_12_s0
To clk_cnt_2_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
2.088 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
2.090 0.002 tNET RR 1 R7C16[0][A] clk_cnt_12_s0/CLK
2.548 0.458 tC2Q RF 2 R7C16[0][A] clk_cnt_12_s0/Q
2.887 0.339 tNET FF 1 R7C16[3][A] n73_s10/I0
3.986 1.099 tINS FF 2 R7C16[3][A] n73_s10/F
5.611 1.624 tNET FF 1 R8C15[1][B] n73_s4/I1
6.637 1.026 tINS FR 1 R8C15[1][B] n73_s4/F
7.055 0.419 tNET RR 1 R7C15[3][A] n73_s2/I0
7.877 0.822 tINS RF 2 R7C15[3][A] n73_s2/F
8.857 0.979 tNET FF 1 R5C16[0][B] n73_s1/I0
9.659 0.802 tINS FR 32 R5C16[0][B] n73_s1/F
10.411 0.753 tNET RR 1 R7C14[1][A] clk_cnt_2_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 sys_clk
37.037 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
39.125 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
39.127 0.002 tNET RR 1 R7C14[1][A] clk_cnt_2_s0/CLK
39.084 -0.043 tSu 1 R7C14[1][A] clk_cnt_2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%
Arrival Data Path Delay cell: 3.749, 45.052%; route: 4.114, 49.440%; tC2Q: 0.458, 5.508%
Required Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%

Path24

Path Summary:

Slack 28.672
Data Arrival Time 10.411
Data Required Time 39.084
From clk_cnt_12_s0
To clk_cnt_3_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
2.088 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
2.090 0.002 tNET RR 1 R7C16[0][A] clk_cnt_12_s0/CLK
2.548 0.458 tC2Q RF 2 R7C16[0][A] clk_cnt_12_s0/Q
2.887 0.339 tNET FF 1 R7C16[3][A] n73_s10/I0
3.986 1.099 tINS FF 2 R7C16[3][A] n73_s10/F
5.611 1.624 tNET FF 1 R8C15[1][B] n73_s4/I1
6.637 1.026 tINS FR 1 R8C15[1][B] n73_s4/F
7.055 0.419 tNET RR 1 R7C15[3][A] n73_s2/I0
7.877 0.822 tINS RF 2 R7C15[3][A] n73_s2/F
8.857 0.979 tNET FF 1 R5C16[0][B] n73_s1/I0
9.659 0.802 tINS FR 32 R5C16[0][B] n73_s1/F
10.411 0.753 tNET RR 1 R7C14[1][B] clk_cnt_3_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 sys_clk
37.037 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
39.125 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
39.127 0.002 tNET RR 1 R7C14[1][B] clk_cnt_3_s0/CLK
39.084 -0.043 tSu 1 R7C14[1][B] clk_cnt_3_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%
Arrival Data Path Delay cell: 3.749, 45.052%; route: 4.114, 49.440%; tC2Q: 0.458, 5.508%
Required Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%

Path25

Path Summary:

Slack 28.672
Data Arrival Time 10.411
Data Required Time 39.084
From clk_cnt_12_s0
To clk_cnt_4_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
2.088 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
2.090 0.002 tNET RR 1 R7C16[0][A] clk_cnt_12_s0/CLK
2.548 0.458 tC2Q RF 2 R7C16[0][A] clk_cnt_12_s0/Q
2.887 0.339 tNET FF 1 R7C16[3][A] n73_s10/I0
3.986 1.099 tINS FF 2 R7C16[3][A] n73_s10/F
5.611 1.624 tNET FF 1 R8C15[1][B] n73_s4/I1
6.637 1.026 tINS FR 1 R8C15[1][B] n73_s4/F
7.055 0.419 tNET RR 1 R7C15[3][A] n73_s2/I0
7.877 0.822 tINS RF 2 R7C15[3][A] n73_s2/F
8.857 0.979 tNET FF 1 R5C16[0][B] n73_s1/I0
9.659 0.802 tINS FR 32 R5C16[0][B] n73_s1/F
10.411 0.753 tNET RR 1 R7C14[2][A] clk_cnt_4_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 sys_clk
37.037 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
39.125 2.088 tINS RR 33 IOR5[A] clk_ibuf/O
39.127 0.002 tNET RR 1 R7C14[2][A] clk_cnt_4_s0/CLK
39.084 -0.043 tSu 1 R7C14[2][A] clk_cnt_4_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%
Arrival Data Path Delay cell: 3.749, 45.052%; route: 4.114, 49.440%; tC2Q: 0.458, 5.508%
Required Clock Path Delay cell: 2.088, 99.907%; route: 0.002, 0.093%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.708
Data Arrival Time 2.101
Data Required Time 1.394
From led_0_s3
To led_0_s3
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R5C16[0][A] led_0_s3/CLK
1.727 0.333 tC2Q RR 3 R5C16[0][A] led_0_s3/Q
1.729 0.002 tNET RR 1 R5C16[0][A] n140_s3/I2
2.101 0.372 tINS RF 1 R5C16[0][A] n140_s3/F
2.101 0.000 tNET FF 1 R5C16[0][A] led_0_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R5C16[0][A] led_0_s3/CLK
1.394 0.000 tHld 1 R5C16[0][A] led_0_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%

Path2

Path Summary:

Slack 0.708
Data Arrival Time 2.101
Data Required Time 1.394
From clk_cnt_0_s0
To clk_cnt_0_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R5C12[0][A] clk_cnt_0_s0/CLK
1.727 0.333 tC2Q RR 3 R5C12[0][A] clk_cnt_0_s0/Q
1.729 0.002 tNET RR 1 R5C12[0][A] n39_s2/I0
2.101 0.372 tINS RF 1 R5C12[0][A] n39_s2/F
2.101 0.000 tNET FF 1 R5C12[0][A] clk_cnt_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R5C12[0][A] clk_cnt_0_s0/CLK
1.394 0.000 tHld 1 R5C12[0][A] clk_cnt_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%

Path3

Path Summary:

Slack 0.730
Data Arrival Time 2.123
Data Required Time 1.394
From clk_cnt_2_s0
To clk_cnt_2_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C14[1][A] clk_cnt_2_s0/CLK
1.727 0.333 tC2Q RR 2 R7C14[1][A] clk_cnt_2_s0/Q
1.729 0.002 tNET RR 2 R7C14[1][A] n37_s/I1
2.123 0.394 tINS RF 1 R7C14[1][A] n37_s/SUM
2.123 0.000 tNET FF 1 R7C14[1][A] clk_cnt_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C14[1][A] clk_cnt_2_s0/CLK
1.394 0.000 tHld 1 R7C14[1][A] clk_cnt_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%
Arrival Data Path Delay cell: 0.394, 53.995%; route: 0.002, 0.324%; tC2Q: 0.333, 45.681%
Required Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%

Path4

Path Summary:

Slack 0.730
Data Arrival Time 2.123
Data Required Time 1.394
From clk_cnt_6_s0
To clk_cnt_6_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C15[0][A] clk_cnt_6_s0/CLK
1.727 0.333 tC2Q RR 2 R7C15[0][A] clk_cnt_6_s0/Q
1.729 0.002 tNET RR 2 R7C15[0][A] n33_s/I1
2.123 0.394 tINS RF 1 R7C15[0][A] n33_s/SUM
2.123 0.000 tNET FF 1 R7C15[0][A] clk_cnt_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C15[0][A] clk_cnt_6_s0/CLK
1.394 0.000 tHld 1 R7C15[0][A] clk_cnt_6_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%
Arrival Data Path Delay cell: 0.394, 53.995%; route: 0.002, 0.324%; tC2Q: 0.333, 45.681%
Required Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%

Path5

Path Summary:

Slack 0.730
Data Arrival Time 2.123
Data Required Time 1.394
From clk_cnt_8_s0
To clk_cnt_8_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C15[1][A] clk_cnt_8_s0/CLK
1.727 0.333 tC2Q RR 2 R7C15[1][A] clk_cnt_8_s0/Q
1.729 0.002 tNET RR 2 R7C15[1][A] n31_s/I1
2.123 0.394 tINS RF 1 R7C15[1][A] n31_s/SUM
2.123 0.000 tNET FF 1 R7C15[1][A] clk_cnt_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C15[1][A] clk_cnt_8_s0/CLK
1.394 0.000 tHld 1 R7C15[1][A] clk_cnt_8_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%
Arrival Data Path Delay cell: 0.394, 53.995%; route: 0.002, 0.324%; tC2Q: 0.333, 45.681%
Required Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%

Path6

Path Summary:

Slack 0.730
Data Arrival Time 2.123
Data Required Time 1.394
From clk_cnt_12_s0
To clk_cnt_12_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C16[0][A] clk_cnt_12_s0/CLK
1.727 0.333 tC2Q RR 2 R7C16[0][A] clk_cnt_12_s0/Q
1.729 0.002 tNET RR 2 R7C16[0][A] n27_s/I1
2.123 0.394 tINS RF 1 R7C16[0][A] n27_s/SUM
2.123 0.000 tNET FF 1 R7C16[0][A] clk_cnt_12_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C16[0][A] clk_cnt_12_s0/CLK
1.394 0.000 tHld 1 R7C16[0][A] clk_cnt_12_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%
Arrival Data Path Delay cell: 0.394, 53.995%; route: 0.002, 0.324%; tC2Q: 0.333, 45.681%
Required Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%

Path7

Path Summary:

Slack 0.730
Data Arrival Time 2.123
Data Required Time 1.394
From clk_cnt_14_s0
To clk_cnt_14_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C16[1][A] clk_cnt_14_s0/CLK
1.727 0.333 tC2Q RR 2 R7C16[1][A] clk_cnt_14_s0/Q
1.729 0.002 tNET RR 2 R7C16[1][A] n25_s/I1
2.123 0.394 tINS RF 1 R7C16[1][A] n25_s/SUM
2.123 0.000 tNET FF 1 R7C16[1][A] clk_cnt_14_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C16[1][A] clk_cnt_14_s0/CLK
1.394 0.000 tHld 1 R7C16[1][A] clk_cnt_14_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%
Arrival Data Path Delay cell: 0.394, 53.995%; route: 0.002, 0.324%; tC2Q: 0.333, 45.681%
Required Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%

Path8

Path Summary:

Slack 0.730
Data Arrival Time 2.123
Data Required Time 1.394
From clk_cnt_18_s0
To clk_cnt_18_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C17[0][A] clk_cnt_18_s0/CLK
1.727 0.333 tC2Q RR 2 R7C17[0][A] clk_cnt_18_s0/Q
1.729 0.002 tNET RR 2 R7C17[0][A] n21_s/I1
2.123 0.394 tINS RF 1 R7C17[0][A] n21_s/SUM
2.123 0.000 tNET FF 1 R7C17[0][A] clk_cnt_18_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C17[0][A] clk_cnt_18_s0/CLK
1.394 0.000 tHld 1 R7C17[0][A] clk_cnt_18_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%
Arrival Data Path Delay cell: 0.394, 53.995%; route: 0.002, 0.324%; tC2Q: 0.333, 45.681%
Required Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%

Path9

Path Summary:

Slack 0.730
Data Arrival Time 2.123
Data Required Time 1.394
From clk_cnt_20_s0
To clk_cnt_20_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C17[1][A] clk_cnt_20_s0/CLK
1.727 0.333 tC2Q RR 2 R7C17[1][A] clk_cnt_20_s0/Q
1.729 0.002 tNET RR 2 R7C17[1][A] n19_s/I1
2.123 0.394 tINS RF 1 R7C17[1][A] n19_s/SUM
2.123 0.000 tNET FF 1 R7C17[1][A] clk_cnt_20_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C17[1][A] clk_cnt_20_s0/CLK
1.394 0.000 tHld 1 R7C17[1][A] clk_cnt_20_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%
Arrival Data Path Delay cell: 0.394, 53.995%; route: 0.002, 0.324%; tC2Q: 0.333, 45.681%
Required Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%

Path10

Path Summary:

Slack 0.730
Data Arrival Time 2.123
Data Required Time 1.394
From clk_cnt_24_s0
To clk_cnt_24_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C18[0][A] clk_cnt_24_s0/CLK
1.727 0.333 tC2Q RR 2 R7C18[0][A] clk_cnt_24_s0/Q
1.729 0.002 tNET RR 2 R7C18[0][A] n15_s/I1
2.123 0.394 tINS RF 1 R7C18[0][A] n15_s/SUM
2.123 0.000 tNET FF 1 R7C18[0][A] clk_cnt_24_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C18[0][A] clk_cnt_24_s0/CLK
1.394 0.000 tHld 1 R7C18[0][A] clk_cnt_24_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%
Arrival Data Path Delay cell: 0.394, 53.995%; route: 0.002, 0.324%; tC2Q: 0.333, 45.681%
Required Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%

Path11

Path Summary:

Slack 0.730
Data Arrival Time 2.123
Data Required Time 1.394
From clk_cnt_26_s0
To clk_cnt_26_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C18[1][A] clk_cnt_26_s0/CLK
1.727 0.333 tC2Q RR 2 R7C18[1][A] clk_cnt_26_s0/Q
1.729 0.002 tNET RR 2 R7C18[1][A] n13_s/I1
2.123 0.394 tINS RF 1 R7C18[1][A] n13_s/SUM
2.123 0.000 tNET FF 1 R7C18[1][A] clk_cnt_26_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C18[1][A] clk_cnt_26_s0/CLK
1.394 0.000 tHld 1 R7C18[1][A] clk_cnt_26_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%
Arrival Data Path Delay cell: 0.394, 53.995%; route: 0.002, 0.324%; tC2Q: 0.333, 45.681%
Required Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%

Path12

Path Summary:

Slack 0.730
Data Arrival Time 2.123
Data Required Time 1.394
From clk_cnt_30_s0
To clk_cnt_30_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C19[0][A] clk_cnt_30_s0/CLK
1.727 0.333 tC2Q RR 2 R7C19[0][A] clk_cnt_30_s0/Q
1.729 0.002 tNET RR 2 R7C19[0][A] n9_s/I1
2.123 0.394 tINS RF 1 R7C19[0][A] n9_s/SUM
2.123 0.000 tNET FF 1 R7C19[0][A] clk_cnt_30_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C19[0][A] clk_cnt_30_s0/CLK
1.394 0.000 tHld 1 R7C19[0][A] clk_cnt_30_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%
Arrival Data Path Delay cell: 0.394, 53.995%; route: 0.002, 0.324%; tC2Q: 0.333, 45.681%
Required Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%

Path13

Path Summary:

Slack 0.853
Data Arrival Time 2.246
Data Required Time 1.394
From clk_cnt_1_s0
To clk_cnt_1_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C14[0][B] clk_cnt_1_s0/CLK
1.727 0.333 tC2Q RR 2 R7C14[0][B] clk_cnt_1_s0/Q
1.729 0.002 tNET RR 2 R7C14[0][B] n38_s/I0
2.246 0.517 tINS RF 1 R7C14[0][B] n38_s/SUM
2.246 0.000 tNET FF 1 R7C14[0][B] clk_cnt_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C14[0][B] clk_cnt_1_s0/CLK
1.394 0.000 tHld 1 R7C14[0][B] clk_cnt_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%
Arrival Data Path Delay cell: 0.517, 60.631%; route: 0.002, 0.277%; tC2Q: 0.333, 39.092%
Required Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%

Path14

Path Summary:

Slack 0.959
Data Arrival Time 2.352
Data Required Time 1.394
From clk_cnt_31_s0
To clk_cnt_31_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C19[0][B] clk_cnt_31_s0/CLK
1.727 0.333 tC2Q RF 2 R7C19[0][B] clk_cnt_31_s0/Q
1.958 0.231 tNET FF 2 R7C19[0][B] n8_s/I1
2.352 0.394 tINS FF 1 R7C19[0][B] n8_s/SUM
2.352 0.000 tNET FF 1 R7C19[0][B] clk_cnt_31_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C19[0][B] clk_cnt_31_s0/CLK
1.394 0.000 tHld 1 R7C19[0][B] clk_cnt_31_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%
Arrival Data Path Delay cell: 0.394, 41.102%; route: 0.231, 24.124%; tC2Q: 0.333, 34.773%
Required Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%

Path15

Path Summary:

Slack 0.962
Data Arrival Time 2.355
Data Required Time 1.394
From clk_cnt_5_s0
To clk_cnt_5_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C14[2][B] clk_cnt_5_s0/CLK
1.727 0.333 tC2Q RF 2 R7C14[2][B] clk_cnt_5_s0/Q
1.961 0.234 tNET FF 2 R7C14[2][B] n34_s/I1
2.355 0.394 tINS FF 1 R7C14[2][B] n34_s/SUM
2.355 0.000 tNET FF 1 R7C14[2][B] clk_cnt_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C14[2][B] clk_cnt_5_s0/CLK
1.394 0.000 tHld 1 R7C14[2][B] clk_cnt_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%
Arrival Data Path Delay cell: 0.394, 40.964%; route: 0.234, 24.379%; tC2Q: 0.333, 34.657%
Required Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%

Path16

Path Summary:

Slack 0.962
Data Arrival Time 2.355
Data Required Time 1.394
From clk_cnt_9_s0
To clk_cnt_9_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C15[1][B] clk_cnt_9_s0/CLK
1.727 0.333 tC2Q RF 2 R7C15[1][B] clk_cnt_9_s0/Q
1.961 0.234 tNET FF 2 R7C15[1][B] n30_s/I1
2.355 0.394 tINS FF 1 R7C15[1][B] n30_s/SUM
2.355 0.000 tNET FF 1 R7C15[1][B] clk_cnt_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C15[1][B] clk_cnt_9_s0/CLK
1.394 0.000 tHld 1 R7C15[1][B] clk_cnt_9_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%
Arrival Data Path Delay cell: 0.394, 40.964%; route: 0.234, 24.379%; tC2Q: 0.333, 34.657%
Required Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%

Path17

Path Summary:

Slack 0.962
Data Arrival Time 2.355
Data Required Time 1.394
From clk_cnt_15_s0
To clk_cnt_15_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C16[1][B] clk_cnt_15_s0/CLK
1.727 0.333 tC2Q RF 2 R7C16[1][B] clk_cnt_15_s0/Q
1.961 0.234 tNET FF 2 R7C16[1][B] n24_s/I1
2.355 0.394 tINS FF 1 R7C16[1][B] n24_s/SUM
2.355 0.000 tNET FF 1 R7C16[1][B] clk_cnt_15_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C16[1][B] clk_cnt_15_s0/CLK
1.394 0.000 tHld 1 R7C16[1][B] clk_cnt_15_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%
Arrival Data Path Delay cell: 0.394, 40.964%; route: 0.234, 24.379%; tC2Q: 0.333, 34.657%
Required Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%

Path18

Path Summary:

Slack 0.962
Data Arrival Time 2.355
Data Required Time 1.394
From clk_cnt_21_s0
To clk_cnt_21_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C17[1][B] clk_cnt_21_s0/CLK
1.727 0.333 tC2Q RF 2 R7C17[1][B] clk_cnt_21_s0/Q
1.961 0.234 tNET FF 2 R7C17[1][B] n18_s/I1
2.355 0.394 tINS FF 1 R7C17[1][B] n18_s/SUM
2.355 0.000 tNET FF 1 R7C17[1][B] clk_cnt_21_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C17[1][B] clk_cnt_21_s0/CLK
1.394 0.000 tHld 1 R7C17[1][B] clk_cnt_21_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%
Arrival Data Path Delay cell: 0.394, 40.964%; route: 0.234, 24.379%; tC2Q: 0.333, 34.657%
Required Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%

Path19

Path Summary:

Slack 0.962
Data Arrival Time 2.355
Data Required Time 1.394
From clk_cnt_27_s0
To clk_cnt_27_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C18[1][B] clk_cnt_27_s0/CLK
1.727 0.333 tC2Q RF 2 R7C18[1][B] clk_cnt_27_s0/Q
1.961 0.234 tNET FF 2 R7C18[1][B] n12_s/I1
2.355 0.394 tINS FF 1 R7C18[1][B] n12_s/SUM
2.355 0.000 tNET FF 1 R7C18[1][B] clk_cnt_27_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C18[1][B] clk_cnt_27_s0/CLK
1.394 0.000 tHld 1 R7C18[1][B] clk_cnt_27_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%
Arrival Data Path Delay cell: 0.394, 40.964%; route: 0.234, 24.379%; tC2Q: 0.333, 34.657%
Required Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%

Path20

Path Summary:

Slack 0.965
Data Arrival Time 2.358
Data Required Time 1.394
From clk_cnt_10_s0
To clk_cnt_10_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C15[2][A] clk_cnt_10_s0/CLK
1.727 0.333 tC2Q RR 2 R7C15[2][A] clk_cnt_10_s0/Q
1.964 0.238 tNET RR 2 R7C15[2][A] n29_s/I1
2.358 0.394 tINS RF 1 R7C15[2][A] n29_s/SUM
2.358 0.000 tNET FF 1 R7C15[2][A] clk_cnt_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C15[2][A] clk_cnt_10_s0/CLK
1.394 0.000 tHld 1 R7C15[2][A] clk_cnt_10_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%
Arrival Data Path Delay cell: 0.394, 40.833%; route: 0.238, 24.621%; tC2Q: 0.333, 34.546%
Required Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%

Path21

Path Summary:

Slack 0.965
Data Arrival Time 2.358
Data Required Time 1.394
From clk_cnt_11_s0
To clk_cnt_11_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C15[2][B] clk_cnt_11_s0/CLK
1.727 0.333 tC2Q RR 2 R7C15[2][B] clk_cnt_11_s0/Q
1.964 0.238 tNET RR 2 R7C15[2][B] n28_s/I1
2.358 0.394 tINS RF 1 R7C15[2][B] n28_s/SUM
2.358 0.000 tNET FF 1 R7C15[2][B] clk_cnt_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C15[2][B] clk_cnt_11_s0/CLK
1.394 0.000 tHld 1 R7C15[2][B] clk_cnt_11_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%
Arrival Data Path Delay cell: 0.394, 40.833%; route: 0.238, 24.621%; tC2Q: 0.333, 34.546%
Required Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%

Path22

Path Summary:

Slack 0.965
Data Arrival Time 2.358
Data Required Time 1.394
From clk_cnt_16_s0
To clk_cnt_16_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C16[2][A] clk_cnt_16_s0/CLK
1.727 0.333 tC2Q RR 2 R7C16[2][A] clk_cnt_16_s0/Q
1.964 0.238 tNET RR 2 R7C16[2][A] n23_s/I1
2.358 0.394 tINS RF 1 R7C16[2][A] n23_s/SUM
2.358 0.000 tNET FF 1 R7C16[2][A] clk_cnt_16_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C16[2][A] clk_cnt_16_s0/CLK
1.394 0.000 tHld 1 R7C16[2][A] clk_cnt_16_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%
Arrival Data Path Delay cell: 0.394, 40.833%; route: 0.238, 24.621%; tC2Q: 0.333, 34.546%
Required Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%

Path23

Path Summary:

Slack 0.965
Data Arrival Time 2.358
Data Required Time 1.394
From clk_cnt_17_s0
To clk_cnt_17_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C16[2][B] clk_cnt_17_s0/CLK
1.727 0.333 tC2Q RR 2 R7C16[2][B] clk_cnt_17_s0/Q
1.964 0.238 tNET RR 2 R7C16[2][B] n22_s/I1
2.358 0.394 tINS RF 1 R7C16[2][B] n22_s/SUM
2.358 0.000 tNET FF 1 R7C16[2][B] clk_cnt_17_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C16[2][B] clk_cnt_17_s0/CLK
1.394 0.000 tHld 1 R7C16[2][B] clk_cnt_17_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%
Arrival Data Path Delay cell: 0.394, 40.833%; route: 0.238, 24.621%; tC2Q: 0.333, 34.546%
Required Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%

Path24

Path Summary:

Slack 0.965
Data Arrival Time 2.358
Data Required Time 1.394
From clk_cnt_22_s0
To clk_cnt_22_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C17[2][A] clk_cnt_22_s0/CLK
1.727 0.333 tC2Q RR 2 R7C17[2][A] clk_cnt_22_s0/Q
1.964 0.238 tNET RR 2 R7C17[2][A] n17_s/I1
2.358 0.394 tINS RF 1 R7C17[2][A] n17_s/SUM
2.358 0.000 tNET FF 1 R7C17[2][A] clk_cnt_22_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C17[2][A] clk_cnt_22_s0/CLK
1.394 0.000 tHld 1 R7C17[2][A] clk_cnt_22_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%
Arrival Data Path Delay cell: 0.394, 40.833%; route: 0.238, 24.621%; tC2Q: 0.333, 34.546%
Required Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%

Path25

Path Summary:

Slack 0.965
Data Arrival Time 2.358
Data Required Time 1.394
From clk_cnt_23_s0
To clk_cnt_23_s0
Launch Clk sys_clk:[R]
Latch Clk sys_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C17[2][B] clk_cnt_23_s0/CLK
1.727 0.333 tC2Q RR 2 R7C17[2][B] clk_cnt_23_s0/Q
1.964 0.238 tNET RR 2 R7C17[2][B] n16_s/I1
2.358 0.394 tINS RF 1 R7C17[2][B] n16_s/SUM
2.358 0.000 tNET FF 1 R7C17[2][B] clk_cnt_23_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 sys_clk
0.000 0.000 tCL RR 1 IOR5[A] clk_ibuf/I
1.392 1.392 tINS RR 33 IOR5[A] clk_ibuf/O
1.394 0.002 tNET RR 1 R7C17[2][B] clk_cnt_23_s0/CLK
1.394 0.000 tHld 1 R7C17[2][B] clk_cnt_23_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%
Arrival Data Path Delay cell: 0.394, 40.833%; route: 0.238, 24.621%; tC2Q: 0.333, 34.546%
Required Clock Path Delay cell: 1.392, 99.886%; route: 0.002, 0.114%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 16.343
Actual Width: 17.593
Required Width: 1.250
Type: Low Pulse Width
Clock: sys_clk
Objects: clk_cnt_30_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 sys_clk
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
20.837 0.005 tNET FF clk_cnt_30_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 sys_clk
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.431 0.002 tNET RR clk_cnt_30_s0/CLK

MPW2

MPW Summary:

Slack: 16.343
Actual Width: 17.593
Required Width: 1.250
Type: Low Pulse Width
Clock: sys_clk
Objects: clk_cnt_28_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 sys_clk
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
20.837 0.005 tNET FF clk_cnt_28_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 sys_clk
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.431 0.002 tNET RR clk_cnt_28_s0/CLK

MPW3

MPW Summary:

Slack: 16.343
Actual Width: 17.593
Required Width: 1.250
Type: Low Pulse Width
Clock: sys_clk
Objects: clk_cnt_24_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 sys_clk
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
20.837 0.005 tNET FF clk_cnt_24_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 sys_clk
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.431 0.002 tNET RR clk_cnt_24_s0/CLK

MPW4

MPW Summary:

Slack: 16.343
Actual Width: 17.593
Required Width: 1.250
Type: Low Pulse Width
Clock: sys_clk
Objects: clk_cnt_16_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 sys_clk
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
20.837 0.005 tNET FF clk_cnt_16_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 sys_clk
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.431 0.002 tNET RR clk_cnt_16_s0/CLK

MPW5

MPW Summary:

Slack: 16.343
Actual Width: 17.593
Required Width: 1.250
Type: Low Pulse Width
Clock: sys_clk
Objects: clk_cnt_0_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 sys_clk
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
20.837 0.005 tNET FF clk_cnt_0_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 sys_clk
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.431 0.002 tNET RR clk_cnt_0_s0/CLK

MPW6

MPW Summary:

Slack: 16.343
Actual Width: 17.593
Required Width: 1.250
Type: Low Pulse Width
Clock: sys_clk
Objects: clk_cnt_1_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 sys_clk
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
20.837 0.005 tNET FF clk_cnt_1_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 sys_clk
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.431 0.002 tNET RR clk_cnt_1_s0/CLK

MPW7

MPW Summary:

Slack: 16.343
Actual Width: 17.593
Required Width: 1.250
Type: Low Pulse Width
Clock: sys_clk
Objects: clk_cnt_17_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 sys_clk
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
20.837 0.005 tNET FF clk_cnt_17_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 sys_clk
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.431 0.002 tNET RR clk_cnt_17_s0/CLK

MPW8

MPW Summary:

Slack: 16.343
Actual Width: 17.593
Required Width: 1.250
Type: Low Pulse Width
Clock: sys_clk
Objects: clk_cnt_2_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 sys_clk
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
20.837 0.005 tNET FF clk_cnt_2_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 sys_clk
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.431 0.002 tNET RR clk_cnt_2_s0/CLK

MPW9

MPW Summary:

Slack: 16.343
Actual Width: 17.593
Required Width: 1.250
Type: Low Pulse Width
Clock: sys_clk
Objects: clk_cnt_3_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 sys_clk
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
20.837 0.005 tNET FF clk_cnt_3_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 sys_clk
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.431 0.002 tNET RR clk_cnt_3_s0/CLK

MPW10

MPW Summary:

Slack: 16.343
Actual Width: 17.593
Required Width: 1.250
Type: Low Pulse Width
Clock: sys_clk
Objects: clk_cnt_25_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 sys_clk
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
20.837 0.005 tNET FF clk_cnt_25_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 sys_clk
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.431 0.002 tNET RR clk_cnt_25_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
33 clk_d 27.874 0.005
32 n73_5 27.874 1.963
3 led_d[0] 35.544 1.957
3 clk_cnt[25] 30.163 0.420
3 clk_cnt[0] 29.141 0.982
2 clk_cnt[27] 30.302 0.420
2 clk_cnt[31] 30.907 0.422
2 clk_cnt[28] 30.708 0.345
2 clk_cnt[29] 31.181 0.345
2 n73_10 29.018 0.821

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R7C16 20.83%
R7C15 16.67%
R7C18 15.28%
R7C17 13.89%
R7C14 12.50%
R1C19 8.33%
R5C16 5.56%
R1C1 4.17%
R3C20 2.78%
R8C15 2.78%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name sys_clk -period 37.037 -waveform {0 18.518} [get_ports {clk}]