Pin Messages

Report Title Pin Report
Design File C:\Users\ADMIN\OneDrive\Documents\OneKiwi-GW1AN-1S\impl\gwsynthesis\Led_project.vg
Physical Constraints File C:\Users\ADMIN\OneDrive\Documents\OneKiwi-GW1AN-1S\src\LED_test.cst
Timing Constraints File C:\Users\ADMIN\OneDrive\Documents\OneKiwi-GW1AN-1S\src\LED_test.sdc
Tool Version V1.9.12.02 (64-bit)
Part Number GW1AN-LV1SFN32C6/I5
Device GW1AN-1S
Device Version A
Created Time Mon Jul 27 03:59:49 2026
Legal Announcement Copyright (C)2014-2026 Gowin Semiconductor Corporation. All rights reserved.

Pin Details

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site CFG IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor BankVccio
clk - 17/2 Y in IOR5[A] GCLKT_2 LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
rst_n - 21/2 Y in IOR4[A] SI/D2 LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
led[0] - 20/2 Y out IOR4[B] SO/D1 LVCMOS33 8 NONE NA NA OFF NA OFF NA 3.3
led[1] - 23/2 Y out IOR2[A] - LVCMOS33 8 NONE NA NA OFF NA OFF NA 3.3

All Package Pins:

Loc./Bank Signal Dir. Site CFG IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor Bank Vccio
7/0 - in IOT2[A] TMS LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
6/0 - in IOT2[B] TCK LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
3/0 - in IOT3[A] TDI LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
1/0 - out IOT3[B] TDO LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
30/0 - in IOT4[A] PLL_T_in LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
26/0 - in IOT4[B] JTAGSEL_N LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
32/1 - in IOT5[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
31/1 - in IOT5[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
2/1 - in IOT6[A] RECONFIG_N LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
28/1 - in IOT6[B] DONE LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
11/1 - in IOT7[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
12/1 - in IOT7[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
27/1 - in IOT8[A] READY LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
29/1 - in IOT8[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
23/2 led[1] out IOR2[A] - LVCMOS33 8 NONE NA NA OFF NA OFF NA 3.3
22/2 - in IOR2[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
25/2 - in IOR3[A] SCLK LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
24/2 - in IOR3[B] SSPI_CS_N/D0 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
21/2 rst_n in IOR4[A] SI/D2 LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
20/2 led[0] out IOR4[B] SO/D1 LVCMOS33 8 NONE NA NA OFF NA OFF NA 3.3
17/2 clk in IOR5[A] GCLKT_2 LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
16/2 - in IOR5[B] GCLKC_2 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
19/2 - in IOR7[A] GCLKT_3/DIN/CLKHOLD_N LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
18/2 - in IOR7[B] GCLKC_3/DOUT/WE_N LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
p1-14/2 - in IOR8[B] MCLK/D4 LVCMOS33 - UP - - - - - - -
p1-9/2 - in IOR9[A] MCS_N/D5 LVCMOS33 - UP - - - - - - -
p1-13/2 - in IOR9[B] MO/D6 LVCMOS33 - UP - - - - - - -
p1-6/2 - in IOR10[A] MI/D7/MODE1 LVCMOS33 - UP - - - - - - -
15/2 - in IOR11[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
14/2 - in IOR11[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3