Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Users\ADMIN\OneDrive\Documents\OneKiwi-GW1AN-1S\src\LED_test.v
GowinSynthesis Constraints File ---
Tool Version V1.9.12.02 (64-bit)
Part Number GW1AN-LV1SFN32C6/I5
Device GW1AN-1S
Device Version A
Created Time Mon Jul 27 03:59:48 2026
Legal Announcement Copyright (C)2014-2026 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module LED_test
Synthesis Process Running parser:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 231.148MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 231.148MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 231.148MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 231.148MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 231.148MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 231.148MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 231.148MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 231.148MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 231.148MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 231.148MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 231.148MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.117s, Peak memory usage = 231.148MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.044s, Peak memory usage = 231.148MB
Generate output files:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 231.148MB
Total Time and Memory Usage CPU time = 0h 0m 0.108s, Elapsed time = 0h 0m 0.195s, Peak memory usage = 231.148MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 4
I/O Buf 4
    IBUF 2
    OBUF 2
Register 33
    DFFR 33
LUT 14
    LUT3 5
    LUT4 9
ALU 31
    ALU 31
INV 2
    INV 2

Resource Utilization Summary

Resource Usage Utilization
Logic 47(16 LUT, 31 ALU) / 1152 5%
Register 33 / 942 4%
  --Register as Latch 0 / 942 0%
  --Register as FF 33 / 942 4%
BSRAM 0 / 4 0%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk Base 20.000 50.000 0.000 10.000 clk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 50.000(MHz) 100.127(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 10.013
Data Arrival Time 10.313
Data Required Time 20.326
From clk_cnt_5_s0
To led_0_s3
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 33 clk_ibuf/O
0.726 0.726 tNET RR 1 clk_cnt_5_s0/CLK
1.184 0.458 tC2Q RF 2 clk_cnt_5_s0/Q
2.144 0.960 tNET FF 1 n73_s12/I1
3.243 1.099 tINS FF 1 n73_s12/F
4.203 0.960 tNET FF 1 n73_s5/I1
5.302 1.099 tINS FF 1 n73_s5/F
6.262 0.960 tNET FF 1 n73_s2/I1
7.361 1.099 tINS FF 2 n73_s2/F
8.321 0.960 tNET FF 1 n140_s3/I0
9.353 1.032 tINS FF 1 n140_s3/F
10.313 0.960 tNET FF 1 led_0_s3/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 33 clk_ibuf/O
20.726 0.726 tNET RR 1 led_0_s3/CLK
20.326 -0.400 tSu 1 led_0_s3
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 4.329, 45.153%; route: 4.800, 50.066%; tC2Q: 0.458, 4.781%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 2

Path Summary:
Slack 10.609
Data Arrival Time 10.073
Data Required Time 20.683
From clk_cnt_5_s0
To clk_cnt_31_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 33 clk_ibuf/O
0.726 0.726 tNET RR 1 clk_cnt_5_s0/CLK
1.184 0.458 tC2Q RF 2 clk_cnt_5_s0/Q
2.144 0.960 tNET FF 1 n73_s12/I1
3.243 1.099 tINS FF 1 n73_s12/F
4.203 0.960 tNET FF 1 n73_s5/I1
5.302 1.099 tINS FF 1 n73_s5/F
6.262 0.960 tNET FF 1 n73_s2/I1
7.361 1.099 tINS FF 2 n73_s2/F
8.321 0.960 tNET FF 1 n73_s1/I0
9.347 1.026 tINS FR 32 n73_s1/F
10.073 0.726 tNET RR 1 clk_cnt_31_s0/RESET
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 33 clk_ibuf/O
20.726 0.726 tNET RR 1 clk_cnt_31_s0/CLK
20.683 -0.043 tSu 1 clk_cnt_31_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 4.323, 46.248%; route: 4.566, 48.849%; tC2Q: 0.458, 4.903%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 3

Path Summary:
Slack 10.609
Data Arrival Time 10.073
Data Required Time 20.683
From clk_cnt_5_s0
To clk_cnt_0_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 33 clk_ibuf/O
0.726 0.726 tNET RR 1 clk_cnt_5_s0/CLK
1.184 0.458 tC2Q RF 2 clk_cnt_5_s0/Q
2.144 0.960 tNET FF 1 n73_s12/I1
3.243 1.099 tINS FF 1 n73_s12/F
4.203 0.960 tNET FF 1 n73_s5/I1
5.302 1.099 tINS FF 1 n73_s5/F
6.262 0.960 tNET FF 1 n73_s2/I1
7.361 1.099 tINS FF 2 n73_s2/F
8.321 0.960 tNET FF 1 n73_s1/I0
9.347 1.026 tINS FR 32 n73_s1/F
10.073 0.726 tNET RR 1 clk_cnt_0_s0/RESET
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 33 clk_ibuf/O
20.726 0.726 tNET RR 1 clk_cnt_0_s0/CLK
20.683 -0.043 tSu 1 clk_cnt_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 4.323, 46.248%; route: 4.566, 48.849%; tC2Q: 0.458, 4.903%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 4

Path Summary:
Slack 10.609
Data Arrival Time 10.073
Data Required Time 20.683
From clk_cnt_5_s0
To clk_cnt_1_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 33 clk_ibuf/O
0.726 0.726 tNET RR 1 clk_cnt_5_s0/CLK
1.184 0.458 tC2Q RF 2 clk_cnt_5_s0/Q
2.144 0.960 tNET FF 1 n73_s12/I1
3.243 1.099 tINS FF 1 n73_s12/F
4.203 0.960 tNET FF 1 n73_s5/I1
5.302 1.099 tINS FF 1 n73_s5/F
6.262 0.960 tNET FF 1 n73_s2/I1
7.361 1.099 tINS FF 2 n73_s2/F
8.321 0.960 tNET FF 1 n73_s1/I0
9.347 1.026 tINS FR 32 n73_s1/F
10.073 0.726 tNET RR 1 clk_cnt_1_s0/RESET
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 33 clk_ibuf/O
20.726 0.726 tNET RR 1 clk_cnt_1_s0/CLK
20.683 -0.043 tSu 1 clk_cnt_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 4.323, 46.248%; route: 4.566, 48.849%; tC2Q: 0.458, 4.903%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 5

Path Summary:
Slack 10.609
Data Arrival Time 10.073
Data Required Time 20.683
From clk_cnt_5_s0
To clk_cnt_2_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 33 clk_ibuf/O
0.726 0.726 tNET RR 1 clk_cnt_5_s0/CLK
1.184 0.458 tC2Q RF 2 clk_cnt_5_s0/Q
2.144 0.960 tNET FF 1 n73_s12/I1
3.243 1.099 tINS FF 1 n73_s12/F
4.203 0.960 tNET FF 1 n73_s5/I1
5.302 1.099 tINS FF 1 n73_s5/F
6.262 0.960 tNET FF 1 n73_s2/I1
7.361 1.099 tINS FF 2 n73_s2/F
8.321 0.960 tNET FF 1 n73_s1/I0
9.347 1.026 tINS FR 32 n73_s1/F
10.073 0.726 tNET RR 1 clk_cnt_2_s0/RESET
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 33 clk_ibuf/O
20.726 0.726 tNET RR 1 clk_cnt_2_s0/CLK
20.683 -0.043 tSu 1 clk_cnt_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 4.323, 46.248%; route: 4.566, 48.849%; tC2Q: 0.458, 4.903%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%