Timing Messages

Report Title	Timing Analysis Report
Design File	C:\Users\ADMIN\OneDrive\Documents\Button_filtering_counterl_Led\impl\gwsynthesis\key_led.vg
Physical Constraints File	C:\Users\ADMIN\OneDrive\Documents\Button_filtering_counterl_Led\src\key_led.cst
Timing Constraint File	---
Tool Version	V1.9.12.02 (64-bit)
Part Number	GW1AN-LV1SFN32C6/I5
Device	GW1AN-1S
Device Version	A
Created Time	Mon Jul 27 04:28:46 2026
Legal Announcement	Copyright (C)2014-2026 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 1.14V 85C C6/I5
Hold Delay Model	Fast 1.26V 0C C6/I5
Numbers of Paths Analyzed	142
Numbers of Endpoints Analyzed	142
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	Clk	Base	20.000	50.000	0.000	10.000			Clk_ibuf/I

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	Clk	50.000(MHz)	159.669(MHz)	4	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
Clk	Setup	0.000	0
Clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	13.737	key_filter1/cnt_6_s0/Q	key_filter1/cnt_13_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	5.863
2	13.762	key_filter0/cnt_0_s0/Q	key_filter0/cnt_16_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	5.838
3	13.859	key_filter0/cnt_0_s0/Q	key_filter0/cnt_17_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	5.741
4	13.909	key_filter0/cnt_13_s0/Q	key_filter0/cnt_18_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	5.691
5	13.972	key_filter0/cnt_0_s0/Q	key_filter0/cnt_15_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	5.628
6	14.055	key_filter0/cnt_0_s0/Q	key_filter0/cnt_19_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	5.545
7	14.289	key_filter1/cnt_6_s0/Q	key_filter1/cnt_16_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	5.311
8	14.325	key_filter0/cnt_17_s0/Q	key_filter0/cnt_full_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	5.275
9	14.344	key_filter0/cnt_0_s0/Q	key_filter0/cnt_13_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	5.256
10	14.344	key_filter0/cnt_0_s0/Q	key_filter0/cnt_14_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	5.256
11	14.431	key_filter0/cnt_0_s0/Q	key_filter0/cnt_11_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	5.169
12	14.555	key_filter1/cnt_19_s0/Q	key_filter1/cnt_full_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	5.045
13	14.612	key_filter0/cnt_7_s0/Q	key_filter0/cnt_12_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	4.988
14	14.619	key_filter1/cnt_6_s0/Q	key_filter1/cnt_14_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	4.981
15	14.705	key_filter1/cnt_6_s0/Q	key_filter1/cnt_15_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	4.895
16	14.705	key_filter1/cnt_6_s0/Q	key_filter1/cnt_17_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	4.895
17	14.705	key_filter1/cnt_6_s0/Q	key_filter1/cnt_18_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	4.895
18	14.835	key_filter1/cnt_4_s0/Q	key_filter1/cnt_6_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	4.765
19	14.839	key_filter1/cnt_6_s0/Q	key_filter1/cnt_10_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	4.761
20	14.839	key_filter1/cnt_6_s0/Q	key_filter1/cnt_11_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	4.761
21	15.046	key_filter0/cnt_0_s0/Q	key_filter0/cnt_9_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	4.554
22	15.046	key_filter0/cnt_0_s0/Q	key_filter0/cnt_10_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	4.554
23	15.101	key_filter1/key_tmpa_s0/Q	key_filter1/en_cnt_s2/D	Clk:[R]	Clk:[R]	20.000	0.000	4.499
24	15.119	key_filter1/cnt_6_s0/Q	key_filter1/cnt_19_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	4.481
25	15.182	key_filter0/cnt_0_s0/Q	key_filter0/cnt_6_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	4.418

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.708	key_filter1/cnt_3_s0/Q	key_filter1/cnt_3_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.708
2	0.708	key_filter1/cnt_6_s0/Q	key_filter1/cnt_6_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.708
3	0.708	key_filter1/cnt_7_s0/Q	key_filter1/cnt_7_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.708
4	0.708	key_filter1/cnt_14_s0/Q	key_filter1/cnt_14_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.708
5	0.708	key_filter1/cnt_18_s0/Q	key_filter1/cnt_18_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.708
6	0.708	key_filter0/key_state_s5/Q	key_filter0/key_state_s5/D	Clk:[R]	Clk:[R]	0.000	0.000	0.708
7	0.708	key_filter0/cnt_2_s0/Q	key_filter0/cnt_2_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.708
8	0.708	key_filter0/cnt_7_s0/Q	key_filter0/cnt_7_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.708
9	0.708	key_filter0/cnt_9_s0/Q	key_filter0/cnt_9_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.708
10	0.708	key_filter0/cnt_16_s0/Q	key_filter0/cnt_16_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.708
11	0.709	led_ctrl0/led_r_0_s1/Q	led_ctrl0/led_r_0_s1/D	Clk:[R]	Clk:[R]	0.000	0.000	0.709
12	0.709	key_filter1/state.IDEL_s0/Q	key_filter1/state.IDEL_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.709
13	0.709	key_filter1/cnt_0_s0/Q	key_filter1/cnt_0_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.709
14	0.709	key_filter1/cnt_10_s0/Q	key_filter1/cnt_10_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.709
15	0.709	key_filter0/cnt_5_s0/Q	key_filter0/cnt_5_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.709
16	0.709	key_filter0/cnt_11_s0/Q	key_filter0/cnt_11_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.709
17	0.709	key_filter0/cnt_12_s0/Q	key_filter0/cnt_12_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.709
18	0.709	key_filter0/cnt_14_s0/Q	key_filter0/cnt_14_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.709
19	0.709	key_filter0/state.DOWN_s0/Q	key_filter0/state.DOWN_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.709
20	0.710	key_filter0/cnt_8_s0/Q	key_filter0/cnt_8_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.710
21	0.892	key_filter1/cnt_13_s0/Q	key_filter1/cnt_13_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.892
22	0.892	key_filter1/cnt_15_s0/Q	key_filter1/cnt_15_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.892
23	0.892	key_filter1/cnt_16_s0/Q	key_filter1/cnt_16_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.892
24	0.892	key_filter0/cnt_19_s0/Q	key_filter0/cnt_19_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.892
25	0.893	key_filter0/cnt_1_s0/Q	key_filter0/cnt_1_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.893

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	6.663	7.913	1.250	High Pulse Width	Clk	key_filter0/key_in_sb_s0
2	6.663	7.913	1.250	High Pulse Width	Clk	key_filter0/key_tmpa_s0
3	6.663	7.913	1.250	High Pulse Width	Clk	key_filter0/state.DOWN_s0
4	6.663	7.913	1.250	High Pulse Width	Clk	key_filter0/cnt_16_s0
5	6.663	7.913	1.250	High Pulse Width	Clk	key_filter0/cnt_8_s0
6	6.663	7.913	1.250	High Pulse Width	Clk	key_filter0/key_state_s5
7	6.663	7.913	1.250	High Pulse Width	Clk	key_filter1/key_state_s5
8	6.663	7.913	1.250	High Pulse Width	Clk	key_filter1/key_flag_s5
9	6.663	7.913	1.250	High Pulse Width	Clk	key_filter0/key_flag_s5
10	6.663	7.913	1.250	High Pulse Width	Clk	key_filter1/state.FILTER1_s1

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	13.737
Data Arrival Time	10.095
Data Required Time	23.832
From	key_filter1/cnt_6_s0
To	key_filter1/cnt_13_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
4.232	0.002	tNET	RR	1	R7C16[1][A]	key_filter1/cnt_6_s0/CLK
4.690	0.458	tC2Q	RF	4	R7C16[1][A]	key_filter1/cnt_6_s0/Q
5.523	0.833	tNET	FF	1	R7C14[3][B]	key_filter1/n103_s3/I2
6.622	1.099	tINS	FF	4	R7C14[3][B]	key_filter1/n103_s3/F
6.638	0.016	tNET	FF	1	R7C14[2][B]	key_filter1/n98_s2/I2
7.670	1.032	tINS	FF	7	R7C14[2][B]	key_filter1/n98_s2/F
8.996	1.325	tNET	FF	1	R5C13[2][A]	key_filter1/n98_s1/I1
10.095	1.099	tINS	FF	1	R5C13[2][A]	key_filter1/n98_s1/F
10.095	0.000	tNET	FF	1	R5C13[2][A]	key_filter1/cnt_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
24.232	0.002	tNET	RR	1	R5C13[2][A]	key_filter1/cnt_13_s0/CLK
23.832	-0.400	tSu		1	R5C13[2][A]	key_filter1/cnt_13_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%
Arrival Data Path Delay	cell: 3.230, 55.092%; route: 2.175, 37.091%; tC2Q: 0.458, 7.817%
Required Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%

Path2

Path Summary:

Slack	13.762
Data Arrival Time	10.070
Data Required Time	23.832
From	key_filter0/cnt_0_s0
To	key_filter0/cnt_16_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
4.232	0.002	tNET	RR	1	R5C7[2][B]	key_filter0/cnt_0_s0/CLK
4.690	0.458	tC2Q	RF	5	R5C7[2][B]	key_filter0/cnt_0_s0/Q
5.848	1.158	tNET	FF	1	R4C8[2][A]	key_filter0/n106_s2/I0
6.474	0.626	tINS	FF	7	R4C8[2][A]	key_filter0/n106_s2/F
7.806	1.332	tNET	FF	1	R5C10[2][A]	key_filter0/n92_s2/I1
8.608	0.802	tINS	FR	7	R5C10[2][A]	key_filter0/n92_s2/F
9.038	0.431	tNET	RR	1	R4C10[1][A]	key_filter0/n95_s1/I0
10.070	1.032	tINS	RF	1	R4C10[1][A]	key_filter0/n95_s1/F
10.070	0.000	tNET	FF	1	R4C10[1][A]	key_filter0/cnt_16_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
24.232	0.002	tNET	RR	1	R4C10[1][A]	key_filter0/cnt_16_s0/CLK
23.832	-0.400	tSu		1	R4C10[1][A]	key_filter0/cnt_16_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%
Arrival Data Path Delay	cell: 2.460, 42.136%; route: 2.920, 50.014%; tC2Q: 0.458, 7.850%
Required Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%

Path3

Path Summary:

Slack	13.859
Data Arrival Time	9.973
Data Required Time	23.832
From	key_filter0/cnt_0_s0
To	key_filter0/cnt_17_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
4.232	0.002	tNET	RR	1	R5C7[2][B]	key_filter0/cnt_0_s0/CLK
4.690	0.458	tC2Q	RF	5	R5C7[2][B]	key_filter0/cnt_0_s0/Q
5.848	1.158	tNET	FF	1	R4C8[2][A]	key_filter0/n106_s2/I0
6.474	0.626	tINS	FF	7	R4C8[2][A]	key_filter0/n106_s2/F
7.806	1.332	tNET	FF	1	R5C10[2][A]	key_filter0/n92_s2/I1
8.628	0.822	tINS	FF	7	R5C10[2][A]	key_filter0/n92_s2/F
9.151	0.523	tNET	FF	1	R5C9[2][B]	key_filter0/n94_s1/I0
9.973	0.822	tINS	FF	1	R5C9[2][B]	key_filter0/n94_s1/F
9.973	0.000	tNET	FF	1	R5C9[2][B]	key_filter0/cnt_17_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
24.232	0.002	tNET	RR	1	R5C9[2][B]	key_filter0/cnt_17_s0/CLK
23.832	-0.400	tSu		1	R5C9[2][B]	key_filter0/cnt_17_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%
Arrival Data Path Delay	cell: 2.270, 39.542%; route: 3.012, 52.474%; tC2Q: 0.458, 7.984%
Required Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%

Path4

Path Summary:

Slack	13.909
Data Arrival Time	9.923
Data Required Time	23.832
From	key_filter0/cnt_13_s0
To	key_filter0/cnt_18_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
4.232	0.002	tNET	RR	1	R5C10[0][B]	key_filter0/cnt_13_s0/CLK
4.690	0.458	tC2Q	RF	6	R5C10[0][B]	key_filter0/cnt_13_s0/Q
5.506	0.816	tNET	FF	1	R4C9[3][B]	key_filter0/n94_s2/I0
6.538	1.032	tINS	FF	3	R4C9[3][B]	key_filter0/n94_s2/F
7.522	0.985	tNET	FF	1	R5C10[3][A]	key_filter0/n93_s2/I1
8.554	1.032	tINS	FF	1	R5C10[3][A]	key_filter0/n93_s2/F
8.891	0.336	tNET	FF	1	R5C10[1][B]	key_filter0/n93_s1/I1
9.923	1.032	tINS	FF	1	R5C10[1][B]	key_filter0/n93_s1/F
9.923	0.000	tNET	FF	1	R5C10[1][B]	key_filter0/cnt_18_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
24.232	0.002	tNET	RR	1	R5C10[1][B]	key_filter0/cnt_18_s0/CLK
23.832	-0.400	tSu		1	R5C10[1][B]	key_filter0/cnt_18_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%
Arrival Data Path Delay	cell: 3.096, 54.402%; route: 2.137, 37.544%; tC2Q: 0.458, 8.054%
Required Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%

Path5

Path Summary:

Slack	13.972
Data Arrival Time	9.860
Data Required Time	23.832
From	key_filter0/cnt_0_s0
To	key_filter0/cnt_15_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
4.232	0.002	tNET	RR	1	R5C7[2][B]	key_filter0/cnt_0_s0/CLK
4.690	0.458	tC2Q	RF	5	R5C7[2][B]	key_filter0/cnt_0_s0/Q
5.848	1.158	tNET	FF	1	R4C8[2][A]	key_filter0/n106_s2/I0
6.474	0.626	tINS	FF	7	R4C8[2][A]	key_filter0/n106_s2/F
7.806	1.332	tNET	FF	1	R5C10[2][A]	key_filter0/n92_s2/I1
8.608	0.802	tINS	FR	7	R5C10[2][A]	key_filter0/n92_s2/F
9.038	0.431	tNET	RR	1	R4C10[0][B]	key_filter0/n96_s1/I0
9.860	0.822	tINS	RF	1	R4C10[0][B]	key_filter0/n96_s1/F
9.860	0.000	tNET	FF	1	R4C10[0][B]	key_filter0/cnt_15_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
24.232	0.002	tNET	RR	1	R4C10[0][B]	key_filter0/cnt_15_s0/CLK
23.832	-0.400	tSu		1	R4C10[0][B]	key_filter0/cnt_15_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%
Arrival Data Path Delay	cell: 2.250, 39.977%; route: 2.920, 51.880%; tC2Q: 0.458, 8.143%
Required Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%

Path6

Path Summary:

Slack	14.055
Data Arrival Time	9.777
Data Required Time	23.832
From	key_filter0/cnt_0_s0
To	key_filter0/cnt_19_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
4.232	0.002	tNET	RR	1	R5C7[2][B]	key_filter0/cnt_0_s0/CLK
4.690	0.458	tC2Q	RF	5	R5C7[2][B]	key_filter0/cnt_0_s0/Q
5.848	1.158	tNET	FF	1	R4C8[2][A]	key_filter0/n106_s2/I0
6.474	0.626	tINS	FF	7	R4C8[2][A]	key_filter0/n106_s2/F
7.806	1.332	tNET	FF	1	R5C10[2][A]	key_filter0/n92_s2/I1
8.628	0.822	tINS	FF	7	R5C10[2][A]	key_filter0/n92_s2/F
9.151	0.523	tNET	FF	1	R4C10[2][A]	key_filter0/n92_s1/I0
9.777	0.626	tINS	FF	1	R4C10[2][A]	key_filter0/n92_s1/F
9.777	0.000	tNET	FF	1	R4C10[2][A]	key_filter0/cnt_19_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
24.232	0.002	tNET	RR	1	R4C10[2][A]	key_filter0/cnt_19_s0/CLK
23.832	-0.400	tSu		1	R4C10[2][A]	key_filter0/cnt_19_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%
Arrival Data Path Delay	cell: 2.074, 37.405%; route: 3.012, 54.329%; tC2Q: 0.458, 8.266%
Required Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%

Path7

Path Summary:

Slack	14.289
Data Arrival Time	9.543
Data Required Time	23.832
From	key_filter1/cnt_6_s0
To	key_filter1/cnt_16_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
4.232	0.002	tNET	RR	1	R7C16[1][A]	key_filter1/cnt_6_s0/CLK
4.690	0.458	tC2Q	RF	4	R7C16[1][A]	key_filter1/cnt_6_s0/Q
5.523	0.833	tNET	FF	1	R7C14[3][B]	key_filter1/n103_s3/I2
6.622	1.099	tINS	FF	4	R7C14[3][B]	key_filter1/n103_s3/F
6.638	0.016	tNET	FF	1	R7C14[2][B]	key_filter1/n98_s2/I2
7.670	1.032	tINS	FF	7	R7C14[2][B]	key_filter1/n98_s2/F
8.511	0.841	tNET	FF	1	R5C14[2][A]	key_filter1/n95_s1/I0
9.543	1.032	tINS	FF	1	R5C14[2][A]	key_filter1/n95_s1/F
9.543	0.000	tNET	FF	1	R5C14[2][A]	key_filter1/cnt_16_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
24.232	0.002	tNET	RR	1	R5C14[2][A]	key_filter1/cnt_16_s0/CLK
23.832	-0.400	tSu		1	R5C14[2][A]	key_filter1/cnt_16_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%
Arrival Data Path Delay	cell: 3.163, 59.551%; route: 1.690, 31.820%; tC2Q: 0.458, 8.629%
Required Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%

Path8

Path Summary:

Slack	14.325
Data Arrival Time	9.507
Data Required Time	23.832
From	key_filter0/cnt_17_s0
To	key_filter0/cnt_full_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
4.232	0.002	tNET	RR	1	R5C9[2][B]	key_filter0/cnt_17_s0/CLK
4.690	0.458	tC2Q	RF	4	R5C9[2][B]	key_filter0/cnt_17_s0/Q
5.518	0.828	tNET	FF	1	R4C9[3][A]	key_filter0/n148_s6/I1
6.544	1.026	tINS	FR	1	R4C9[3][A]	key_filter0/n148_s6/F
6.963	0.419	tNET	RR	1	R5C9[3][B]	key_filter0/n148_s4/I3
7.989	1.026	tINS	RR	1	R5C9[3][B]	key_filter0/n148_s4/F
8.408	0.419	tNET	RR	1	R4C9[1][A]	key_filter0/n148_s1/I3
9.507	1.099	tINS	RF	1	R4C9[1][A]	key_filter0/n148_s1/F
9.507	0.000	tNET	FF	1	R4C9[1][A]	key_filter0/cnt_full_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
24.232	0.002	tNET	RR	1	R4C9[1][A]	key_filter0/cnt_full_s0/CLK
23.832	-0.400	tSu		1	R4C9[1][A]	key_filter0/cnt_full_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%
Arrival Data Path Delay	cell: 3.151, 59.737%; route: 1.665, 31.574%; tC2Q: 0.458, 8.689%
Required Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%

Path9

Path Summary:

Slack	14.344
Data Arrival Time	9.488
Data Required Time	23.832
From	key_filter0/cnt_0_s0
To	key_filter0/cnt_13_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
4.232	0.002	tNET	RR	1	R5C7[2][B]	key_filter0/cnt_0_s0/CLK
4.690	0.458	tC2Q	RF	5	R5C7[2][B]	key_filter0/cnt_0_s0/Q
5.848	1.158	tNET	FF	1	R4C8[2][A]	key_filter0/n106_s2/I0
6.474	0.626	tINS	FF	7	R4C8[2][A]	key_filter0/n106_s2/F
7.806	1.332	tNET	FF	1	R5C10[2][A]	key_filter0/n92_s2/I1
8.628	0.822	tINS	FF	7	R5C10[2][A]	key_filter0/n92_s2/F
8.666	0.038	tNET	FF	1	R5C10[0][B]	key_filter0/n98_s1/I1
9.488	0.822	tINS	FF	1	R5C10[0][B]	key_filter0/n98_s1/F
9.488	0.000	tNET	FF	1	R5C10[0][B]	key_filter0/cnt_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
24.232	0.002	tNET	RR	1	R5C10[0][B]	key_filter0/cnt_13_s0/CLK
23.832	-0.400	tSu		1	R5C10[0][B]	key_filter0/cnt_13_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%
Arrival Data Path Delay	cell: 2.270, 43.187%; route: 2.528, 48.093%; tC2Q: 0.458, 8.720%
Required Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%

Path10

Path Summary:

Slack	14.344
Data Arrival Time	9.488
Data Required Time	23.832
From	key_filter0/cnt_0_s0
To	key_filter0/cnt_14_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
4.232	0.002	tNET	RR	1	R5C7[2][B]	key_filter0/cnt_0_s0/CLK
4.690	0.458	tC2Q	RF	5	R5C7[2][B]	key_filter0/cnt_0_s0/Q
5.848	1.158	tNET	FF	1	R4C8[2][A]	key_filter0/n106_s2/I0
6.474	0.626	tINS	FF	7	R4C8[2][A]	key_filter0/n106_s2/F
7.806	1.332	tNET	FF	1	R5C10[2][A]	key_filter0/n92_s2/I1
8.628	0.822	tINS	FF	7	R5C10[2][A]	key_filter0/n92_s2/F
8.666	0.038	tNET	FF	1	R5C10[1][A]	key_filter0/n97_s1/I1
9.488	0.822	tINS	FF	1	R5C10[1][A]	key_filter0/n97_s1/F
9.488	0.000	tNET	FF	1	R5C10[1][A]	key_filter0/cnt_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
24.232	0.002	tNET	RR	1	R5C10[1][A]	key_filter0/cnt_14_s0/CLK
23.832	-0.400	tSu		1	R5C10[1][A]	key_filter0/cnt_14_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%
Arrival Data Path Delay	cell: 2.270, 43.187%; route: 2.528, 48.093%; tC2Q: 0.458, 8.720%
Required Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%

Path11

Path Summary:

Slack	14.431
Data Arrival Time	9.401
Data Required Time	23.832
From	key_filter0/cnt_0_s0
To	key_filter0/cnt_11_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
4.232	0.002	tNET	RR	1	R5C7[2][B]	key_filter0/cnt_0_s0/CLK
4.690	0.458	tC2Q	RF	5	R5C7[2][B]	key_filter0/cnt_0_s0/Q
5.848	1.158	tNET	FF	1	R4C8[2][A]	key_filter0/n106_s2/I0
6.474	0.626	tINS	FF	7	R4C8[2][A]	key_filter0/n106_s2/F
7.321	0.847	tNET	FF	1	R5C9[3][A]	key_filter0/n100_s3/I0
7.946	0.625	tINS	FR	3	R5C9[3][A]	key_filter0/n100_s3/F
8.369	0.423	tNET	RR	1	R5C10[0][A]	key_filter0/n100_s1/I1
9.401	1.032	tINS	RF	1	R5C10[0][A]	key_filter0/n100_s1/F
9.401	0.000	tNET	FF	1	R5C10[0][A]	key_filter0/cnt_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
24.232	0.002	tNET	RR	1	R5C10[0][A]	key_filter0/cnt_11_s0/CLK
23.832	-0.400	tSu		1	R5C10[0][A]	key_filter0/cnt_11_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%
Arrival Data Path Delay	cell: 2.283, 44.167%; route: 2.428, 46.966%; tC2Q: 0.458, 8.867%
Required Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%

Path12

Path Summary:

Slack	14.555
Data Arrival Time	9.277
Data Required Time	23.832
From	key_filter1/cnt_19_s0
To	key_filter1/cnt_full_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
4.232	0.002	tNET	RR	1	R7C15[1][B]	key_filter1/cnt_19_s0/CLK
4.690	0.458	tC2Q	RF	2	R7C15[1][B]	key_filter1/cnt_19_s0/Q
5.828	1.138	tNET	FF	1	R5C14[0][B]	key_filter1/n148_s5/I3
6.650	0.822	tINS	FF	1	R5C14[0][B]	key_filter1/n148_s5/F
6.655	0.005	tNET	FF	1	R5C14[2][B]	key_filter1/n148_s2/I3
7.754	1.099	tINS	FF	1	R5C14[2][B]	key_filter1/n148_s2/F
8.245	0.490	tNET	FF	1	R7C14[1][A]	key_filter1/n148_s1/I1
9.277	1.032	tINS	FF	1	R7C14[1][A]	key_filter1/n148_s1/F
9.277	0.000	tNET	FF	1	R7C14[1][A]	key_filter1/cnt_full_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
24.232	0.002	tNET	RR	1	R7C14[1][A]	key_filter1/cnt_full_s0/CLK
23.832	-0.400	tSu		1	R7C14[1][A]	key_filter1/cnt_full_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%
Arrival Data Path Delay	cell: 2.953, 58.536%; route: 1.633, 32.378%; tC2Q: 0.458, 9.085%
Required Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%

Path13

Path Summary:

Slack	14.612
Data Arrival Time	9.220
Data Required Time	23.832
From	key_filter0/cnt_7_s0
To	key_filter0/cnt_12_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
4.232	0.002	tNET	RR	1	R5C8[1][A]	key_filter0/cnt_7_s0/CLK
4.690	0.458	tC2Q	RF	3	R5C8[1][A]	key_filter0/cnt_7_s0/Q
5.502	0.812	tNET	FF	1	R5C9[2][A]	key_filter0/n92_s5/I3
6.324	0.822	tINS	FF	4	R5C9[2][A]	key_filter0/n92_s5/F
7.150	0.827	tNET	FF	1	R4C10[2][B]	key_filter0/n99_s2/I2
8.182	1.032	tINS	FF	1	R4C10[2][B]	key_filter0/n99_s2/F
8.188	0.005	tNET	FF	1	R4C10[0][A]	key_filter0/n99_s1/I0
9.220	1.032	tINS	FF	1	R4C10[0][A]	key_filter0/n99_s1/F
9.220	0.000	tNET	FF	1	R4C10[0][A]	key_filter0/cnt_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
24.232	0.002	tNET	RR	1	R4C10[0][A]	key_filter0/cnt_12_s0/CLK
23.832	-0.400	tSu		1	R4C10[0][A]	key_filter0/cnt_12_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%
Arrival Data Path Delay	cell: 2.886, 57.858%; route: 1.644, 32.953%; tC2Q: 0.458, 9.189%
Required Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%

Path14

Path Summary:

Slack	14.619
Data Arrival Time	9.212
Data Required Time	23.832
From	key_filter1/cnt_6_s0
To	key_filter1/cnt_14_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
4.232	0.002	tNET	RR	1	R7C16[1][A]	key_filter1/cnt_6_s0/CLK
4.690	0.458	tC2Q	RF	4	R7C16[1][A]	key_filter1/cnt_6_s0/Q
5.523	0.833	tNET	FF	1	R7C14[3][B]	key_filter1/n103_s3/I2
6.622	1.099	tINS	FF	4	R7C14[3][B]	key_filter1/n103_s3/F
6.638	0.016	tNET	FF	1	R7C14[2][B]	key_filter1/n98_s2/I2
7.670	1.032	tINS	FF	7	R7C14[2][B]	key_filter1/n98_s2/F
8.180	0.510	tNET	FF	1	R5C14[1][A]	key_filter1/n97_s1/I1
9.212	1.032	tINS	FF	1	R5C14[1][A]	key_filter1/n97_s1/F
9.212	0.000	tNET	FF	1	R5C14[1][A]	key_filter1/cnt_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
24.232	0.002	tNET	RR	1	R5C14[1][A]	key_filter1/cnt_14_s0/CLK
23.832	-0.400	tSu		1	R5C14[1][A]	key_filter1/cnt_14_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%
Arrival Data Path Delay	cell: 3.163, 63.507%; route: 1.359, 27.291%; tC2Q: 0.458, 9.202%
Required Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%

Path15

Path Summary:

Slack	14.705
Data Arrival Time	9.127
Data Required Time	23.832
From	key_filter1/cnt_6_s0
To	key_filter1/cnt_15_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
4.232	0.002	tNET	RR	1	R7C16[1][A]	key_filter1/cnt_6_s0/CLK
4.690	0.458	tC2Q	RF	4	R7C16[1][A]	key_filter1/cnt_6_s0/Q
5.523	0.833	tNET	FF	1	R7C14[3][B]	key_filter1/n103_s3/I2
6.622	1.099	tINS	FF	4	R7C14[3][B]	key_filter1/n103_s3/F
6.638	0.016	tNET	FF	1	R7C14[2][B]	key_filter1/n98_s2/I2
7.664	1.026	tINS	FR	7	R7C14[2][B]	key_filter1/n98_s2/F
8.095	0.431	tNET	RR	1	R7C15[2][A]	key_filter1/n96_s1/I0
9.127	1.032	tINS	RF	1	R7C15[2][A]	key_filter1/n96_s1/F
9.127	0.000	tNET	FF	1	R7C15[2][A]	key_filter1/cnt_15_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
24.232	0.002	tNET	RR	1	R7C15[2][A]	key_filter1/cnt_15_s0/CLK
23.832	-0.400	tSu		1	R7C15[2][A]	key_filter1/cnt_15_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%
Arrival Data Path Delay	cell: 3.157, 64.492%; route: 1.280, 26.144%; tC2Q: 0.458, 9.363%
Required Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%

Path16

Path Summary:

Slack	14.705
Data Arrival Time	9.127
Data Required Time	23.832
From	key_filter1/cnt_6_s0
To	key_filter1/cnt_17_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
4.232	0.002	tNET	RR	1	R7C16[1][A]	key_filter1/cnt_6_s0/CLK
4.690	0.458	tC2Q	RF	4	R7C16[1][A]	key_filter1/cnt_6_s0/Q
5.523	0.833	tNET	FF	1	R7C14[3][B]	key_filter1/n103_s3/I2
6.622	1.099	tINS	FF	4	R7C14[3][B]	key_filter1/n103_s3/F
6.638	0.016	tNET	FF	1	R7C14[2][B]	key_filter1/n98_s2/I2
7.664	1.026	tINS	FR	7	R7C14[2][B]	key_filter1/n98_s2/F
8.095	0.431	tNET	RR	1	R7C15[0][B]	key_filter1/n94_s1/I0
9.127	1.032	tINS	RF	1	R7C15[0][B]	key_filter1/n94_s1/F
9.127	0.000	tNET	FF	1	R7C15[0][B]	key_filter1/cnt_17_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
24.232	0.002	tNET	RR	1	R7C15[0][B]	key_filter1/cnt_17_s0/CLK
23.832	-0.400	tSu		1	R7C15[0][B]	key_filter1/cnt_17_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%
Arrival Data Path Delay	cell: 3.157, 64.492%; route: 1.280, 26.144%; tC2Q: 0.458, 9.363%
Required Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%

Path17

Path Summary:

Slack	14.705
Data Arrival Time	9.127
Data Required Time	23.832
From	key_filter1/cnt_6_s0
To	key_filter1/cnt_18_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
4.232	0.002	tNET	RR	1	R7C16[1][A]	key_filter1/cnt_6_s0/CLK
4.690	0.458	tC2Q	RF	4	R7C16[1][A]	key_filter1/cnt_6_s0/Q
5.523	0.833	tNET	FF	1	R7C14[3][B]	key_filter1/n103_s3/I2
6.622	1.099	tINS	FF	4	R7C14[3][B]	key_filter1/n103_s3/F
6.638	0.016	tNET	FF	1	R7C14[2][B]	key_filter1/n98_s2/I2
7.664	1.026	tINS	FR	7	R7C14[2][B]	key_filter1/n98_s2/F
8.095	0.431	tNET	RR	1	R7C15[1][A]	key_filter1/n93_s1/I0
9.127	1.032	tINS	RF	1	R7C15[1][A]	key_filter1/n93_s1/F
9.127	0.000	tNET	FF	1	R7C15[1][A]	key_filter1/cnt_18_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
24.232	0.002	tNET	RR	1	R7C15[1][A]	key_filter1/cnt_18_s0/CLK
23.832	-0.400	tSu		1	R7C15[1][A]	key_filter1/cnt_18_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%
Arrival Data Path Delay	cell: 3.157, 64.492%; route: 1.280, 26.144%; tC2Q: 0.458, 9.363%
Required Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%

Path18

Path Summary:

Slack	14.835
Data Arrival Time	8.997
Data Required Time	23.832
From	key_filter1/cnt_4_s0
To	key_filter1/cnt_6_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
4.232	0.002	tNET	RR	1	R5C13[1][B]	key_filter1/cnt_4_s0/CLK
4.690	0.458	tC2Q	RF	4	R5C13[1][B]	key_filter1/cnt_4_s0/Q
6.322	1.632	tNET	FF	1	R7C13[3][B]	key_filter1/n148_s3/I0
7.354	1.032	tINS	FF	3	R7C13[3][B]	key_filter1/n148_s3/F
8.175	0.821	tNET	FF	1	R7C16[1][A]	key_filter1/n105_s1/I1
8.997	0.822	tINS	FF	1	R7C16[1][A]	key_filter1/n105_s1/F
8.997	0.000	tNET	FF	1	R7C16[1][A]	key_filter1/cnt_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
24.232	0.002	tNET	RR	1	R7C16[1][A]	key_filter1/cnt_6_s0/CLK
23.832	-0.400	tSu		1	R7C16[1][A]	key_filter1/cnt_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	3
Arrival Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%
Arrival Data Path Delay	cell: 1.854, 38.909%; route: 2.453, 51.473%; tC2Q: 0.458, 9.619%
Required Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%

Path19

Path Summary:

Slack	14.839
Data Arrival Time	8.992
Data Required Time	23.832
From	key_filter1/cnt_6_s0
To	key_filter1/cnt_10_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
4.232	0.002	tNET	RR	1	R7C16[1][A]	key_filter1/cnt_6_s0/CLK
4.690	0.458	tC2Q	RF	4	R7C16[1][A]	key_filter1/cnt_6_s0/Q
5.523	0.833	tNET	FF	1	R7C14[3][B]	key_filter1/n103_s3/I2
6.622	1.099	tINS	FF	4	R7C14[3][B]	key_filter1/n103_s3/F
7.127	0.506	tNET	FF	1	R7C16[3][A]	key_filter1/n101_s2/I3
8.159	1.032	tINS	FF	2	R7C16[3][A]	key_filter1/n101_s2/F
8.170	0.011	tNET	FF	1	R7C16[0][A]	key_filter1/n101_s1/I1
8.992	0.822	tINS	FF	1	R7C16[0][A]	key_filter1/n101_s1/F
8.992	0.000	tNET	FF	1	R7C16[0][A]	key_filter1/cnt_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
24.232	0.002	tNET	RR	1	R7C16[0][A]	key_filter1/cnt_10_s0/CLK
23.832	-0.400	tSu		1	R7C16[0][A]	key_filter1/cnt_10_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%
Arrival Data Path Delay	cell: 2.953, 62.031%; route: 1.349, 28.342%; tC2Q: 0.458, 9.628%
Required Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%

Path20

Path Summary:

Slack	14.839
Data Arrival Time	8.992
Data Required Time	23.832
From	key_filter1/cnt_6_s0
To	key_filter1/cnt_11_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
4.232	0.002	tNET	RR	1	R7C16[1][A]	key_filter1/cnt_6_s0/CLK
4.690	0.458	tC2Q	RF	4	R7C16[1][A]	key_filter1/cnt_6_s0/Q
5.523	0.833	tNET	FF	1	R7C14[3][B]	key_filter1/n103_s3/I2
6.622	1.099	tINS	FF	4	R7C14[3][B]	key_filter1/n103_s3/F
7.127	0.506	tNET	FF	1	R7C16[3][A]	key_filter1/n101_s2/I3
8.159	1.032	tINS	FF	2	R7C16[3][A]	key_filter1/n101_s2/F
8.170	0.011	tNET	FF	1	R7C16[0][B]	key_filter1/n100_s1/I1
8.992	0.822	tINS	FF	1	R7C16[0][B]	key_filter1/n100_s1/F
8.992	0.000	tNET	FF	1	R7C16[0][B]	key_filter1/cnt_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
24.232	0.002	tNET	RR	1	R7C16[0][B]	key_filter1/cnt_11_s0/CLK
23.832	-0.400	tSu		1	R7C16[0][B]	key_filter1/cnt_11_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%
Arrival Data Path Delay	cell: 2.953, 62.031%; route: 1.349, 28.342%; tC2Q: 0.458, 9.628%
Required Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%

Path21

Path Summary:

Slack	15.046
Data Arrival Time	8.785
Data Required Time	23.832
From	key_filter0/cnt_0_s0
To	key_filter0/cnt_9_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
4.232	0.002	tNET	RR	1	R5C7[2][B]	key_filter0/cnt_0_s0/CLK
4.690	0.458	tC2Q	RF	5	R5C7[2][B]	key_filter0/cnt_0_s0/Q
5.848	1.158	tNET	FF	1	R4C8[2][A]	key_filter0/n106_s2/I0
6.474	0.626	tINS	FF	7	R4C8[2][A]	key_filter0/n106_s2/F
7.321	0.847	tNET	FF	1	R5C9[3][A]	key_filter0/n100_s3/I0
7.947	0.626	tINS	FF	3	R5C9[3][A]	key_filter0/n100_s3/F
7.963	0.016	tNET	FF	1	R5C9[1][A]	key_filter0/n102_s1/I1
8.785	0.822	tINS	FF	1	R5C9[1][A]	key_filter0/n102_s1/F
8.785	0.000	tNET	FF	1	R5C9[1][A]	key_filter0/cnt_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
24.232	0.002	tNET	RR	1	R5C9[1][A]	key_filter0/cnt_9_s0/CLK
23.832	-0.400	tSu		1	R5C9[1][A]	key_filter0/cnt_9_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%
Arrival Data Path Delay	cell: 2.074, 45.546%; route: 2.021, 44.389%; tC2Q: 0.458, 10.065%
Required Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%

Path22

Path Summary:

Slack	15.046
Data Arrival Time	8.785
Data Required Time	23.832
From	key_filter0/cnt_0_s0
To	key_filter0/cnt_10_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
4.232	0.002	tNET	RR	1	R5C7[2][B]	key_filter0/cnt_0_s0/CLK
4.690	0.458	tC2Q	RF	5	R5C7[2][B]	key_filter0/cnt_0_s0/Q
5.848	1.158	tNET	FF	1	R4C8[2][A]	key_filter0/n106_s2/I0
6.474	0.626	tINS	FF	7	R4C8[2][A]	key_filter0/n106_s2/F
7.321	0.847	tNET	FF	1	R5C9[3][A]	key_filter0/n100_s3/I0
7.947	0.626	tINS	FF	3	R5C9[3][A]	key_filter0/n100_s3/F
7.963	0.016	tNET	FF	1	R5C9[1][B]	key_filter0/n101_s1/I1
8.785	0.822	tINS	FF	1	R5C9[1][B]	key_filter0/n101_s1/F
8.785	0.000	tNET	FF	1	R5C9[1][B]	key_filter0/cnt_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
24.232	0.002	tNET	RR	1	R5C9[1][B]	key_filter0/cnt_10_s0/CLK
23.832	-0.400	tSu		1	R5C9[1][B]	key_filter0/cnt_10_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%
Arrival Data Path Delay	cell: 2.074, 45.546%; route: 2.021, 44.389%; tC2Q: 0.458, 10.065%
Required Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%

Path23

Path Summary:

Slack	15.101
Data Arrival Time	8.731
Data Required Time	23.832
From	key_filter1/key_tmpa_s0
To	key_filter1/en_cnt_s2
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
4.232	0.002	tNET	RR	1	R4C16[0][A]	key_filter1/key_tmpa_s0/CLK
4.690	0.458	tC2Q	RF	9	R4C16[0][A]	key_filter1/key_tmpa_s0/Q
6.476	1.786	tNET	FF	1	R5C11[1][B]	key_filter1/n57_s9/I1
7.278	0.802	tINS	FR	2	R5C11[1][B]	key_filter1/n57_s9/F
7.699	0.421	tNET	RR	1	R5C12[2][A]	key_filter1/n58_s16/I3
8.731	1.032	tINS	RF	1	R5C12[2][A]	key_filter1/n58_s16/F
8.731	0.000	tNET	FF	1	R5C12[2][A]	key_filter1/en_cnt_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
24.232	0.002	tNET	RR	1	R5C12[2][A]	key_filter1/en_cnt_s2/CLK
23.832	-0.400	tSu		1	R5C12[2][A]	key_filter1/en_cnt_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	3
Arrival Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%
Arrival Data Path Delay	cell: 1.834, 40.765%; route: 2.207, 49.047%; tC2Q: 0.458, 10.188%
Required Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%

Path24

Path Summary:

Slack	15.119
Data Arrival Time	8.713
Data Required Time	23.832
From	key_filter1/cnt_6_s0
To	key_filter1/cnt_19_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
4.232	0.002	tNET	RR	1	R7C16[1][A]	key_filter1/cnt_6_s0/CLK
4.690	0.458	tC2Q	RF	4	R7C16[1][A]	key_filter1/cnt_6_s0/Q
5.523	0.833	tNET	FF	1	R7C14[3][B]	key_filter1/n103_s3/I2
6.622	1.099	tINS	FF	4	R7C14[3][B]	key_filter1/n103_s3/F
6.638	0.016	tNET	FF	1	R7C14[2][B]	key_filter1/n98_s2/I2
7.664	1.026	tINS	FR	7	R7C14[2][B]	key_filter1/n98_s2/F
8.087	0.423	tNET	RR	1	R7C15[1][B]	key_filter1/n92_s1/I0
8.713	0.626	tINS	RF	1	R7C15[1][B]	key_filter1/n92_s1/F
8.713	0.000	tNET	FF	1	R7C15[1][B]	key_filter1/cnt_19_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
24.232	0.002	tNET	RR	1	R7C15[1][B]	key_filter1/cnt_19_s0/CLK
23.832	-0.400	tSu		1	R7C15[1][B]	key_filter1/cnt_19_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%
Arrival Data Path Delay	cell: 2.751, 61.389%; route: 1.272, 28.383%; tC2Q: 0.458, 10.228%
Required Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%

Path25

Path Summary:

Slack	15.182
Data Arrival Time	8.649
Data Required Time	23.832
From	key_filter0/cnt_0_s0
To	key_filter0/cnt_6_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
4.232	0.002	tNET	RR	1	R5C7[2][B]	key_filter0/cnt_0_s0/CLK
4.690	0.458	tC2Q	RF	5	R5C7[2][B]	key_filter0/cnt_0_s0/Q
5.848	1.158	tNET	FF	1	R4C8[2][A]	key_filter0/n106_s2/I0
6.474	0.626	tINS	FF	7	R4C8[2][A]	key_filter0/n106_s2/F
6.975	0.501	tNET	FF	1	R5C8[2][B]	key_filter0/n148_s3/I2
7.601	0.626	tINS	FF	3	R5C8[2][B]	key_filter0/n148_s3/F
7.617	0.016	tNET	FF	1	R5C8[0][B]	key_filter0/n105_s1/I1
8.649	1.032	tINS	FF	1	R5C8[0][B]	key_filter0/n105_s1/F
8.649	0.000	tNET	FF	1	R5C8[0][B]	key_filter0/cnt_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOR5[A]	Clk_ibuf/O
24.232	0.002	tNET	RR	1	R5C8[0][B]	key_filter0/cnt_6_s0/CLK
23.832	-0.400	tSu		1	R5C8[0][B]	key_filter0/cnt_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%
Arrival Data Path Delay	cell: 2.284, 51.702%; route: 1.675, 37.923%; tC2Q: 0.458, 10.375%
Required Clock Path Delay	cell: 4.230, 99.954%; route: 0.002, 0.046%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.708
Data Arrival Time	3.836
Data Required Time	3.128
From	key_filter1/cnt_3_s0
To	key_filter1/cnt_3_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R7C13[1][A]	key_filter1/cnt_3_s0/CLK
3.461	0.333	tC2Q	RR	2	R7C13[1][A]	key_filter1/cnt_3_s0/Q
3.464	0.002	tNET	RR	1	R7C13[1][A]	key_filter1/n108_s1/I1
3.836	0.372	tINS	RF	1	R7C13[1][A]	key_filter1/n108_s1/F
3.836	0.000	tNET	FF	1	R7C13[1][A]	key_filter1/cnt_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R7C13[1][A]	key_filter1/cnt_3_s0/CLK
3.128	0.000	tHld		1	R7C13[1][A]	key_filter1/cnt_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%

Path2

Path Summary:

Slack	0.708
Data Arrival Time	3.836
Data Required Time	3.128
From	key_filter1/cnt_6_s0
To	key_filter1/cnt_6_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R7C16[1][A]	key_filter1/cnt_6_s0/CLK
3.461	0.333	tC2Q	RR	4	R7C16[1][A]	key_filter1/cnt_6_s0/Q
3.464	0.002	tNET	RR	1	R7C16[1][A]	key_filter1/n105_s1/I0
3.836	0.372	tINS	RF	1	R7C16[1][A]	key_filter1/n105_s1/F
3.836	0.000	tNET	FF	1	R7C16[1][A]	key_filter1/cnt_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R7C16[1][A]	key_filter1/cnt_6_s0/CLK
3.128	0.000	tHld		1	R7C16[1][A]	key_filter1/cnt_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%

Path3

Path Summary:

Slack	0.708
Data Arrival Time	3.836
Data Required Time	3.128
From	key_filter1/cnt_7_s0
To	key_filter1/cnt_7_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R7C13[0][A]	key_filter1/cnt_7_s0/CLK
3.461	0.333	tC2Q	RR	3	R7C13[0][A]	key_filter1/cnt_7_s0/Q
3.464	0.002	tNET	RR	1	R7C13[0][A]	key_filter1/n104_s1/I2
3.836	0.372	tINS	RF	1	R7C13[0][A]	key_filter1/n104_s1/F
3.836	0.000	tNET	FF	1	R7C13[0][A]	key_filter1/cnt_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R7C13[0][A]	key_filter1/cnt_7_s0/CLK
3.128	0.000	tHld		1	R7C13[0][A]	key_filter1/cnt_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%

Path4

Path Summary:

Slack	0.708
Data Arrival Time	3.836
Data Required Time	3.128
From	key_filter1/cnt_14_s0
To	key_filter1/cnt_14_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R5C14[1][A]	key_filter1/cnt_14_s0/CLK
3.461	0.333	tC2Q	RR	5	R5C14[1][A]	key_filter1/cnt_14_s0/Q
3.464	0.002	tNET	RR	1	R5C14[1][A]	key_filter1/n97_s1/I2
3.836	0.372	tINS	RF	1	R5C14[1][A]	key_filter1/n97_s1/F
3.836	0.000	tNET	FF	1	R5C14[1][A]	key_filter1/cnt_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R5C14[1][A]	key_filter1/cnt_14_s0/CLK
3.128	0.000	tHld		1	R5C14[1][A]	key_filter1/cnt_14_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%

Path5

Path Summary:

Slack	0.708
Data Arrival Time	3.836
Data Required Time	3.128
From	key_filter1/cnt_18_s0
To	key_filter1/cnt_18_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R7C15[1][A]	key_filter1/cnt_18_s0/CLK
3.461	0.333	tC2Q	RR	3	R7C15[1][A]	key_filter1/cnt_18_s0/Q
3.464	0.002	tNET	RR	1	R7C15[1][A]	key_filter1/n93_s1/I2
3.836	0.372	tINS	RF	1	R7C15[1][A]	key_filter1/n93_s1/F
3.836	0.000	tNET	FF	1	R7C15[1][A]	key_filter1/cnt_18_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R7C15[1][A]	key_filter1/cnt_18_s0/CLK
3.128	0.000	tHld		1	R7C15[1][A]	key_filter1/cnt_18_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%

Path6

Path Summary:

Slack	0.708
Data Arrival Time	3.836
Data Required Time	3.128
From	key_filter0/key_state_s5
To	key_filter0/key_state_s5
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R4C6[0][A]	key_filter0/key_state_s5/CLK
3.461	0.333	tC2Q	RR	3	R4C6[0][A]	key_filter0/key_state_s5/Q
3.464	0.002	tNET	RR	1	R4C6[0][A]	key_filter0/n52_s9/I3
3.836	0.372	tINS	RF	1	R4C6[0][A]	key_filter0/n52_s9/F
3.836	0.000	tNET	FF	1	R4C6[0][A]	key_filter0/key_state_s5/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R4C6[0][A]	key_filter0/key_state_s5/CLK
3.128	0.000	tHld		1	R4C6[0][A]	key_filter0/key_state_s5

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%

Path7

Path Summary:

Slack	0.708
Data Arrival Time	3.836
Data Required Time	3.128
From	key_filter0/cnt_2_s0
To	key_filter0/cnt_2_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R5C8[0][A]	key_filter0/cnt_2_s0/CLK
3.461	0.333	tC2Q	RR	3	R5C8[0][A]	key_filter0/cnt_2_s0/Q
3.464	0.002	tNET	RR	1	R5C8[0][A]	key_filter0/n109_s1/I2
3.836	0.372	tINS	RF	1	R5C8[0][A]	key_filter0/n109_s1/F
3.836	0.000	tNET	FF	1	R5C8[0][A]	key_filter0/cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R5C8[0][A]	key_filter0/cnt_2_s0/CLK
3.128	0.000	tHld		1	R5C8[0][A]	key_filter0/cnt_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%

Path8

Path Summary:

Slack	0.708
Data Arrival Time	3.836
Data Required Time	3.128
From	key_filter0/cnt_7_s0
To	key_filter0/cnt_7_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R5C8[1][A]	key_filter0/cnt_7_s0/CLK
3.461	0.333	tC2Q	RR	3	R5C8[1][A]	key_filter0/cnt_7_s0/Q
3.464	0.002	tNET	RR	1	R5C8[1][A]	key_filter0/n104_s1/I2
3.836	0.372	tINS	RF	1	R5C8[1][A]	key_filter0/n104_s1/F
3.836	0.000	tNET	FF	1	R5C8[1][A]	key_filter0/cnt_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R5C8[1][A]	key_filter0/cnt_7_s0/CLK
3.128	0.000	tHld		1	R5C8[1][A]	key_filter0/cnt_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%

Path9

Path Summary:

Slack	0.708
Data Arrival Time	3.836
Data Required Time	3.128
From	key_filter0/cnt_9_s0
To	key_filter0/cnt_9_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R5C9[1][A]	key_filter0/cnt_9_s0/CLK
3.461	0.333	tC2Q	RR	4	R5C9[1][A]	key_filter0/cnt_9_s0/Q
3.464	0.002	tNET	RR	1	R5C9[1][A]	key_filter0/n102_s1/I2
3.836	0.372	tINS	RF	1	R5C9[1][A]	key_filter0/n102_s1/F
3.836	0.000	tNET	FF	1	R5C9[1][A]	key_filter0/cnt_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R5C9[1][A]	key_filter0/cnt_9_s0/CLK
3.128	0.000	tHld		1	R5C9[1][A]	key_filter0/cnt_9_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%

Path10

Path Summary:

Slack	0.708
Data Arrival Time	3.836
Data Required Time	3.128
From	key_filter0/cnt_16_s0
To	key_filter0/cnt_16_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R4C10[1][A]	key_filter0/cnt_16_s0/CLK
3.461	0.333	tC2Q	RR	3	R4C10[1][A]	key_filter0/cnt_16_s0/Q
3.464	0.002	tNET	RR	1	R4C10[1][A]	key_filter0/n95_s1/I2
3.836	0.372	tINS	RF	1	R4C10[1][A]	key_filter0/n95_s1/F
3.836	0.000	tNET	FF	1	R4C10[1][A]	key_filter0/cnt_16_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R4C10[1][A]	key_filter0/cnt_16_s0/CLK
3.128	0.000	tHld		1	R4C10[1][A]	key_filter0/cnt_16_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%

Path11

Path Summary:

Slack	0.709
Data Arrival Time	3.837
Data Required Time	3.128
From	led_ctrl0/led_r_0_s1
To	led_ctrl0/led_r_0_s1
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R4C14[0][A]	led_ctrl0/led_r_0_s1/CLK
3.461	0.333	tC2Q	RR	3	R4C14[0][A]	led_ctrl0/led_r_0_s1/Q
3.465	0.004	tNET	RR	1	R4C14[0][A]	led_ctrl0/n18_s1/I0
3.837	0.372	tINS	RF	1	R4C14[0][A]	led_ctrl0/n18_s1/F
3.837	0.000	tNET	FF	1	R4C14[0][A]	led_ctrl0/led_r_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R4C14[0][A]	led_ctrl0/led_r_0_s1/CLK
3.128	0.000	tHld		1	R4C14[0][A]	led_ctrl0/led_r_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%

Path12

Path Summary:

Slack	0.709
Data Arrival Time	3.837
Data Required Time	3.128
From	key_filter1/state.IDEL_s0
To	key_filter1/state.IDEL_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R5C12[0][A]	key_filter1/state.IDEL_s0/CLK
3.461	0.333	tC2Q	RR	7	R5C12[0][A]	key_filter1/state.IDEL_s0/Q
3.465	0.004	tNET	RR	1	R5C12[0][A]	key_filter1/n52_s6/I1
3.837	0.372	tINS	RF	1	R5C12[0][A]	key_filter1/n52_s6/F
3.837	0.000	tNET	FF	1	R5C12[0][A]	key_filter1/state.IDEL_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R5C12[0][A]	key_filter1/state.IDEL_s0/CLK
3.128	0.000	tHld		1	R5C12[0][A]	key_filter1/state.IDEL_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%

Path13

Path Summary:

Slack	0.709
Data Arrival Time	3.837
Data Required Time	3.128
From	key_filter1/cnt_0_s0
To	key_filter1/cnt_0_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R7C12[0][A]	key_filter1/cnt_0_s0/CLK
3.461	0.333	tC2Q	RR	5	R7C12[0][A]	key_filter1/cnt_0_s0/Q
3.465	0.004	tNET	RR	1	R7C12[0][A]	key_filter1/n111_s2/I0
3.837	0.372	tINS	RF	1	R7C12[0][A]	key_filter1/n111_s2/F
3.837	0.000	tNET	FF	1	R7C12[0][A]	key_filter1/cnt_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R7C12[0][A]	key_filter1/cnt_0_s0/CLK
3.128	0.000	tHld		1	R7C12[0][A]	key_filter1/cnt_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%

Path14

Path Summary:

Slack	0.709
Data Arrival Time	3.837
Data Required Time	3.128
From	key_filter1/cnt_10_s0
To	key_filter1/cnt_10_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R7C16[0][A]	key_filter1/cnt_10_s0/CLK
3.461	0.333	tC2Q	RR	4	R7C16[0][A]	key_filter1/cnt_10_s0/Q
3.465	0.004	tNET	RR	1	R7C16[0][A]	key_filter1/n101_s1/I0
3.837	0.372	tINS	RF	1	R7C16[0][A]	key_filter1/n101_s1/F
3.837	0.000	tNET	FF	1	R7C16[0][A]	key_filter1/cnt_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R7C16[0][A]	key_filter1/cnt_10_s0/CLK
3.128	0.000	tHld		1	R7C16[0][A]	key_filter1/cnt_10_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%

Path15

Path Summary:

Slack	0.709
Data Arrival Time	3.837
Data Required Time	3.128
From	key_filter0/cnt_5_s0
To	key_filter0/cnt_5_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R5C9[0][A]	key_filter0/cnt_5_s0/CLK
3.461	0.333	tC2Q	RR	3	R5C9[0][A]	key_filter0/cnt_5_s0/Q
3.465	0.004	tNET	RR	1	R5C9[0][A]	key_filter0/n106_s1/I2
3.837	0.372	tINS	RF	1	R5C9[0][A]	key_filter0/n106_s1/F
3.837	0.000	tNET	FF	1	R5C9[0][A]	key_filter0/cnt_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R5C9[0][A]	key_filter0/cnt_5_s0/CLK
3.128	0.000	tHld		1	R5C9[0][A]	key_filter0/cnt_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%

Path16

Path Summary:

Slack	0.709
Data Arrival Time	3.837
Data Required Time	3.128
From	key_filter0/cnt_11_s0
To	key_filter0/cnt_11_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R5C10[0][A]	key_filter0/cnt_11_s0/CLK
3.461	0.333	tC2Q	RR	4	R5C10[0][A]	key_filter0/cnt_11_s0/Q
3.465	0.004	tNET	RR	1	R5C10[0][A]	key_filter0/n100_s1/I2
3.837	0.372	tINS	RF	1	R5C10[0][A]	key_filter0/n100_s1/F
3.837	0.000	tNET	FF	1	R5C10[0][A]	key_filter0/cnt_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R5C10[0][A]	key_filter0/cnt_11_s0/CLK
3.128	0.000	tHld		1	R5C10[0][A]	key_filter0/cnt_11_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%

Path17

Path Summary:

Slack	0.709
Data Arrival Time	3.837
Data Required Time	3.128
From	key_filter0/cnt_12_s0
To	key_filter0/cnt_12_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R4C10[0][A]	key_filter0/cnt_12_s0/CLK
3.461	0.333	tC2Q	RR	3	R4C10[0][A]	key_filter0/cnt_12_s0/Q
3.465	0.004	tNET	RR	1	R4C10[0][A]	key_filter0/n99_s1/I1
3.837	0.372	tINS	RF	1	R4C10[0][A]	key_filter0/n99_s1/F
3.837	0.000	tNET	FF	1	R4C10[0][A]	key_filter0/cnt_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R4C10[0][A]	key_filter0/cnt_12_s0/CLK
3.128	0.000	tHld		1	R4C10[0][A]	key_filter0/cnt_12_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%

Path18

Path Summary:

Slack	0.709
Data Arrival Time	3.837
Data Required Time	3.128
From	key_filter0/cnt_14_s0
To	key_filter0/cnt_14_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R5C10[1][A]	key_filter0/cnt_14_s0/CLK
3.461	0.333	tC2Q	RR	5	R5C10[1][A]	key_filter0/cnt_14_s0/Q
3.465	0.004	tNET	RR	1	R5C10[1][A]	key_filter0/n97_s1/I2
3.837	0.372	tINS	RF	1	R5C10[1][A]	key_filter0/n97_s1/F
3.837	0.000	tNET	FF	1	R5C10[1][A]	key_filter0/cnt_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R5C10[1][A]	key_filter0/cnt_14_s0/CLK
3.128	0.000	tHld		1	R5C10[1][A]	key_filter0/cnt_14_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%

Path19

Path Summary:

Slack	0.709
Data Arrival Time	3.837
Data Required Time	3.128
From	key_filter0/state.DOWN_s0
To	key_filter0/state.DOWN_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R4C7[0][A]	key_filter0/state.DOWN_s0/CLK
3.461	0.333	tC2Q	RR	6	R4C7[0][A]	key_filter0/state.DOWN_s0/Q
3.465	0.004	tNET	RR	1	R4C7[0][A]	key_filter0/n55_s5/I1
3.837	0.372	tINS	RF	1	R4C7[0][A]	key_filter0/n55_s5/F
3.837	0.000	tNET	FF	1	R4C7[0][A]	key_filter0/state.DOWN_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R4C7[0][A]	key_filter0/state.DOWN_s0/CLK
3.128	0.000	tHld		1	R4C7[0][A]	key_filter0/state.DOWN_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%

Path20

Path Summary:

Slack	0.710
Data Arrival Time	3.838
Data Required Time	3.128
From	key_filter0/cnt_8_s0
To	key_filter0/cnt_8_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R4C9[0][A]	key_filter0/cnt_8_s0/CLK
3.461	0.333	tC2Q	RR	5	R4C9[0][A]	key_filter0/cnt_8_s0/Q
3.466	0.005	tNET	RR	1	R4C9[0][A]	key_filter0/n103_s2/I0
3.838	0.372	tINS	RF	1	R4C9[0][A]	key_filter0/n103_s2/F
3.838	0.000	tNET	FF	1	R4C9[0][A]	key_filter0/cnt_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R4C9[0][A]	key_filter0/cnt_8_s0/CLK
3.128	0.000	tHld		1	R4C9[0][A]	key_filter0/cnt_8_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%
Arrival Data Path Delay	cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%

Path21

Path Summary:

Slack	0.892
Data Arrival Time	4.020
Data Required Time	3.128
From	key_filter1/cnt_13_s0
To	key_filter1/cnt_13_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R5C13[2][A]	key_filter1/cnt_13_s0/CLK
3.461	0.333	tC2Q	RR	6	R5C13[2][A]	key_filter1/cnt_13_s0/Q
3.464	0.002	tNET	RR	1	R5C13[2][A]	key_filter1/n98_s1/I0
4.020	0.556	tINS	RR	1	R5C13[2][A]	key_filter1/n98_s1/F
4.020	0.000	tNET	RR	1	R5C13[2][A]	key_filter1/cnt_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R5C13[2][A]	key_filter1/cnt_13_s0/CLK
3.128	0.000	tHld		1	R5C13[2][A]	key_filter1/cnt_13_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%
Arrival Data Path Delay	cell: 0.556, 62.353%; route: 0.002, 0.265%; tC2Q: 0.333, 37.382%
Required Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%

Path22

Path Summary:

Slack	0.892
Data Arrival Time	4.020
Data Required Time	3.128
From	key_filter1/cnt_15_s0
To	key_filter1/cnt_15_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R7C15[2][A]	key_filter1/cnt_15_s0/CLK
3.461	0.333	tC2Q	RR	4	R7C15[2][A]	key_filter1/cnt_15_s0/Q
3.464	0.002	tNET	RR	1	R7C15[2][A]	key_filter1/n96_s1/I2
4.020	0.556	tINS	RR	1	R7C15[2][A]	key_filter1/n96_s1/F
4.020	0.000	tNET	RR	1	R7C15[2][A]	key_filter1/cnt_15_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R7C15[2][A]	key_filter1/cnt_15_s0/CLK
3.128	0.000	tHld		1	R7C15[2][A]	key_filter1/cnt_15_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%
Arrival Data Path Delay	cell: 0.556, 62.353%; route: 0.002, 0.265%; tC2Q: 0.333, 37.382%
Required Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%

Path23

Path Summary:

Slack	0.892
Data Arrival Time	4.020
Data Required Time	3.128
From	key_filter1/cnt_16_s0
To	key_filter1/cnt_16_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R5C14[2][A]	key_filter1/cnt_16_s0/CLK
3.461	0.333	tC2Q	RR	3	R5C14[2][A]	key_filter1/cnt_16_s0/Q
3.464	0.002	tNET	RR	1	R5C14[2][A]	key_filter1/n95_s1/I2
4.020	0.556	tINS	RR	1	R5C14[2][A]	key_filter1/n95_s1/F
4.020	0.000	tNET	RR	1	R5C14[2][A]	key_filter1/cnt_16_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R5C14[2][A]	key_filter1/cnt_16_s0/CLK
3.128	0.000	tHld		1	R5C14[2][A]	key_filter1/cnt_16_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%
Arrival Data Path Delay	cell: 0.556, 62.353%; route: 0.002, 0.265%; tC2Q: 0.333, 37.382%
Required Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%

Path24

Path Summary:

Slack	0.892
Data Arrival Time	4.020
Data Required Time	3.128
From	key_filter0/cnt_19_s0
To	key_filter0/cnt_19_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R4C10[2][A]	key_filter0/cnt_19_s0/CLK
3.461	0.333	tC2Q	RR	2	R4C10[2][A]	key_filter0/cnt_19_s0/Q
3.464	0.002	tNET	RR	1	R4C10[2][A]	key_filter0/n92_s1/I2
4.020	0.556	tINS	RR	1	R4C10[2][A]	key_filter0/n92_s1/F
4.020	0.000	tNET	RR	1	R4C10[2][A]	key_filter0/cnt_19_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R4C10[2][A]	key_filter0/cnt_19_s0/CLK
3.128	0.000	tHld		1	R4C10[2][A]	key_filter0/cnt_19_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%
Arrival Data Path Delay	cell: 0.556, 62.353%; route: 0.002, 0.265%; tC2Q: 0.333, 37.382%
Required Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%

Path25

Path Summary:

Slack	0.893
Data Arrival Time	4.021
Data Required Time	3.128
From	key_filter0/cnt_1_s0
To	key_filter0/cnt_1_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R5C8[2][A]	key_filter0/cnt_1_s0/CLK
3.461	0.333	tC2Q	RR	4	R5C8[2][A]	key_filter0/cnt_1_s0/Q
3.465	0.004	tNET	RR	1	R5C8[2][A]	key_filter0/n110_s1/I1
4.021	0.556	tINS	RR	1	R5C8[2][A]	key_filter0/n110_s1/F
4.021	0.000	tNET	RR	1	R5C8[2][A]	key_filter0/cnt_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOR5[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOR5[A]	Clk_ibuf/O
3.128	0.002	tNET	RR	1	R5C8[2][A]	key_filter0/cnt_1_s0/CLK
3.128	0.000	tHld		1	R5C8[2][A]	key_filter0/cnt_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%
Arrival Data Path Delay	cell: 0.556, 62.271%; route: 0.004, 0.397%; tC2Q: 0.333, 37.333%
Required Clock Path Delay	cell: 3.126, 99.949%; route: 0.002, 0.051%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	6.663
Actual Width:	7.913
Required Width:	1.250
Type:	High Pulse Width
Clock:	Clk
Objects:	key_filter0/key_in_sb_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
4.232	0.002	tNET	RR	key_filter0/key_in_sb_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
12.144	0.004	tNET	FF	key_filter0/key_in_sb_s0/CLK

MPW2

MPW Summary:

Slack:	6.663
Actual Width:	7.913
Required Width:	1.250
Type:	High Pulse Width
Clock:	Clk
Objects:	key_filter0/key_tmpa_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
4.232	0.002	tNET	RR	key_filter0/key_tmpa_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
12.144	0.004	tNET	FF	key_filter0/key_tmpa_s0/CLK

MPW3

MPW Summary:

Slack:	6.663
Actual Width:	7.913
Required Width:	1.250
Type:	High Pulse Width
Clock:	Clk
Objects:	key_filter0/state.DOWN_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
4.232	0.002	tNET	RR	key_filter0/state.DOWN_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
12.144	0.004	tNET	FF	key_filter0/state.DOWN_s0/CLK

MPW4

MPW Summary:

Slack:	6.663
Actual Width:	7.913
Required Width:	1.250
Type:	High Pulse Width
Clock:	Clk
Objects:	key_filter0/cnt_16_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
4.232	0.002	tNET	RR	key_filter0/cnt_16_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
12.144	0.004	tNET	FF	key_filter0/cnt_16_s0/CLK

MPW5

MPW Summary:

Slack:	6.663
Actual Width:	7.913
Required Width:	1.250
Type:	High Pulse Width
Clock:	Clk
Objects:	key_filter0/cnt_8_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
4.232	0.002	tNET	RR	key_filter0/cnt_8_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
12.144	0.004	tNET	FF	key_filter0/cnt_8_s0/CLK

MPW6

MPW Summary:

Slack:	6.663
Actual Width:	7.913
Required Width:	1.250
Type:	High Pulse Width
Clock:	Clk
Objects:	key_filter0/key_state_s5

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
4.232	0.002	tNET	RR	key_filter0/key_state_s5/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
12.144	0.004	tNET	FF	key_filter0/key_state_s5/CLK

MPW7

MPW Summary:

Slack:	6.663
Actual Width:	7.913
Required Width:	1.250
Type:	High Pulse Width
Clock:	Clk
Objects:	key_filter1/key_state_s5

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
4.232	0.002	tNET	RR	key_filter1/key_state_s5/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
12.144	0.004	tNET	FF	key_filter1/key_state_s5/CLK

MPW8

MPW Summary:

Slack:	6.663
Actual Width:	7.913
Required Width:	1.250
Type:	High Pulse Width
Clock:	Clk
Objects:	key_filter1/key_flag_s5

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
4.232	0.002	tNET	RR	key_filter1/key_flag_s5/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
12.144	0.004	tNET	FF	key_filter1/key_flag_s5/CLK

MPW9

MPW Summary:

Slack:	6.663
Actual Width:	7.913
Required Width:	1.250
Type:	High Pulse Width
Clock:	Clk
Objects:	key_filter0/key_flag_s5

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
4.232	0.002	tNET	RR	key_filter0/key_flag_s5/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
12.144	0.004	tNET	FF	key_filter0/key_flag_s5/CLK

MPW10

MPW Summary:

Slack:	6.663
Actual Width:	7.913
Required Width:	1.250
Type:	High Pulse Width
Clock:	Clk
Objects:	key_filter1/state.FILTER1_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
4.232	0.002	tNET	RR	key_filter1/state.FILTER1_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
12.144	0.004	tNET	FF	key_filter1/state.FILTER1_s1/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
66	Clk_d	13.737	0.005
20	key_filter0/en_cnt	16.709	1.674
20	key_filter1/en_cnt	16.137	2.182
9	key_filter0/key_tmpa	16.062	1.813
9	key_filter1/key_tmpa	15.101	2.752
8	key_filter1/key_tmpb	16.324	0.875
8	key_filter1/cnt_full	15.626	1.648
8	key_filter0/key_tmpb	16.666	0.511
8	key_filter0/cnt_full	16.088	1.168
7	key_filter0/n92_7	13.762	0.523

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R5C9	27.78%
R7C14	27.78%
R4C9	22.22%
R5C10	22.22%
R4C7	22.22%
R4C8	20.83%
R7C13	20.83%
R5C12	19.44%
R5C13	19.44%
R5C8	19.44%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command