PnR Messages

Report Title PnR Report
Design File C:\Users\ADMIN\OneDrive\Documents\Button_filtering_counterl_Led\impl\gwsynthesis\key_led.vg
Physical Constraints File C:\Users\ADMIN\OneDrive\Documents\Button_filtering_counterl_Led\src\key_led.cst
Timing Constraints File ---
Tool Version V1.9.12.02 (64-bit)
Part Number GW1AN-LV1SFN32C6/I5
Device GW1AN-1S
Device Version A
Created Time Mon Jul 27 04:28:46 2026
Legal Announcement Copyright (C)2014-2026 Gowin Semiconductor Corporation. All rights reserved.

PnR Details

Place & Route Process Running placement: Placement Phase 0: CPU time = 0h 0m 0.006s, Elapsed time = 0h 0m 0.006s Placement Phase 1: CPU time = 0h 0m 0.009s, Elapsed time = 0h 0m 0.008s Placement Phase 2: CPU time = 0h 0m 0.003s, Elapsed time = 0h 0m 0.003s Placement Phase 3: CPU time = 0h 0m 0.429s, Elapsed time = 0h 0m 0.428s Total Placement: CPU time = 0h 0m 0.447s, Elapsed time = 0h 0m 0.445s Running routing: Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Routing Phase 1: CPU time = 0h 0m 0.008s, Elapsed time = 0h 0m 0.008s Routing Phase 2: CPU time = 0h 0m 0.03s, Elapsed time = 0h 0m 0.029s Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Total Routing: CPU time = 0h 0m 0.038s, Elapsed time = 0h 0m 0.037s Generate output files: CPU time = 0h 0m 0.098s, Elapsed time = 0h 0m 0.098s
Total Time and Memory Usage CPU time = 0h 0m 0.583s, Elapsed time = 0h 0m 0.58s, Peak memory usage = 234MB

Resource

Resource Usage Summary:

Resource Usage Utilization
Logic 109/1152 10%
    --LUT,ALU,ROM16 109(109 LUT, 0 ALU, 0 ROM16) -
    --SSRAM(RAM16) 0 -
Register 66/942 7%
    --Logic Register as Latch 0/864 0%
    --Logic Register as FF 64/864 8%
    --I/O Register as Latch 0/78 0%
    --I/O Register as FF 2/78 3%
CLS 64/576 12%
I/O Port 6/26 24%
I/O Buf 6 -
    --Input Buf 4 -
    --Output Buf 2 -
    --Inout Buf 0 -

I/O Bank Usage Summary:

I/O Bank UsageUtilization
bank 0 0/60%
bank 1 0/80%
bank 2 6/1250%

Clock Resource Usage Summary:

Clock Resource Usage Utilization
PRIMARY 1/8 13%
LW 1/8 13%
GCLK_PIN 2/2 100%

Global Clock Signals:

Signal Global Clock Location
Clk_d PRIMARY LEFT RIGHT
Rst_n_d LW -

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site CFG IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor BankVccio
Clk - 17/2 Y in IOR5[A] GCLKT_2 LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
Rst_n - 19/2 N in IOR7[A] GCLKT_3/DIN/CLKHOLD_N LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
key_in0 - 22/2 Y in IOR2[B] - LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
key_in1 - 21/2 Y in IOR4[A] SI/D2 LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
led[0] - 20/2 Y out IOR4[B] SO/D1 LVCMOS18 8 NONE NA NA OFF NA OFF NA 1.8
led[1] - 23/2 Y out IOR2[A] - LVCMOS18 8 NONE NA NA OFF NA OFF NA 1.8

All Package Pins:

Loc./Bank Signal Dir. Site CFG IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor Bank Vccio
7/0 - in IOT2[A] TMS LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
6/0 - in IOT2[B] TCK LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
3/0 - in IOT3[A] TDI LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
1/0 - out IOT3[B] TDO LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
30/0 - in IOT4[A] PLL_T_in LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
26/0 - in IOT4[B] JTAGSEL_N LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
32/1 - in IOT5[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
31/1 - in IOT5[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
2/1 - in IOT6[A] RECONFIG_N LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
28/1 - in IOT6[B] DONE LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
11/1 - in IOT7[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
12/1 - in IOT7[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
27/1 - in IOT8[A] READY LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
29/1 - in IOT8[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
23/2 led[1] out IOR2[A] - LVCMOS18 8 NONE NA NA OFF NA OFF NA 1.8
22/2 key_in0 in IOR2[B] - LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
25/2 - in IOR3[A] SCLK LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
24/2 - in IOR3[B] SSPI_CS_N/D0 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
21/2 key_in1 in IOR4[A] SI/D2 LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
20/2 led[0] out IOR4[B] SO/D1 LVCMOS18 8 NONE NA NA OFF NA OFF NA 1.8
17/2 Clk in IOR5[A] GCLKT_2 LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
16/2 - in IOR5[B] GCLKC_2 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
19/2 Rst_n in IOR7[A] GCLKT_3/DIN/CLKHOLD_N LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
18/2 - in IOR7[B] GCLKC_3/DOUT/WE_N LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
p1-14/2 - in IOR8[B] MCLK/D4 LVCMOS18 - UP - - - - - - -
p1-9/2 - in IOR9[A] MCS_N/D5 LVCMOS18 - UP - - - - - - -
p1-13/2 - in IOR9[B] MO/D6 LVCMOS18 - UP - - - - - - -
p1-6/2 - in IOR10[A] MI/D7/MODE1 LVCMOS18 - UP - - - - - - -
15/2 - in IOR11[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
14/2 - in IOR11[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8