Synthesis Messages

Report Title	GowinSynthesis Report
Design File	C:\Users\ADMIN\OneDrive\Documents\Button_filtering_counterl_Led\src\key_filter.v C:\Users\ADMIN\OneDrive\Documents\Button_filtering_counterl_Led\src\key_led_top.v C:\Users\ADMIN\OneDrive\Documents\Button_filtering_counterl_Led\src\led_ctrl.v
GowinSynthesis Constraints File	---
Tool Version	V1.9.12.02 (64-bit)
Part Number	GW1AN-LV1SFN32C6/I5
Device	GW1AN-1S
Device Version	A
Created Time	Mon Jul 27 04:28:46 2026
Legal Announcement	Copyright (C)2014-2026 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module	key_led_top
Synthesis Process	Running parser:     CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 217.121MB Running netlist conversion:     CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization:     Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 217.121MB     Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 217.121MB     Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 217.121MB Running inference:     Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 217.121MB     Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 217.121MB     Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 217.121MB     Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 217.121MB Running technical mapping:     Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 217.121MB     Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 217.121MB     Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 217.121MB     Tech-Mapping Phase 3: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.229s, Peak memory usage = 224.754MB     Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.053s, Peak memory usage = 224.754MB Generate output files:     CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 224.754MB
Total Time and Memory Usage	CPU time = 0h 0m 0.249s, Elapsed time = 0h 0m 0.32s, Peak memory usage = 224.754MB

Resource

Resource Usage Summary

Resource	Usage
I/O Port	6
I/O Buf	6
IBUF	4
OBUF	2
Register	66
DFFP	4
DFFC	54
DFFCE	8
LUT	108
LUT2	10
LUT3	31
LUT4	67
INV	2
INV	2

Resource Utilization Summary

Resource	Usage	Utilization
Logic	110(110 LUT, 0 ALU) / 1152	10%
Register	66 / 942	8%
--Register as Latch	0 / 942	0%
--Register as FF	66 / 942	8%
BSRAM	0 / 4	0%

Timing

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Object
1	Clk	Base	20.000	50.000	0.000	10.000			Clk_ibuf/I

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	Clk	50.000(MHz)	125.073(MHz)	4	TOP

Detail Timing Paths Information

Path 1

Path Summary:

Slack	12.005
Data Arrival Time	8.321
Data Required Time	20.326
From	key_filter1/cnt_5_s0
To	key_filter1/cnt_9_s0
Launch Clk	Clk[R]
Latch Clk	Clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				Clk
0.000	0.000	tCL	RR	1	Clk_ibuf/I
0.000	0.000	tINS	RR	66	Clk_ibuf/O
0.726	0.726	tNET	RR	1	key_filter1/cnt_5_s0/CLK
1.184	0.458	tC2Q	RF	3	key_filter1/cnt_5_s0/Q
2.144	0.960	tNET	FF	1	key_filter1/n103_s3/I1
3.243	1.099	tINS	FF	4	key_filter1/n103_s3/F
4.203	0.960	tNET	FF	1	key_filter1/n103_s2/I1
5.302	1.099	tINS	FF	2	key_filter1/n103_s2/F
6.262	0.960	tNET	FF	1	key_filter1/n102_s1/I1
7.361	1.099	tINS	FF	1	key_filter1/n102_s1/F
8.321	0.960	tNET	FF	1	key_filter1/cnt_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	20.000				active clock edge time
20.000	0.000				Clk
20.000	0.000	tCL	RR	1	Clk_ibuf/I
20.000	0.000	tINS	RR	66	Clk_ibuf/O
20.726	0.726	tNET	RR	1	key_filter1/cnt_9_s0/CLK
20.326	-0.400	tSu		1	key_filter1/cnt_9_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	4
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay:	cell: 3.297, 43.408%; route: 3.840, 50.558%; tC2Q: 0.458, 6.034%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 2

Path Summary:

Slack	12.005
Data Arrival Time	8.321
Data Required Time	20.326
From	key_filter1/cnt_1_s0
To	key_filter1/cnt_13_s0
Launch Clk	Clk[R]
Latch Clk	Clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				Clk
0.000	0.000	tCL	RR	1	Clk_ibuf/I
0.000	0.000	tINS	RR	66	Clk_ibuf/O
0.726	0.726	tNET	RR	1	key_filter1/cnt_1_s0/CLK
1.184	0.458	tC2Q	RF	4	key_filter1/cnt_1_s0/Q
2.144	0.960	tNET	FF	1	key_filter1/n107_s2/I1
3.243	1.099	tINS	FF	7	key_filter1/n107_s2/F
4.203	0.960	tNET	FF	1	key_filter1/n98_s2/I1
5.302	1.099	tINS	FF	7	key_filter1/n98_s2/F
6.262	0.960	tNET	FF	1	key_filter1/n98_s1/I1
7.361	1.099	tINS	FF	1	key_filter1/n98_s1/F
8.321	0.960	tNET	FF	1	key_filter1/cnt_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	20.000				active clock edge time
20.000	0.000				Clk
20.000	0.000	tCL	RR	1	Clk_ibuf/I
20.000	0.000	tINS	RR	66	Clk_ibuf/O
20.726	0.726	tNET	RR	1	key_filter1/cnt_13_s0/CLK
20.326	-0.400	tSu		1	key_filter1/cnt_13_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	4
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay:	cell: 3.297, 43.408%; route: 3.840, 50.558%; tC2Q: 0.458, 6.034%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 3

Path Summary:

Slack	12.005
Data Arrival Time	8.321
Data Required Time	20.326
From	key_filter1/cnt_1_s0
To	key_filter1/cnt_14_s0
Launch Clk	Clk[R]
Latch Clk	Clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				Clk
0.000	0.000	tCL	RR	1	Clk_ibuf/I
0.000	0.000	tINS	RR	66	Clk_ibuf/O
0.726	0.726	tNET	RR	1	key_filter1/cnt_1_s0/CLK
1.184	0.458	tC2Q	RF	4	key_filter1/cnt_1_s0/Q
2.144	0.960	tNET	FF	1	key_filter1/n107_s2/I1
3.243	1.099	tINS	FF	7	key_filter1/n107_s2/F
4.203	0.960	tNET	FF	1	key_filter1/n98_s2/I1
5.302	1.099	tINS	FF	7	key_filter1/n98_s2/F
6.262	0.960	tNET	FF	1	key_filter1/n97_s1/I1
7.361	1.099	tINS	FF	1	key_filter1/n97_s1/F
8.321	0.960	tNET	FF	1	key_filter1/cnt_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	20.000				active clock edge time
20.000	0.000				Clk
20.000	0.000	tCL	RR	1	Clk_ibuf/I
20.000	0.000	tINS	RR	66	Clk_ibuf/O
20.726	0.726	tNET	RR	1	key_filter1/cnt_14_s0/CLK
20.326	-0.400	tSu		1	key_filter1/cnt_14_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	4
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay:	cell: 3.297, 43.408%; route: 3.840, 50.558%; tC2Q: 0.458, 6.034%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 4

Path Summary:

Slack	12.005
Data Arrival Time	8.321
Data Required Time	20.326
From	key_filter1/cnt_14_s0
To	key_filter1/cnt_18_s0
Launch Clk	Clk[R]
Latch Clk	Clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				Clk
0.000	0.000	tCL	RR	1	Clk_ibuf/I
0.000	0.000	tINS	RR	66	Clk_ibuf/O
0.726	0.726	tNET	RR	1	key_filter1/cnt_14_s0/CLK
1.184	0.458	tC2Q	RF	5	key_filter1/cnt_14_s0/Q
2.144	0.960	tNET	FF	1	key_filter1/n94_s2/I1
3.243	1.099	tINS	FF	3	key_filter1/n94_s2/F
4.203	0.960	tNET	FF	1	key_filter1/n93_s2/I1
5.302	1.099	tINS	FF	1	key_filter1/n93_s2/F
6.262	0.960	tNET	FF	1	key_filter1/n93_s1/I1
7.361	1.099	tINS	FF	1	key_filter1/n93_s1/F
8.321	0.960	tNET	FF	1	key_filter1/cnt_18_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	20.000				active clock edge time
20.000	0.000				Clk
20.000	0.000	tCL	RR	1	Clk_ibuf/I
20.000	0.000	tINS	RR	66	Clk_ibuf/O
20.726	0.726	tNET	RR	1	key_filter1/cnt_18_s0/CLK
20.326	-0.400	tSu		1	key_filter1/cnt_18_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	4
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay:	cell: 3.297, 43.408%; route: 3.840, 50.558%; tC2Q: 0.458, 6.034%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 5

Path Summary:

Slack	12.005
Data Arrival Time	8.321
Data Required Time	20.326
From	key_filter0/cnt_5_s0
To	key_filter0/cnt_9_s0
Launch Clk	Clk[R]
Latch Clk	Clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				active clock edge time
0.000	0.000				Clk
0.000	0.000	tCL	RR	1	Clk_ibuf/I
0.000	0.000	tINS	RR	66	Clk_ibuf/O
0.726	0.726	tNET	RR	1	key_filter0/cnt_5_s0/CLK
1.184	0.458	tC2Q	RF	3	key_filter0/cnt_5_s0/Q
2.144	0.960	tNET	FF	1	key_filter0/n92_s5/I1
3.243	1.099	tINS	FF	4	key_filter0/n92_s5/F
4.203	0.960	tNET	FF	1	key_filter0/n100_s3/I1
5.302	1.099	tINS	FF	3	key_filter0/n100_s3/F
6.262	0.960	tNET	FF	1	key_filter0/n102_s1/I1
7.361	1.099	tINS	FF	1	key_filter0/n102_s1/F
8.321	0.960	tNET	FF	1	key_filter0/cnt_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	20.000				active clock edge time
20.000	0.000				Clk
20.000	0.000	tCL	RR	1	Clk_ibuf/I
20.000	0.000	tINS	RR	66	Clk_ibuf/O
20.726	0.726	tNET	RR	1	key_filter0/cnt_9_s0/CLK
20.326	-0.400	tSu		1	key_filter0/cnt_9_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	4
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay:	cell: 3.297, 43.408%; route: 3.840, 50.558%; tC2Q: 0.458, 6.034%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%