Timing Messages

Report Title	Timing Analysis Report
Design File	/home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/led_flash/impl/gwsynthesis/led_flash.vg
Physical Constraints File	/home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/led_flash/src/led_flash.cst
Timing Constraint File	---
Tool Version	V1.9.11
Part Number	GW1NSR-LV4CQN48PC6/I5
Device	GW1NSR-4C
Created Time	Tue Apr 8 12:18:11 2025
Legal Announcement	Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 1.14V 85C C6/I5
Hold Delay Model	Fast 1.26V 0C C6/I5
Numbers of Paths Analyzed	54
Numbers of Endpoints Analyzed	54
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	clk	Base	20.000	50.000	0.000	10.000			clk_ibuf/I

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk	50.000(MHz)	102.082(MHz)	5	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk	Setup	0.000	0
clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	10.204	cnt_23_s0/Q	cnt_6_s0/D	clk:[R]	clk:[R]	20.000	0.000	9.396
2	10.204	cnt_23_s0/Q	cnt_1_s0/D	clk:[R]	clk:[R]	20.000	0.000	9.396
3	10.214	cnt_23_s0/Q	cnt_23_s0/D	clk:[R]	clk:[R]	20.000	0.000	9.386
4	10.214	cnt_23_s0/Q	cnt_22_s0/D	clk:[R]	clk:[R]	20.000	0.000	9.386
5	10.214	cnt_23_s0/Q	cnt_16_s0/D	clk:[R]	clk:[R]	20.000	0.000	9.386
6	10.224	cnt_23_s0/Q	cnt_19_s0/D	clk:[R]	clk:[R]	20.000	0.000	9.376
7	10.224	cnt_23_s0/Q	cnt_11_s0/D	clk:[R]	clk:[R]	20.000	0.000	9.376
8	10.224	cnt_23_s0/Q	cnt_5_s0/D	clk:[R]	clk:[R]	20.000	0.000	9.376
9	10.271	cnt_23_s0/Q	cnt_2_s0/D	clk:[R]	clk:[R]	20.000	0.000	9.329
10	10.271	cnt_23_s0/Q	cnt_7_s0/D	clk:[R]	clk:[R]	20.000	0.000	9.329
11	10.281	cnt_23_s0/Q	cnt_12_s0/D	clk:[R]	clk:[R]	20.000	0.000	9.319
12	10.281	cnt_23_s0/Q	cnt_13_s0/D	clk:[R]	clk:[R]	20.000	0.000	9.319
13	10.281	cnt_23_s0/Q	cnt_14_s0/D	clk:[R]	clk:[R]	20.000	0.000	9.319
14	10.291	cnt_23_s0/Q	cnt_4_s0/D	clk:[R]	clk:[R]	20.000	0.000	9.309
15	10.291	cnt_23_s0/Q	cnt_15_s0/D	clk:[R]	clk:[R]	20.000	0.000	9.309
16	10.291	cnt_23_s0/Q	cnt_20_s0/D	clk:[R]	clk:[R]	20.000	0.000	9.309
17	10.300	cnt_23_s0/Q	cnt_18_s0/D	clk:[R]	clk:[R]	20.000	0.000	9.300
18	10.491	cnt_23_s0/Q	cnt_17_s0/D	clk:[R]	clk:[R]	20.000	0.000	9.109
19	10.491	cnt_23_s0/Q	cnt_21_s0/D	clk:[R]	clk:[R]	20.000	0.000	9.109
20	10.491	cnt_23_s0/Q	cnt_24_s0/D	clk:[R]	clk:[R]	20.000	0.000	9.109
21	12.260	cnt_23_s0/Q	cnt_8_s0/D	clk:[R]	clk:[R]	20.000	0.000	7.340
22	12.260	cnt_23_s0/Q	cnt_9_s0/D	clk:[R]	clk:[R]	20.000	0.000	7.340
23	12.260	cnt_23_s0/Q	cnt_10_s0/D	clk:[R]	clk:[R]	20.000	0.000	7.340
24	13.179	cnt_23_s0/Q	cnt_3_s0/D	clk:[R]	clk:[R]	20.000	0.000	6.421
25	13.365	cnt_23_s0/Q	cnt_0_s0/D	clk:[R]	clk:[R]	20.000	0.000	6.235

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.708	led_s3/Q	led_s3/D	clk:[R]	clk:[R]	0.000	0.000	0.708
2	0.708	cnt_6_s0/Q	cnt_6_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.708
3	0.708	cnt_12_s0/Q	cnt_12_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.708
4	0.708	cnt_19_s0/Q	cnt_19_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.708
5	0.709	cnt_10_s0/Q	cnt_10_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.709
6	0.709	cnt_11_s0/Q	cnt_11_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.709
7	0.709	cnt_14_s0/Q	cnt_14_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.709
8	0.709	cnt_17_s0/Q	cnt_17_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.709
9	0.709	cnt_20_s0/Q	cnt_20_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.709
10	0.709	cnt_22_s0/Q	cnt_22_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.709
11	0.709	cnt_23_s0/Q	cnt_23_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.709
12	0.710	cnt_4_s0/Q	cnt_4_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.710
13	0.710	cnt_5_s0/Q	cnt_5_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.710
14	0.711	cnt_7_s0/Q	cnt_7_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.711
15	0.943	cnt_23_s0/Q	cnt_24_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.943
16	0.944	cnt_1_s0/Q	cnt_2_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.944
17	0.950	cnt_0_s0/Q	cnt_1_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.950
18	1.060	cnt_15_s0/Q	cnt_15_s0/D	clk:[R]	clk:[R]	0.000	0.000	1.060
19	1.061	cnt_21_s0/Q	cnt_21_s0/D	clk:[R]	clk:[R]	0.000	0.000	1.061
20	1.061	cnt_13_s0/Q	cnt_13_s0/D	clk:[R]	clk:[R]	0.000	0.000	1.061
21	1.061	cnt_0_s0/Q	cnt_0_s0/D	clk:[R]	clk:[R]	0.000	0.000	1.061
22	1.062	cnt_16_s0/Q	cnt_16_s0/D	clk:[R]	clk:[R]	0.000	0.000	1.062
23	1.062	cnt_9_s0/Q	cnt_9_s0/D	clk:[R]	clk:[R]	0.000	0.000	1.062
24	1.063	cnt_8_s0/Q	cnt_8_s0/D	clk:[R]	clk:[R]	0.000	0.000	1.063
25	1.063	cnt_18_s0/Q	cnt_18_s0/D	clk:[R]	clk:[R]	0.000	0.000	1.063

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	6.521	7.771	1.250	High Pulse Width	clk	cnt_24_s0
2	6.521	7.771	1.250	High Pulse Width	clk	cnt_23_s0
3	6.521	7.771	1.250	High Pulse Width	clk	cnt_21_s0
4	6.521	7.771	1.250	High Pulse Width	clk	cnt_17_s0
5	6.521	7.771	1.250	High Pulse Width	clk	cnt_9_s0
6	6.521	7.771	1.250	High Pulse Width	clk	cnt_10_s0
7	6.521	7.771	1.250	High Pulse Width	clk	cnt_18_s0
8	6.521	7.771	1.250	High Pulse Width	clk	cnt_11_s0
9	6.521	7.771	1.250	High Pulse Width	clk	cnt_12_s0
10	6.521	7.771	1.250	High Pulse Width	clk	led_s3

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	10.204
Data Arrival Time	14.987
Data Required Time	25.191
From	cnt_23_s0
To	cnt_6_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R14C7[1][A]	cnt_23_s0/CLK
6.049	0.458	tC2Q	RF	4	R14C7[1][A]	cnt_23_s0/Q
6.887	0.837	tNET	FF	1	R12C7[0][B]	n36_s9/I2
7.986	1.099	tINS	FF	1	R12C7[0][B]	n36_s9/F
8.807	0.821	tNET	FF	1	R11C7[3][B]	n36_s10/I2
9.906	1.099	tINS	FF	3	R11C7[3][B]	n36_s10/F
11.055	1.149	tNET	FF	1	R7C8[3][B]	n36_s3/I2
11.877	0.822	tINS	FF	23	R7C8[3][B]	n36_s3/F
13.888	2.011	tNET	FF	1	R8C8[1][A]	n54_s1/I2
14.987	1.099	tINS	FF	1	R8C8[1][A]	n54_s1/F
14.987	0.000	tNET	FF	1	R8C8[1][A]	cnt_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R8C8[1][A]	cnt_6_s0/CLK
25.191	-0.400	tSu		1	R8C8[1][A]	cnt_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 4.119, 43.838%; route: 4.819, 51.284%; tC2Q: 0.458, 4.878%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path2

Path Summary:

Slack	10.204
Data Arrival Time	14.987
Data Required Time	25.191
From	cnt_23_s0
To	cnt_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R14C7[1][A]	cnt_23_s0/CLK
6.049	0.458	tC2Q	RF	4	R14C7[1][A]	cnt_23_s0/Q
6.887	0.837	tNET	FF	1	R12C7[0][B]	n36_s9/I2
7.986	1.099	tINS	FF	1	R12C7[0][B]	n36_s9/F
8.807	0.821	tNET	FF	1	R11C7[3][B]	n36_s10/I2
9.906	1.099	tINS	FF	3	R11C7[3][B]	n36_s10/F
11.055	1.149	tNET	FF	1	R7C8[3][B]	n36_s3/I2
11.877	0.822	tINS	FF	23	R7C8[3][B]	n36_s3/F
13.888	2.011	tNET	FF	1	R8C8[2][B]	n59_s1/I2
14.987	1.099	tINS	FF	1	R8C8[2][B]	n59_s1/F
14.987	0.000	tNET	FF	1	R8C8[2][B]	cnt_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R8C8[2][B]	cnt_1_s0/CLK
25.191	-0.400	tSu		1	R8C8[2][B]	cnt_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 4.119, 43.838%; route: 4.819, 51.284%; tC2Q: 0.458, 4.878%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path3

Path Summary:

Slack	10.214
Data Arrival Time	14.977
Data Required Time	25.191
From	cnt_23_s0
To	cnt_23_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R14C7[1][A]	cnt_23_s0/CLK
6.049	0.458	tC2Q	RF	4	R14C7[1][A]	cnt_23_s0/Q
6.887	0.837	tNET	FF	1	R12C7[0][B]	n36_s9/I2
7.986	1.099	tINS	FF	1	R12C7[0][B]	n36_s9/F
8.807	0.821	tNET	FF	1	R11C7[3][B]	n36_s10/I2
9.906	1.099	tINS	FF	3	R11C7[3][B]	n36_s10/F
11.055	1.149	tNET	FF	1	R7C8[3][B]	n36_s3/I2
11.877	0.822	tINS	FF	23	R7C8[3][B]	n36_s3/F
13.878	2.001	tNET	FF	1	R14C7[1][A]	n37_s1/I2
14.977	1.099	tINS	FF	1	R14C7[1][A]	n37_s1/F
14.977	0.000	tNET	FF	1	R14C7[1][A]	cnt_23_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R14C7[1][A]	cnt_23_s0/CLK
25.191	-0.400	tSu		1	R14C7[1][A]	cnt_23_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 4.119, 43.884%; route: 4.809, 51.233%; tC2Q: 0.458, 4.883%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path4

Path Summary:

Slack	10.214
Data Arrival Time	14.977
Data Required Time	25.191
From	cnt_23_s0
To	cnt_22_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R14C7[1][A]	cnt_23_s0/CLK
6.049	0.458	tC2Q	RF	4	R14C7[1][A]	cnt_23_s0/Q
6.887	0.837	tNET	FF	1	R12C7[0][B]	n36_s9/I2
7.986	1.099	tINS	FF	1	R12C7[0][B]	n36_s9/F
8.807	0.821	tNET	FF	1	R11C7[3][B]	n36_s10/I2
9.906	1.099	tINS	FF	3	R11C7[3][B]	n36_s10/F
11.055	1.149	tNET	FF	1	R7C8[3][B]	n36_s3/I2
11.877	0.822	tINS	FF	23	R7C8[3][B]	n36_s3/F
13.878	2.001	tNET	FF	1	R12C7[1][A]	n38_s1/I3
14.977	1.099	tINS	FF	1	R12C7[1][A]	n38_s1/F
14.977	0.000	tNET	FF	1	R12C7[1][A]	cnt_22_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R12C7[1][A]	cnt_22_s0/CLK
25.191	-0.400	tSu		1	R12C7[1][A]	cnt_22_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 4.119, 43.884%; route: 4.809, 51.233%; tC2Q: 0.458, 4.883%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path5

Path Summary:

Slack	10.214
Data Arrival Time	14.977
Data Required Time	25.191
From	cnt_23_s0
To	cnt_16_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R14C7[1][A]	cnt_23_s0/CLK
6.049	0.458	tC2Q	RF	4	R14C7[1][A]	cnt_23_s0/Q
6.887	0.837	tNET	FF	1	R12C7[0][B]	n36_s9/I2
7.986	1.099	tINS	FF	1	R12C7[0][B]	n36_s9/F
8.807	0.821	tNET	FF	1	R11C7[3][B]	n36_s10/I2
9.906	1.099	tINS	FF	3	R11C7[3][B]	n36_s10/F
11.055	1.149	tNET	FF	1	R7C8[3][B]	n36_s3/I2
11.877	0.822	tINS	FF	23	R7C8[3][B]	n36_s3/F
13.878	2.001	tNET	FF	1	R13C7[2][B]	n44_s1/I3
14.977	1.099	tINS	FF	1	R13C7[2][B]	n44_s1/F
14.977	0.000	tNET	FF	1	R13C7[2][B]	cnt_16_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R13C7[2][B]	cnt_16_s0/CLK
25.191	-0.400	tSu		1	R13C7[2][B]	cnt_16_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 4.119, 43.884%; route: 4.809, 51.233%; tC2Q: 0.458, 4.883%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path6

Path Summary:

Slack	10.224
Data Arrival Time	14.968
Data Required Time	25.191
From	cnt_23_s0
To	cnt_19_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R14C7[1][A]	cnt_23_s0/CLK
6.049	0.458	tC2Q	RF	4	R14C7[1][A]	cnt_23_s0/Q
6.887	0.837	tNET	FF	1	R12C7[0][B]	n36_s9/I2
7.986	1.099	tINS	FF	1	R12C7[0][B]	n36_s9/F
8.807	0.821	tNET	FF	1	R11C7[3][B]	n36_s10/I2
9.906	1.099	tINS	FF	3	R11C7[3][B]	n36_s10/F
11.055	1.149	tNET	FF	1	R7C8[3][B]	n36_s3/I2
11.877	0.822	tINS	FF	23	R7C8[3][B]	n36_s3/F
13.869	1.992	tNET	FF	1	R11C7[1][A]	n41_s1/I3
14.968	1.099	tINS	FF	1	R11C7[1][A]	n41_s1/F
14.968	0.000	tNET	FF	1	R11C7[1][A]	cnt_19_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R11C7[1][A]	cnt_19_s0/CLK
25.191	-0.400	tSu		1	R11C7[1][A]	cnt_19_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 4.119, 43.930%; route: 4.799, 51.182%; tC2Q: 0.458, 4.888%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path7

Path Summary:

Slack	10.224
Data Arrival Time	14.968
Data Required Time	25.191
From	cnt_23_s0
To	cnt_11_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R14C7[1][A]	cnt_23_s0/CLK
6.049	0.458	tC2Q	RF	4	R14C7[1][A]	cnt_23_s0/Q
6.887	0.837	tNET	FF	1	R12C7[0][B]	n36_s9/I2
7.986	1.099	tINS	FF	1	R12C7[0][B]	n36_s9/F
8.807	0.821	tNET	FF	1	R11C7[3][B]	n36_s10/I2
9.906	1.099	tINS	FF	3	R11C7[3][B]	n36_s10/F
11.055	1.149	tNET	FF	1	R7C8[3][B]	n36_s3/I2
11.877	0.822	tINS	FF	23	R7C8[3][B]	n36_s3/F
13.869	1.992	tNET	FF	1	R12C8[1][A]	n49_s1/I2
14.968	1.099	tINS	FF	1	R12C8[1][A]	n49_s1/F
14.968	0.000	tNET	FF	1	R12C8[1][A]	cnt_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R12C8[1][A]	cnt_11_s0/CLK
25.191	-0.400	tSu		1	R12C8[1][A]	cnt_11_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 4.119, 43.930%; route: 4.799, 51.182%; tC2Q: 0.458, 4.888%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path8

Path Summary:

Slack	10.224
Data Arrival Time	14.968
Data Required Time	25.191
From	cnt_23_s0
To	cnt_5_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R14C7[1][A]	cnt_23_s0/CLK
6.049	0.458	tC2Q	RF	4	R14C7[1][A]	cnt_23_s0/Q
6.887	0.837	tNET	FF	1	R12C7[0][B]	n36_s9/I2
7.986	1.099	tINS	FF	1	R12C7[0][B]	n36_s9/F
8.807	0.821	tNET	FF	1	R11C7[3][B]	n36_s10/I2
9.906	1.099	tINS	FF	3	R11C7[3][B]	n36_s10/F
11.055	1.149	tNET	FF	1	R7C8[3][B]	n36_s3/I2
11.877	0.822	tINS	FF	23	R7C8[3][B]	n36_s3/F
13.869	1.992	tNET	FF	1	R9C8[1][A]	n55_s1/I3
14.968	1.099	tINS	FF	1	R9C8[1][A]	n55_s1/F
14.968	0.000	tNET	FF	1	R9C8[1][A]	cnt_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R9C8[1][A]	cnt_5_s0/CLK
25.191	-0.400	tSu		1	R9C8[1][A]	cnt_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 4.119, 43.930%; route: 4.799, 51.182%; tC2Q: 0.458, 4.888%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path9

Path Summary:

Slack	10.271
Data Arrival Time	14.920
Data Required Time	25.191
From	cnt_23_s0
To	cnt_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R14C7[1][A]	cnt_23_s0/CLK
6.049	0.458	tC2Q	RF	4	R14C7[1][A]	cnt_23_s0/Q
6.887	0.837	tNET	FF	1	R12C7[0][B]	n36_s9/I2
7.986	1.099	tINS	FF	1	R12C7[0][B]	n36_s9/F
8.807	0.821	tNET	FF	1	R11C7[3][B]	n36_s10/I2
9.906	1.099	tINS	FF	3	R11C7[3][B]	n36_s10/F
11.055	1.149	tNET	FF	1	R7C8[3][B]	n36_s3/I2
11.877	0.822	tINS	FF	23	R7C8[3][B]	n36_s3/F
13.888	2.011	tNET	FF	1	R8C8[0][B]	n58_s1/I3
14.920	1.032	tINS	FF	1	R8C8[0][B]	n58_s1/F
14.920	0.000	tNET	FF	1	R8C8[0][B]	cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R8C8[0][B]	cnt_2_s0/CLK
25.191	-0.400	tSu		1	R8C8[0][B]	cnt_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 4.052, 43.434%; route: 4.819, 51.653%; tC2Q: 0.458, 4.913%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path10

Path Summary:

Slack	10.271
Data Arrival Time	14.920
Data Required Time	25.191
From	cnt_23_s0
To	cnt_7_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R14C7[1][A]	cnt_23_s0/CLK
6.049	0.458	tC2Q	RF	4	R14C7[1][A]	cnt_23_s0/Q
6.887	0.837	tNET	FF	1	R12C7[0][B]	n36_s9/I2
7.986	1.099	tINS	FF	1	R12C7[0][B]	n36_s9/F
8.807	0.821	tNET	FF	1	R11C7[3][B]	n36_s10/I2
9.906	1.099	tINS	FF	3	R11C7[3][B]	n36_s10/F
11.055	1.149	tNET	FF	1	R7C8[3][B]	n36_s3/I2
11.877	0.822	tINS	FF	23	R7C8[3][B]	n36_s3/F
13.888	2.011	tNET	FF	1	R8C8[0][A]	n53_s1/I3
14.920	1.032	tINS	FF	1	R8C8[0][A]	n53_s1/F
14.920	0.000	tNET	FF	1	R8C8[0][A]	cnt_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R8C8[0][A]	cnt_7_s0/CLK
25.191	-0.400	tSu		1	R8C8[0][A]	cnt_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 4.052, 43.434%; route: 4.819, 51.653%; tC2Q: 0.458, 4.913%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path11

Path Summary:

Slack	10.281
Data Arrival Time	14.910
Data Required Time	25.191
From	cnt_23_s0
To	cnt_12_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R14C7[1][A]	cnt_23_s0/CLK
6.049	0.458	tC2Q	RF	4	R14C7[1][A]	cnt_23_s0/Q
6.887	0.837	tNET	FF	1	R12C7[0][B]	n36_s9/I2
7.986	1.099	tINS	FF	1	R12C7[0][B]	n36_s9/F
8.807	0.821	tNET	FF	1	R11C7[3][B]	n36_s10/I2
9.906	1.099	tINS	FF	3	R11C7[3][B]	n36_s10/F
11.055	1.149	tNET	FF	1	R7C8[3][B]	n36_s3/I2
11.877	0.822	tINS	FF	23	R7C8[3][B]	n36_s3/F
13.878	2.001	tNET	FF	1	R12C7[0][A]	n48_s1/I3
14.910	1.032	tINS	FF	1	R12C7[0][A]	n48_s1/F
14.910	0.000	tNET	FF	1	R12C7[0][A]	cnt_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R12C7[0][A]	cnt_12_s0/CLK
25.191	-0.400	tSu		1	R12C7[0][A]	cnt_12_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 4.052, 43.480%; route: 4.809, 51.602%; tC2Q: 0.458, 4.918%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path12

Path Summary:

Slack	10.281
Data Arrival Time	14.910
Data Required Time	25.191
From	cnt_23_s0
To	cnt_13_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R14C7[1][A]	cnt_23_s0/CLK
6.049	0.458	tC2Q	RF	4	R14C7[1][A]	cnt_23_s0/Q
6.887	0.837	tNET	FF	1	R12C7[0][B]	n36_s9/I2
7.986	1.099	tINS	FF	1	R12C7[0][B]	n36_s9/F
8.807	0.821	tNET	FF	1	R11C7[3][B]	n36_s10/I2
9.906	1.099	tINS	FF	3	R11C7[3][B]	n36_s10/F
11.055	1.149	tNET	FF	1	R7C8[3][B]	n36_s3/I2
11.877	0.822	tINS	FF	23	R7C8[3][B]	n36_s3/F
13.878	2.001	tNET	FF	1	R14C7[0][B]	n47_s1/I2
14.910	1.032	tINS	FF	1	R14C7[0][B]	n47_s1/F
14.910	0.000	tNET	FF	1	R14C7[0][B]	cnt_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R14C7[0][B]	cnt_13_s0/CLK
25.191	-0.400	tSu		1	R14C7[0][B]	cnt_13_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 4.052, 43.480%; route: 4.809, 51.602%; tC2Q: 0.458, 4.918%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path13

Path Summary:

Slack	10.281
Data Arrival Time	14.910
Data Required Time	25.191
From	cnt_23_s0
To	cnt_14_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R14C7[1][A]	cnt_23_s0/CLK
6.049	0.458	tC2Q	RF	4	R14C7[1][A]	cnt_23_s0/Q
6.887	0.837	tNET	FF	1	R12C7[0][B]	n36_s9/I2
7.986	1.099	tINS	FF	1	R12C7[0][B]	n36_s9/F
8.807	0.821	tNET	FF	1	R11C7[3][B]	n36_s10/I2
9.906	1.099	tINS	FF	3	R11C7[3][B]	n36_s10/F
11.055	1.149	tNET	FF	1	R7C8[3][B]	n36_s3/I2
11.877	0.822	tINS	FF	23	R7C8[3][B]	n36_s3/F
13.878	2.001	tNET	FF	1	R13C7[0][A]	n46_s1/I3
14.910	1.032	tINS	FF	1	R13C7[0][A]	n46_s1/F
14.910	0.000	tNET	FF	1	R13C7[0][A]	cnt_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R13C7[0][A]	cnt_14_s0/CLK
25.191	-0.400	tSu		1	R13C7[0][A]	cnt_14_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 4.052, 43.480%; route: 4.809, 51.602%; tC2Q: 0.458, 4.918%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path14

Path Summary:

Slack	10.291
Data Arrival Time	14.901
Data Required Time	25.191
From	cnt_23_s0
To	cnt_4_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R14C7[1][A]	cnt_23_s0/CLK
6.049	0.458	tC2Q	RF	4	R14C7[1][A]	cnt_23_s0/Q
6.887	0.837	tNET	FF	1	R12C7[0][B]	n36_s9/I2
7.986	1.099	tINS	FF	1	R12C7[0][B]	n36_s9/F
8.807	0.821	tNET	FF	1	R11C7[3][B]	n36_s10/I2
9.906	1.099	tINS	FF	3	R11C7[3][B]	n36_s10/F
11.055	1.149	tNET	FF	1	R7C8[3][B]	n36_s3/I2
11.877	0.822	tINS	FF	23	R7C8[3][B]	n36_s3/F
13.869	1.992	tNET	FF	1	R9C8[0][A]	n56_s1/I2
14.901	1.032	tINS	FF	1	R9C8[0][A]	n56_s1/F
14.901	0.000	tNET	FF	1	R9C8[0][A]	cnt_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R9C8[0][A]	cnt_4_s0/CLK
25.191	-0.400	tSu		1	R9C8[0][A]	cnt_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 4.052, 43.526%; route: 4.799, 51.551%; tC2Q: 0.458, 4.923%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path15

Path Summary:

Slack	10.291
Data Arrival Time	14.901
Data Required Time	25.191
From	cnt_23_s0
To	cnt_15_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R14C7[1][A]	cnt_23_s0/CLK
6.049	0.458	tC2Q	RF	4	R14C7[1][A]	cnt_23_s0/Q
6.887	0.837	tNET	FF	1	R12C7[0][B]	n36_s9/I2
7.986	1.099	tINS	FF	1	R12C7[0][B]	n36_s9/F
8.807	0.821	tNET	FF	1	R11C7[3][B]	n36_s10/I2
9.906	1.099	tINS	FF	3	R11C7[3][B]	n36_s10/F
11.055	1.149	tNET	FF	1	R7C8[3][B]	n36_s3/I2
11.877	0.822	tINS	FF	23	R7C8[3][B]	n36_s3/F
13.869	1.992	tNET	FF	1	R11C7[0][B]	n45_s1/I2
14.901	1.032	tINS	FF	1	R11C7[0][B]	n45_s1/F
14.901	0.000	tNET	FF	1	R11C7[0][B]	cnt_15_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R11C7[0][B]	cnt_15_s0/CLK
25.191	-0.400	tSu		1	R11C7[0][B]	cnt_15_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 4.052, 43.526%; route: 4.799, 51.551%; tC2Q: 0.458, 4.923%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path16

Path Summary:

Slack	10.291
Data Arrival Time	14.901
Data Required Time	25.191
From	cnt_23_s0
To	cnt_20_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R14C7[1][A]	cnt_23_s0/CLK
6.049	0.458	tC2Q	RF	4	R14C7[1][A]	cnt_23_s0/Q
6.887	0.837	tNET	FF	1	R12C7[0][B]	n36_s9/I2
7.986	1.099	tINS	FF	1	R12C7[0][B]	n36_s9/F
8.807	0.821	tNET	FF	1	R11C7[3][B]	n36_s10/I2
9.906	1.099	tINS	FF	3	R11C7[3][B]	n36_s10/F
11.055	1.149	tNET	FF	1	R7C8[3][B]	n36_s3/I2
11.877	0.822	tINS	FF	23	R7C8[3][B]	n36_s3/F
13.869	1.992	tNET	FF	1	R12C8[0][A]	n40_s1/I3
14.901	1.032	tINS	FF	1	R12C8[0][A]	n40_s1/F
14.901	0.000	tNET	FF	1	R12C8[0][A]	cnt_20_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R12C8[0][A]	cnt_20_s0/CLK
25.191	-0.400	tSu		1	R12C8[0][A]	cnt_20_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 4.052, 43.526%; route: 4.799, 51.551%; tC2Q: 0.458, 4.923%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path17

Path Summary:

Slack	10.300
Data Arrival Time	14.891
Data Required Time	25.191
From	cnt_23_s0
To	cnt_18_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R14C7[1][A]	cnt_23_s0/CLK
6.049	0.458	tC2Q	RF	4	R14C7[1][A]	cnt_23_s0/Q
6.887	0.837	tNET	FF	1	R12C7[0][B]	n36_s9/I2
7.986	1.099	tINS	FF	1	R12C7[0][B]	n36_s9/F
8.807	0.821	tNET	FF	1	R11C7[3][B]	n36_s10/I2
9.906	1.099	tINS	FF	3	R11C7[3][B]	n36_s10/F
11.055	1.149	tNET	FF	1	R7C8[3][B]	n36_s3/I2
11.877	0.822	tINS	FF	23	R7C8[3][B]	n36_s3/F
13.859	1.982	tNET	FF	1	R11C7[1][B]	n42_s1/I2
14.891	1.032	tINS	FF	1	R11C7[1][B]	n42_s1/F
14.891	0.000	tNET	FF	1	R11C7[1][B]	cnt_18_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R11C7[1][B]	cnt_18_s0/CLK
25.191	-0.400	tSu		1	R11C7[1][B]	cnt_18_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 4.052, 43.572%; route: 4.789, 51.500%; tC2Q: 0.458, 4.929%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path18

Path Summary:

Slack	10.491
Data Arrival Time	14.700
Data Required Time	25.191
From	cnt_23_s0
To	cnt_17_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R14C7[1][A]	cnt_23_s0/CLK
6.049	0.458	tC2Q	RF	4	R14C7[1][A]	cnt_23_s0/Q
6.887	0.837	tNET	FF	1	R12C7[0][B]	n36_s9/I2
7.986	1.099	tINS	FF	1	R12C7[0][B]	n36_s9/F
8.807	0.821	tNET	FF	1	R11C7[3][B]	n36_s10/I2
9.906	1.099	tINS	FF	3	R11C7[3][B]	n36_s10/F
11.055	1.149	tNET	FF	1	R7C8[3][B]	n36_s3/I2
11.877	0.822	tINS	FF	23	R7C8[3][B]	n36_s3/F
13.878	2.001	tNET	FF	1	R13C7[1][A]	n43_s1/I3
14.700	0.822	tINS	FF	1	R13C7[1][A]	n43_s1/F
14.700	0.000	tNET	FF	1	R13C7[1][A]	cnt_17_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R13C7[1][A]	cnt_17_s0/CLK
25.191	-0.400	tSu		1	R13C7[1][A]	cnt_17_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.842, 42.177%; route: 4.809, 52.791%; tC2Q: 0.458, 5.032%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path19

Path Summary:

Slack	10.491
Data Arrival Time	14.700
Data Required Time	25.191
From	cnt_23_s0
To	cnt_21_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R14C7[1][A]	cnt_23_s0/CLK
6.049	0.458	tC2Q	RF	4	R14C7[1][A]	cnt_23_s0/Q
6.887	0.837	tNET	FF	1	R12C7[0][B]	n36_s9/I2
7.986	1.099	tINS	FF	1	R12C7[0][B]	n36_s9/F
8.807	0.821	tNET	FF	1	R11C7[3][B]	n36_s10/I2
9.906	1.099	tINS	FF	3	R11C7[3][B]	n36_s10/F
11.055	1.149	tNET	FF	1	R7C8[3][B]	n36_s3/I2
11.877	0.822	tINS	FF	23	R7C8[3][B]	n36_s3/F
13.878	2.001	tNET	FF	1	R12C7[1][B]	n39_s1/I2
14.700	0.822	tINS	FF	1	R12C7[1][B]	n39_s1/F
14.700	0.000	tNET	FF	1	R12C7[1][B]	cnt_21_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R12C7[1][B]	cnt_21_s0/CLK
25.191	-0.400	tSu		1	R12C7[1][B]	cnt_21_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.842, 42.177%; route: 4.809, 52.791%; tC2Q: 0.458, 5.032%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path20

Path Summary:

Slack	10.491
Data Arrival Time	14.700
Data Required Time	25.191
From	cnt_23_s0
To	cnt_24_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R14C7[1][A]	cnt_23_s0/CLK
6.049	0.458	tC2Q	RF	4	R14C7[1][A]	cnt_23_s0/Q
6.887	0.837	tNET	FF	1	R12C7[0][B]	n36_s9/I2
7.986	1.099	tINS	FF	1	R12C7[0][B]	n36_s9/F
8.807	0.821	tNET	FF	1	R11C7[3][B]	n36_s10/I2
9.906	1.099	tINS	FF	3	R11C7[3][B]	n36_s10/F
11.055	1.149	tNET	FF	1	R7C8[3][B]	n36_s3/I2
11.877	0.822	tINS	FF	23	R7C8[3][B]	n36_s3/F
13.878	2.001	tNET	FF	1	R14C7[1][B]	n36_s1/I3
14.700	0.822	tINS	FF	1	R14C7[1][B]	n36_s1/F
14.700	0.000	tNET	FF	1	R14C7[1][B]	cnt_24_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R14C7[1][B]	cnt_24_s0/CLK
25.191	-0.400	tSu		1	R14C7[1][B]	cnt_24_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.842, 42.177%; route: 4.809, 52.791%; tC2Q: 0.458, 5.032%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path21

Path Summary:

Slack	12.260
Data Arrival Time	12.931
Data Required Time	25.191
From	cnt_23_s0
To	cnt_8_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R14C7[1][A]	cnt_23_s0/CLK
6.049	0.458	tC2Q	RF	4	R14C7[1][A]	cnt_23_s0/Q
6.887	0.837	tNET	FF	1	R12C7[0][B]	n36_s9/I2
7.986	1.099	tINS	FF	1	R12C7[0][B]	n36_s9/F
8.807	0.821	tNET	FF	1	R11C7[3][B]	n36_s10/I2
9.906	1.099	tINS	FF	3	R11C7[3][B]	n36_s10/F
11.055	1.149	tNET	FF	1	R7C8[3][B]	n36_s3/I2
11.877	0.822	tINS	FF	23	R7C8[3][B]	n36_s3/F
11.899	0.022	tNET	FF	1	R7C8[0][B]	n52_s2/I3
12.931	1.032	tINS	FF	1	R7C8[0][B]	n52_s2/F
12.931	0.000	tNET	FF	1	R7C8[0][B]	cnt_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R7C8[0][B]	cnt_8_s0/CLK
25.191	-0.400	tSu		1	R7C8[0][B]	cnt_8_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 4.052, 55.206%; route: 2.829, 38.550%; tC2Q: 0.458, 6.245%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path22

Path Summary:

Slack	12.260
Data Arrival Time	12.931
Data Required Time	25.191
From	cnt_23_s0
To	cnt_9_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R14C7[1][A]	cnt_23_s0/CLK
6.049	0.458	tC2Q	RF	4	R14C7[1][A]	cnt_23_s0/Q
6.887	0.837	tNET	FF	1	R12C7[0][B]	n36_s9/I2
7.986	1.099	tINS	FF	1	R12C7[0][B]	n36_s9/F
8.807	0.821	tNET	FF	1	R11C7[3][B]	n36_s10/I2
9.906	1.099	tINS	FF	3	R11C7[3][B]	n36_s10/F
11.055	1.149	tNET	FF	1	R7C8[3][B]	n36_s3/I2
11.877	0.822	tINS	FF	23	R7C8[3][B]	n36_s3/F
11.899	0.022	tNET	FF	1	R7C8[1][B]	n51_s1/I3
12.931	1.032	tINS	FF	1	R7C8[1][B]	n51_s1/F
12.931	0.000	tNET	FF	1	R7C8[1][B]	cnt_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R7C8[1][B]	cnt_9_s0/CLK
25.191	-0.400	tSu		1	R7C8[1][B]	cnt_9_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 4.052, 55.206%; route: 2.829, 38.550%; tC2Q: 0.458, 6.245%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path23

Path Summary:

Slack	12.260
Data Arrival Time	12.931
Data Required Time	25.191
From	cnt_23_s0
To	cnt_10_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R14C7[1][A]	cnt_23_s0/CLK
6.049	0.458	tC2Q	RF	4	R14C7[1][A]	cnt_23_s0/Q
6.887	0.837	tNET	FF	1	R12C7[0][B]	n36_s9/I2
7.986	1.099	tINS	FF	1	R12C7[0][B]	n36_s9/F
8.807	0.821	tNET	FF	1	R11C7[3][B]	n36_s10/I2
9.906	1.099	tINS	FF	3	R11C7[3][B]	n36_s10/F
11.055	1.149	tNET	FF	1	R7C8[3][B]	n36_s3/I2
11.877	0.822	tINS	FF	23	R7C8[3][B]	n36_s3/F
11.899	0.022	tNET	FF	1	R7C8[0][A]	n50_s1/I3
12.931	1.032	tINS	FF	1	R7C8[0][A]	n50_s1/F
12.931	0.000	tNET	FF	1	R7C8[0][A]	cnt_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R7C8[0][A]	cnt_10_s0/CLK
25.191	-0.400	tSu		1	R7C8[0][A]	cnt_10_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 4.052, 55.206%; route: 2.829, 38.550%; tC2Q: 0.458, 6.245%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path24

Path Summary:

Slack	13.179
Data Arrival Time	12.012
Data Required Time	25.191
From	cnt_23_s0
To	cnt_3_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R14C7[1][A]	cnt_23_s0/CLK
6.049	0.458	tC2Q	RF	4	R14C7[1][A]	cnt_23_s0/Q
6.887	0.837	tNET	FF	1	R12C7[0][B]	n36_s9/I2
7.986	1.099	tINS	FF	1	R12C7[0][B]	n36_s9/F
8.807	0.821	tNET	FF	1	R11C7[3][B]	n36_s10/I2
9.906	1.099	tINS	FF	3	R11C7[3][B]	n36_s10/F
11.386	1.480	tNET	FF	1	R7C8[1][A]	n57_s3/I3
12.012	0.626	tINS	FF	1	R7C8[1][A]	n57_s3/F
12.012	0.000	tNET	FF	1	R7C8[1][A]	cnt_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R7C8[1][A]	cnt_3_s0/CLK
25.191	-0.400	tSu		1	R7C8[1][A]	cnt_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 2.824, 43.983%; route: 3.138, 48.879%; tC2Q: 0.458, 7.138%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path25

Path Summary:

Slack	13.365
Data Arrival Time	11.826
Data Required Time	25.191
From	cnt_23_s0
To	cnt_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R14C7[1][A]	cnt_23_s0/CLK
6.049	0.458	tC2Q	RF	4	R14C7[1][A]	cnt_23_s0/Q
6.887	0.837	tNET	FF	1	R12C7[0][B]	n36_s9/I2
7.986	1.099	tINS	FF	1	R12C7[0][B]	n36_s9/F
8.807	0.821	tNET	FF	1	R11C7[3][B]	n36_s10/I2
9.906	1.099	tINS	FF	3	R11C7[3][B]	n36_s10/F
11.200	1.294	tNET	FF	1	R8C8[1][B]	n60_s3/I3
11.826	0.626	tINS	FF	1	R8C8[1][B]	n60_s3/F
11.826	0.000	tNET	FF	1	R8C8[1][B]	cnt_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	26	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R8C8[1][B]	cnt_0_s0/CLK
25.191	-0.400	tSu		1	R8C8[1][B]	cnt_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 2.824, 45.292%; route: 2.953, 47.357%; tC2Q: 0.458, 7.351%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	led_s3
To	led_s3
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R9C7[0][A]	led_s3/CLK
4.426	0.333	tC2Q	RR	2	R9C7[0][A]	led_s3/Q
4.428	0.002	tNET	RR	1	R9C7[0][A]	n111_s2/I0
4.800	0.372	tINS	RF	1	R9C7[0][A]	n111_s2/F
4.800	0.000	tNET	FF	1	R9C7[0][A]	led_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R9C7[0][A]	led_s3/CLK
4.093	0.000	tHld		1	R9C7[0][A]	led_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path2

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	cnt_6_s0
To	cnt_6_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C8[1][A]	cnt_6_s0/CLK
4.426	0.333	tC2Q	RR	5	R8C8[1][A]	cnt_6_s0/Q
4.428	0.002	tNET	RR	1	R8C8[1][A]	n54_s1/I1
4.800	0.372	tINS	RF	1	R8C8[1][A]	n54_s1/F
4.800	0.000	tNET	FF	1	R8C8[1][A]	cnt_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C8[1][A]	cnt_6_s0/CLK
4.093	0.000	tHld		1	R8C8[1][A]	cnt_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path3

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	cnt_12_s0
To	cnt_12_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R12C7[0][A]	cnt_12_s0/CLK
4.426	0.333	tC2Q	RR	2	R12C7[0][A]	cnt_12_s0/Q
4.428	0.002	tNET	RR	1	R12C7[0][A]	n48_s1/I2
4.800	0.372	tINS	RF	1	R12C7[0][A]	n48_s1/F
4.800	0.000	tNET	FF	1	R12C7[0][A]	cnt_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R12C7[0][A]	cnt_12_s0/CLK
4.093	0.000	tHld		1	R12C7[0][A]	cnt_12_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path4

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	cnt_19_s0
To	cnt_19_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R11C7[1][A]	cnt_19_s0/CLK
4.426	0.333	tC2Q	RR	3	R11C7[1][A]	cnt_19_s0/Q
4.428	0.002	tNET	RR	1	R11C7[1][A]	n41_s1/I2
4.800	0.372	tINS	RF	1	R11C7[1][A]	n41_s1/F
4.800	0.000	tNET	FF	1	R11C7[1][A]	cnt_19_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R11C7[1][A]	cnt_19_s0/CLK
4.093	0.000	tHld		1	R11C7[1][A]	cnt_19_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path5

Path Summary:

Slack	0.709
Data Arrival Time	4.802
Data Required Time	4.093
From	cnt_10_s0
To	cnt_10_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R7C8[0][A]	cnt_10_s0/CLK
4.426	0.333	tC2Q	RR	3	R7C8[0][A]	cnt_10_s0/Q
4.430	0.004	tNET	RR	1	R7C8[0][A]	n50_s1/I2
4.802	0.372	tINS	RF	1	R7C8[0][A]	n50_s1/F
4.802	0.000	tNET	FF	1	R7C8[0][A]	cnt_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R7C8[0][A]	cnt_10_s0/CLK
4.093	0.000	tHld		1	R7C8[0][A]	cnt_10_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path6

Path Summary:

Slack	0.709
Data Arrival Time	4.802
Data Required Time	4.093
From	cnt_11_s0
To	cnt_11_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R12C8[1][A]	cnt_11_s0/CLK
4.426	0.333	tC2Q	RR	3	R12C8[1][A]	cnt_11_s0/Q
4.430	0.004	tNET	RR	1	R12C8[1][A]	n49_s1/I1
4.802	0.372	tINS	RF	1	R12C8[1][A]	n49_s1/F
4.802	0.000	tNET	FF	1	R12C8[1][A]	cnt_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R12C8[1][A]	cnt_11_s0/CLK
4.093	0.000	tHld		1	R12C8[1][A]	cnt_11_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path7

Path Summary:

Slack	0.709
Data Arrival Time	4.802
Data Required Time	4.093
From	cnt_14_s0
To	cnt_14_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R13C7[0][A]	cnt_14_s0/CLK
4.426	0.333	tC2Q	RR	3	R13C7[0][A]	cnt_14_s0/Q
4.430	0.004	tNET	RR	1	R13C7[0][A]	n46_s1/I2
4.802	0.372	tINS	RF	1	R13C7[0][A]	n46_s1/F
4.802	0.000	tNET	FF	1	R13C7[0][A]	cnt_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R13C7[0][A]	cnt_14_s0/CLK
4.093	0.000	tHld		1	R13C7[0][A]	cnt_14_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path8

Path Summary:

Slack	0.709
Data Arrival Time	4.802
Data Required Time	4.093
From	cnt_17_s0
To	cnt_17_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R13C7[1][A]	cnt_17_s0/CLK
4.426	0.333	tC2Q	RR	4	R13C7[1][A]	cnt_17_s0/Q
4.430	0.004	tNET	RR	1	R13C7[1][A]	n43_s1/I2
4.802	0.372	tINS	RF	1	R13C7[1][A]	n43_s1/F
4.802	0.000	tNET	FF	1	R13C7[1][A]	cnt_17_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R13C7[1][A]	cnt_17_s0/CLK
4.093	0.000	tHld		1	R13C7[1][A]	cnt_17_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path9

Path Summary:

Slack	0.709
Data Arrival Time	4.802
Data Required Time	4.093
From	cnt_20_s0
To	cnt_20_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R12C8[0][A]	cnt_20_s0/CLK
4.426	0.333	tC2Q	RR	4	R12C8[0][A]	cnt_20_s0/Q
4.430	0.004	tNET	RR	1	R12C8[0][A]	n40_s1/I2
4.802	0.372	tINS	RF	1	R12C8[0][A]	n40_s1/F
4.802	0.000	tNET	FF	1	R12C8[0][A]	cnt_20_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R12C8[0][A]	cnt_20_s0/CLK
4.093	0.000	tHld		1	R12C8[0][A]	cnt_20_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path10

Path Summary:

Slack	0.709
Data Arrival Time	4.802
Data Required Time	4.093
From	cnt_22_s0
To	cnt_22_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R12C7[1][A]	cnt_22_s0/CLK
4.426	0.333	tC2Q	RR	4	R12C7[1][A]	cnt_22_s0/Q
4.430	0.004	tNET	RR	1	R12C7[1][A]	n38_s1/I2
4.802	0.372	tINS	RF	1	R12C7[1][A]	n38_s1/F
4.802	0.000	tNET	FF	1	R12C7[1][A]	cnt_22_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R12C7[1][A]	cnt_22_s0/CLK
4.093	0.000	tHld		1	R12C7[1][A]	cnt_22_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path11

Path Summary:

Slack	0.709
Data Arrival Time	4.802
Data Required Time	4.093
From	cnt_23_s0
To	cnt_23_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R14C7[1][A]	cnt_23_s0/CLK
4.426	0.333	tC2Q	RR	4	R14C7[1][A]	cnt_23_s0/Q
4.430	0.004	tNET	RR	1	R14C7[1][A]	n37_s1/I1
4.802	0.372	tINS	RF	1	R14C7[1][A]	n37_s1/F
4.802	0.000	tNET	FF	1	R14C7[1][A]	cnt_23_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R14C7[1][A]	cnt_23_s0/CLK
4.093	0.000	tHld		1	R14C7[1][A]	cnt_23_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path12

Path Summary:

Slack	0.710
Data Arrival Time	4.803
Data Required Time	4.093
From	cnt_4_s0
To	cnt_4_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R9C8[0][A]	cnt_4_s0/CLK
4.426	0.333	tC2Q	RR	5	R9C8[0][A]	cnt_4_s0/Q
4.431	0.005	tNET	RR	1	R9C8[0][A]	n56_s1/I1
4.803	0.372	tINS	RF	1	R9C8[0][A]	n56_s1/F
4.803	0.000	tNET	FF	1	R9C8[0][A]	cnt_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R9C8[0][A]	cnt_4_s0/CLK
4.093	0.000	tHld		1	R9C8[0][A]	cnt_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path13

Path Summary:

Slack	0.710
Data Arrival Time	4.803
Data Required Time	4.093
From	cnt_5_s0
To	cnt_5_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R9C8[1][A]	cnt_5_s0/CLK
4.426	0.333	tC2Q	RR	4	R9C8[1][A]	cnt_5_s0/Q
4.431	0.005	tNET	RR	1	R9C8[1][A]	n55_s1/I2
4.803	0.372	tINS	RF	1	R9C8[1][A]	n55_s1/F
4.803	0.000	tNET	FF	1	R9C8[1][A]	cnt_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R9C8[1][A]	cnt_5_s0/CLK
4.093	0.000	tHld		1	R9C8[1][A]	cnt_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path14

Path Summary:

Slack	0.711
Data Arrival Time	4.804
Data Required Time	4.093
From	cnt_7_s0
To	cnt_7_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C8[0][A]	cnt_7_s0/CLK
4.426	0.333	tC2Q	RR	5	R8C8[0][A]	cnt_7_s0/Q
4.432	0.006	tNET	RR	1	R8C8[0][A]	n53_s1/I2
4.804	0.372	tINS	RF	1	R8C8[0][A]	n53_s1/F
4.804	0.000	tNET	FF	1	R8C8[0][A]	cnt_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C8[0][A]	cnt_7_s0/CLK
4.093	0.000	tHld		1	R8C8[0][A]	cnt_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path15

Path Summary:

Slack	0.943
Data Arrival Time	5.036
Data Required Time	4.093
From	cnt_23_s0
To	cnt_24_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R14C7[1][A]	cnt_23_s0/CLK
4.426	0.333	tC2Q	RF	4	R14C7[1][A]	cnt_23_s0/Q
4.664	0.238	tNET	FF	1	R14C7[1][B]	n36_s1/I1
5.036	0.372	tINS	FF	1	R14C7[1][B]	n36_s1/F
5.036	0.000	tNET	FF	1	R14C7[1][B]	cnt_24_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R14C7[1][B]	cnt_24_s0/CLK
4.093	0.000	tHld		1	R14C7[1][B]	cnt_24_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 39.447%; route: 0.238, 25.207%; tC2Q: 0.333, 35.347%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path16

Path Summary:

Slack	0.944
Data Arrival Time	5.037
Data Required Time	4.093
From	cnt_1_s0
To	cnt_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C8[2][B]	cnt_1_s0/CLK
4.426	0.333	tC2Q	RR	4	R8C8[2][B]	cnt_1_s0/Q
4.665	0.239	tNET	RR	1	R8C8[0][B]	n58_s1/I1
5.037	0.372	tINS	RF	1	R8C8[0][B]	n58_s1/F
5.037	0.000	tNET	FF	1	R8C8[0][B]	cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C8[0][B]	cnt_2_s0/CLK
4.093	0.000	tHld		1	R8C8[0][B]	cnt_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 39.403%; route: 0.239, 25.289%; tC2Q: 0.333, 35.307%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path17

Path Summary:

Slack	0.950
Data Arrival Time	5.043
Data Required Time	4.093
From	cnt_0_s0
To	cnt_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C8[1][B]	cnt_0_s0/CLK
4.426	0.333	tC2Q	RR	5	R8C8[1][B]	cnt_0_s0/Q
4.671	0.245	tNET	RR	1	R8C8[2][B]	n59_s1/I0
5.043	0.372	tINS	RF	1	R8C8[2][B]	n59_s1/F
5.043	0.000	tNET	FF	1	R8C8[2][B]	cnt_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C8[2][B]	cnt_1_s0/CLK
4.093	0.000	tHld		1	R8C8[2][B]	cnt_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 39.146%; route: 0.245, 25.778%; tC2Q: 0.333, 35.077%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path18

Path Summary:

Slack	1.060
Data Arrival Time	5.152
Data Required Time	4.093
From	cnt_15_s0
To	cnt_15_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R11C7[0][B]	cnt_15_s0/CLK
4.426	0.333	tC2Q	RR	3	R11C7[0][B]	cnt_15_s0/Q
4.428	0.002	tNET	RR	1	R11C7[0][B]	n45_s1/I1
5.152	0.724	tINS	RR	1	R11C7[0][B]	n45_s1/F
5.152	0.000	tNET	RR	1	R11C7[0][B]	cnt_15_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R11C7[0][B]	cnt_15_s0/CLK
4.093	0.000	tHld		1	R11C7[0][B]	cnt_15_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.724, 68.322%; route: 0.002, 0.223%; tC2Q: 0.333, 31.456%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path19

Path Summary:

Slack	1.061
Data Arrival Time	5.154
Data Required Time	4.093
From	cnt_21_s0
To	cnt_21_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R12C7[1][B]	cnt_21_s0/CLK
4.426	0.333	tC2Q	RR	5	R12C7[1][B]	cnt_21_s0/Q
4.430	0.004	tNET	RR	1	R12C7[1][B]	n39_s1/I1
5.154	0.724	tINS	RR	1	R12C7[1][B]	n39_s1/F
5.154	0.000	tNET	RR	1	R12C7[1][B]	cnt_21_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R12C7[1][B]	cnt_21_s0/CLK
4.093	0.000	tHld		1	R12C7[1][B]	cnt_21_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.724, 68.246%; route: 0.004, 0.334%; tC2Q: 0.333, 31.421%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path20

Path Summary:

Slack	1.061
Data Arrival Time	5.154
Data Required Time	4.093
From	cnt_13_s0
To	cnt_13_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R14C7[0][B]	cnt_13_s0/CLK
4.426	0.333	tC2Q	RR	4	R14C7[0][B]	cnt_13_s0/Q
4.430	0.004	tNET	RR	1	R14C7[0][B]	n47_s1/I1
5.154	0.724	tINS	RR	1	R14C7[0][B]	n47_s1/F
5.154	0.000	tNET	RR	1	R14C7[0][B]	cnt_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R14C7[0][B]	cnt_13_s0/CLK
4.093	0.000	tHld		1	R14C7[0][B]	cnt_13_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.724, 68.246%; route: 0.004, 0.334%; tC2Q: 0.333, 31.421%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path21

Path Summary:

Slack	1.061
Data Arrival Time	5.154
Data Required Time	4.093
From	cnt_0_s0
To	cnt_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C8[1][B]	cnt_0_s0/CLK
4.426	0.333	tC2Q	RR	5	R8C8[1][B]	cnt_0_s0/Q
4.430	0.004	tNET	RR	1	R8C8[1][B]	n60_s3/I0
5.154	0.724	tINS	RR	1	R8C8[1][B]	n60_s3/F
5.154	0.000	tNET	RR	1	R8C8[1][B]	cnt_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C8[1][B]	cnt_0_s0/CLK
4.093	0.000	tHld		1	R8C8[1][B]	cnt_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.724, 68.246%; route: 0.004, 0.334%; tC2Q: 0.333, 31.421%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path22

Path Summary:

Slack	1.062
Data Arrival Time	5.154
Data Required Time	4.093
From	cnt_16_s0
To	cnt_16_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R13C7[2][B]	cnt_16_s0/CLK
4.426	0.333	tC2Q	RR	2	R13C7[2][B]	cnt_16_s0/Q
4.428	0.002	tNET	RR	1	R13C7[2][B]	n44_s1/I2
5.154	0.726	tINS	RR	1	R13C7[2][B]	n44_s1/F
5.154	0.000	tNET	RR	1	R13C7[2][B]	cnt_16_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R13C7[2][B]	cnt_16_s0/CLK
4.093	0.000	tHld		1	R13C7[2][B]	cnt_16_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.726, 68.381%; route: 0.002, 0.222%; tC2Q: 0.333, 31.396%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path23

Path Summary:

Slack	1.062
Data Arrival Time	5.155
Data Required Time	4.093
From	cnt_9_s0
To	cnt_9_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R7C8[1][B]	cnt_9_s0/CLK
4.426	0.333	tC2Q	RR	5	R7C8[1][B]	cnt_9_s0/Q
4.431	0.005	tNET	RR	1	R7C8[1][B]	n51_s1/I2
5.155	0.724	tINS	RR	1	R7C8[1][B]	n51_s1/F
5.155	0.000	tNET	RR	1	R7C8[1][B]	cnt_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R7C8[1][B]	cnt_9_s0/CLK
4.093	0.000	tHld		1	R7C8[1][B]	cnt_9_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.724, 68.170%; route: 0.005, 0.445%; tC2Q: 0.333, 31.386%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path24

Path Summary:

Slack	1.063
Data Arrival Time	5.156
Data Required Time	4.093
From	cnt_8_s0
To	cnt_8_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R7C8[0][B]	cnt_8_s0/CLK
4.426	0.333	tC2Q	RR	6	R7C8[0][B]	cnt_8_s0/Q
4.432	0.006	tNET	RR	1	R7C8[0][B]	n52_s2/I2
5.156	0.724	tINS	RR	1	R7C8[0][B]	n52_s2/F
5.156	0.000	tNET	RR	1	R7C8[0][B]	cnt_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R7C8[0][B]	cnt_8_s0/CLK
4.093	0.000	tHld		1	R7C8[0][B]	cnt_8_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.724, 68.094%; route: 0.006, 0.555%; tC2Q: 0.333, 31.351%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path25

Path Summary:

Slack	1.063
Data Arrival Time	5.156
Data Required Time	4.093
From	cnt_18_s0
To	cnt_18_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R11C7[1][B]	cnt_18_s0/CLK
4.426	0.333	tC2Q	RR	5	R11C7[1][B]	cnt_18_s0/Q
4.432	0.006	tNET	RR	1	R11C7[1][B]	n42_s1/I1
5.156	0.724	tINS	RR	1	R11C7[1][B]	n42_s1/F
5.156	0.000	tNET	RR	1	R11C7[1][B]	cnt_18_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	26	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R11C7[1][B]	cnt_18_s0/CLK
4.093	0.000	tHld		1	R11C7[1][B]	cnt_18_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.724, 68.094%; route: 0.006, 0.555%; tC2Q: 0.333, 31.351%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	clk
Objects:	cnt_24_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
5.591	1.361	tNET	RR	cnt_24_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
13.362	1.222	tNET	FF	cnt_24_s0/CLK

MPW2

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	clk
Objects:	cnt_23_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
5.591	1.361	tNET	RR	cnt_23_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
13.362	1.222	tNET	FF	cnt_23_s0/CLK

MPW3

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	clk
Objects:	cnt_21_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
5.591	1.361	tNET	RR	cnt_21_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
13.362	1.222	tNET	FF	cnt_21_s0/CLK

MPW4

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	clk
Objects:	cnt_17_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
5.591	1.361	tNET	RR	cnt_17_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
13.362	1.222	tNET	FF	cnt_17_s0/CLK

MPW5

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	clk
Objects:	cnt_9_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
5.591	1.361	tNET	RR	cnt_9_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
13.362	1.222	tNET	FF	cnt_9_s0/CLK

MPW6

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	clk
Objects:	cnt_10_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
5.591	1.361	tNET	RR	cnt_10_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
13.362	1.222	tNET	FF	cnt_10_s0/CLK

MPW7

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	clk
Objects:	cnt_18_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
5.591	1.361	tNET	RR	cnt_18_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
13.362	1.222	tNET	FF	cnt_18_s0/CLK

MPW8

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	clk
Objects:	cnt_11_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
5.591	1.361	tNET	RR	cnt_11_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
13.362	1.222	tNET	FF	cnt_11_s0/CLK

MPW9

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	clk
Objects:	cnt_12_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
5.591	1.361	tNET	RR	cnt_12_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
13.362	1.222	tNET	FF	cnt_12_s0/CLK

MPW10

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	clk
Objects:	led_s3

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
5.591	1.361	tNET	RR	led_s3/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
13.362	1.222	tNET	FF	led_s3/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
26	clk_d	10.204	1.727
23	n36_7	10.204	2.011
8	n40_6	11.786	1.476
7	n55_6	11.092	0.855
6	cnt[8]	12.926	0.840
5	cnt[0]	11.616	0.986
5	cnt[21]	10.746	0.811
5	cnt[18]	12.677	0.505
5	cnt[9]	12.651	0.832
5	cnt[7]	11.941	0.819

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R8C8	68.06%
R7C8	63.89%
R12C7	51.39%
R13C7	51.39%
R11C7	48.61%
R9C8	47.22%
R14C7	34.72%
R12C8	34.72%
R9C7	33.33%
R7C7	8.33%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command