Synthesis Messages

Report Title GowinSynthesis Report
Design File /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/led_flash/src/led_flash.v
/home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/led_flash/src/led_flash_tb.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11
Part Number GW1NSR-LV4CQN48PC6/I5
Device GW1NSR-4C
Created Time Tue Apr 8 12:18:06 2025
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module led_flash
Synthesis Process Running parser:
    CPU time = 0h 0m 0.055s, Elapsed time = 0h 0m 0.051s, Peak memory usage = 239.383MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0s, Peak memory usage = 239.383MB
    Optimizing Phase 1: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0s, Peak memory usage = 239.383MB
    Optimizing Phase 2: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0s, Peak memory usage = 239.383MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 239.383MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 239.383MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 239.383MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 239.383MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.003s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 239.383MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0s, Peak memory usage = 239.383MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 239.383MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.464s, Elapsed time = 0h 0m 0.456s, Peak memory usage = 257.855MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.068s, Elapsed time = 0h 0m 0.066s, Peak memory usage = 257.855MB
Generate output files:
    CPU time = 0h 0m 0.022s, Elapsed time = 0h 0m 0.03s, Peak memory usage = 257.855MB
Total Time and Memory Usage CPU time = 0h 0m 0.616s, Elapsed time = 0h 0m 0.605s, Peak memory usage = 257.855MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 3
I/O Buf 3
    IBUF 2
    OBUF 1
Register 26
    DFFC 25
    DFFCE 1
LUT 52
    LUT2 2
    LUT3 21
    LUT4 29
INV 2
    INV 2

Resource Utilization Summary

Resource Usage Utilization
Logic 54(54 LUT, 0 ALU) / 4608 2%
Register 26 / 3573 <1%
  --Register as Latch 0 / 3573 0%
  --Register as FF 26 / 3573 <1%
BSRAM 0 / 10 0%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk Base 20.000 50.000 0.000 10.000 clk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 50.000(MHz) 100.803(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 10.080
Data Arrival Time 10.246
Data Required Time 20.326
From cnt_14_s0
To cnt_24_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 26 clk_ibuf/O
0.726 0.726 tNET RR 1 cnt_14_s0/CLK
1.184 0.458 tC2Q RF 3 cnt_14_s0/Q
2.144 0.960 tNET FF 1 n43_s2/I1
3.243 1.099 tINS FF 4 n43_s2/F
4.203 0.960 tNET FF 1 n40_s3/I0
5.235 1.032 tINS FF 3 n40_s3/F
6.195 0.960 tNET FF 1 n36_s2/I1
7.294 1.099 tINS FF 2 n36_s2/F
8.254 0.960 tNET FF 1 n36_s1/I0
9.286 1.032 tINS FF 1 n36_s1/F
10.246 0.960 tNET FF 1 cnt_24_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 26 clk_ibuf/O
20.726 0.726 tNET RR 1 cnt_24_s0/CLK
20.326 -0.400 tSu 1 cnt_24_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 4.262, 44.767%; route: 4.800, 50.419%; tC2Q: 0.458, 4.814%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 2

Path Summary:
Slack 10.080
Data Arrival Time 10.246
Data Required Time 20.326
From cnt_14_s0
To cnt_23_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 26 clk_ibuf/O
0.726 0.726 tNET RR 1 cnt_14_s0/CLK
1.184 0.458 tC2Q RF 3 cnt_14_s0/Q
2.144 0.960 tNET FF 1 n43_s2/I1
3.243 1.099 tINS FF 4 n43_s2/F
4.203 0.960 tNET FF 1 n40_s3/I0
5.235 1.032 tINS FF 3 n40_s3/F
6.195 0.960 tNET FF 1 n36_s2/I1
7.294 1.099 tINS FF 2 n36_s2/F
8.254 0.960 tNET FF 1 n37_s1/I0
9.286 1.032 tINS FF 1 n37_s1/F
10.246 0.960 tNET FF 1 cnt_23_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 26 clk_ibuf/O
20.726 0.726 tNET RR 1 cnt_23_s0/CLK
20.326 -0.400 tSu 1 cnt_23_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 4.262, 44.767%; route: 4.800, 50.419%; tC2Q: 0.458, 4.814%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 3

Path Summary:
Slack 10.080
Data Arrival Time 10.246
Data Required Time 20.326
From cnt_14_s0
To cnt_22_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 26 clk_ibuf/O
0.726 0.726 tNET RR 1 cnt_14_s0/CLK
1.184 0.458 tC2Q RF 3 cnt_14_s0/Q
2.144 0.960 tNET FF 1 n43_s2/I1
3.243 1.099 tINS FF 4 n43_s2/F
4.203 0.960 tNET FF 1 n40_s3/I0
5.235 1.032 tINS FF 3 n40_s3/F
6.195 0.960 tNET FF 1 n38_s2/I1
7.294 1.099 tINS FF 2 n38_s2/F
8.254 0.960 tNET FF 1 n38_s1/I0
9.286 1.032 tINS FF 1 n38_s1/F
10.246 0.960 tNET FF 1 cnt_22_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 26 clk_ibuf/O
20.726 0.726 tNET RR 1 cnt_22_s0/CLK
20.326 -0.400 tSu 1 cnt_22_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 4.262, 44.767%; route: 4.800, 50.419%; tC2Q: 0.458, 4.814%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 4

Path Summary:
Slack 10.080
Data Arrival Time 10.246
Data Required Time 20.326
From cnt_14_s0
To cnt_21_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 26 clk_ibuf/O
0.726 0.726 tNET RR 1 cnt_14_s0/CLK
1.184 0.458 tC2Q RF 3 cnt_14_s0/Q
2.144 0.960 tNET FF 1 n43_s2/I1
3.243 1.099 tINS FF 4 n43_s2/F
4.203 0.960 tNET FF 1 n40_s3/I0
5.235 1.032 tINS FF 3 n40_s3/F
6.195 0.960 tNET FF 1 n38_s2/I1
7.294 1.099 tINS FF 2 n38_s2/F
8.254 0.960 tNET FF 1 n39_s1/I0
9.286 1.032 tINS FF 1 n39_s1/F
10.246 0.960 tNET FF 1 cnt_21_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 26 clk_ibuf/O
20.726 0.726 tNET RR 1 cnt_21_s0/CLK
20.326 -0.400 tSu 1 cnt_21_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 4.262, 44.767%; route: 4.800, 50.419%; tC2Q: 0.458, 4.814%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 5

Path Summary:
Slack 10.080
Data Arrival Time 10.246
Data Required Time 20.326
From cnt_5_s0
To cnt_11_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 26 clk_ibuf/O
0.726 0.726 tNET RR 1 cnt_5_s0/CLK
1.184 0.458 tC2Q RF 4 cnt_5_s0/Q
2.144 0.960 tNET FF 1 n40_s4/I1
3.243 1.099 tINS FF 3 n40_s4/F
4.203 0.960 tNET FF 1 n50_s2/I1
5.302 1.099 tINS FF 3 n50_s2/F
6.262 0.960 tNET FF 1 n48_s3/I0
7.294 1.032 tINS FF 2 n48_s3/F
8.254 0.960 tNET FF 1 n49_s1/I0
9.286 1.032 tINS FF 1 n49_s1/F
10.246 0.960 tNET FF 1 cnt_11_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 26 clk_ibuf/O
20.726 0.726 tNET RR 1 cnt_11_s0/CLK
20.326 -0.400 tSu 1 cnt_11_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 4.262, 44.767%; route: 4.800, 50.419%; tC2Q: 0.458, 4.814%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%