Timing Messages

Report Title Timing Analysis Report
Design File /home/quang1806/Desktop/hex84k/led7segmentled7segment/impl/gwsynthesis/led7segmentled7segment.vg
Physical Constraints File /home/quang1806/Desktop/hex84k/led7segmentled7segment/src/led7segmentled7segment.cst
Timing Constraint File ---
Tool Version V1.9.11
Part Number GW1NSR-LV4CQN48PC6/I5
Device GW1NSR-4C
Created Time Fri Aug 22 11:55:47 2025
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 1.14V 85C C6/I5
Hold Delay Model Fast 1.26V 0C C6/I5
Numbers of Paths Analyzed 138
Numbers of Endpoints Analyzed 139
Numbers of Falling Endpoints 0
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
1 clk Base 20.000 50.000 0.000 10.000 clk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 50.000(MHz) 107.960(MHz) 5 TOP

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
clk Setup 0.000 0
clk Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 10.737 div_cnt_0_s0/Q div_cnt_22_s0/D clk:[R] clk:[R] 20.000 0.000 8.863
2 11.222 div_cnt_0_s0/Q div_cnt_19_s0/D clk:[R] clk:[R] 20.000 0.000 8.378
3 11.222 div_cnt_0_s0/Q div_cnt_20_s0/D clk:[R] clk:[R] 20.000 0.000 8.378
4 11.222 div_cnt_0_s0/Q div_cnt_21_s0/D clk:[R] clk:[R] 20.000 0.000 8.378
5 11.439 div_cnt_0_s0/Q div_cnt_17_s0/D clk:[R] clk:[R] 20.000 0.000 8.161
6 11.439 div_cnt_0_s0/Q div_cnt_16_s0/D clk:[R] clk:[R] 20.000 0.000 8.161
7 11.443 div_cnt_0_s0/Q div_cnt_23_s0/D clk:[R] clk:[R] 20.000 0.000 8.157
8 11.443 div_cnt_0_s0/Q div_cnt_24_s0/D clk:[R] clk:[R] 20.000 0.000 8.157
9 11.718 div_cnt_0_s0/Q div_cnt_15_s0/D clk:[R] clk:[R] 20.000 0.000 7.882
10 11.729 div_cnt_0_s0/Q div_cnt_12_s0/D clk:[R] clk:[R] 20.000 0.000 7.871
11 11.796 div_cnt_0_s0/Q div_cnt_6_s0/D clk:[R] clk:[R] 20.000 0.000 7.804
12 11.796 div_cnt_0_s0/Q div_cnt_10_s0/D clk:[R] clk:[R] 20.000 0.000 7.804
13 11.796 div_cnt_0_s0/Q div_cnt_11_s0/D clk:[R] clk:[R] 20.000 0.000 7.804
14 11.885 div_cnt_0_s0/Q tick_1hz_s0/D clk:[R] clk:[R] 20.000 0.000 7.715
15 11.936 div_cnt_0_s0/Q div_cnt_7_s0/D clk:[R] clk:[R] 20.000 0.000 7.664
16 12.143 div_cnt_0_s0/Q div_cnt_13_s0/D clk:[R] clk:[R] 20.000 0.000 7.457
17 12.143 div_cnt_0_s0/Q div_cnt_14_s0/D clk:[R] clk:[R] 20.000 0.000 7.457
18 12.644 div_cnt_0_s0/Q div_cnt_18_s0/D clk:[R] clk:[R] 20.000 0.000 6.956
19 12.941 div_cnt_0_s0/Q u_drv/step_cnt_10_s0/D clk:[R] clk:[R] 20.000 0.000 6.659
20 12.995 div_cnt_0_s0/Q u_drv/step_cnt_11_s0/D clk:[R] clk:[R] 20.000 0.000 6.605
21 13.142 div_cnt_0_s0/Q u_drv/step_cnt_12_s0/D clk:[R] clk:[R] 20.000 0.000 6.458
22 13.573 u_drv/step_cnt_10_s0/Q u_drv/step_cnt_4_s0/D clk:[R] clk:[R] 20.000 0.000 6.027
23 13.644 u_drv/step_cnt_10_s0/Q u_drv/step_cnt_6_s0/D clk:[R] clk:[R] 20.000 0.000 5.956
24 14.097 u_drv/step_cnt_10_s0/Q u_drv/step_cnt_1_s0/D clk:[R] clk:[R] 20.000 0.000 5.503
25 14.133 div_cnt_0_s0/Q u_drv/step_cnt_9_s0/D clk:[R] clk:[R] 20.000 0.000 5.467

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.708 u_drv/step_cnt_4_s0/Q u_drv/step_cnt_4_s0/D clk:[R] clk:[R] 0.000 0.000 0.708
2 0.708 div_cnt_24_s0/Q div_cnt_24_s0/D clk:[R] clk:[R] 0.000 0.000 0.708
3 0.708 div_cnt_1_s0/Q div_cnt_1_s0/D clk:[R] clk:[R] 0.000 0.000 0.708
4 0.708 div_cnt_3_s0/Q div_cnt_3_s0/D clk:[R] clk:[R] 0.000 0.000 0.708
5 0.708 div_cnt_18_s0/Q div_cnt_18_s0/D clk:[R] clk:[R] 0.000 0.000 0.708
6 0.709 u_drv/step_cnt_2_s0/Q u_drv/step_cnt_2_s0/D clk:[R] clk:[R] 0.000 0.000 0.709
7 0.709 u_drv/step_cnt_5_s0/Q u_drv/step_cnt_5_s0/D clk:[R] clk:[R] 0.000 0.000 0.709
8 0.709 u_drv/step_cnt_8_s0/Q u_drv/step_cnt_8_s0/D clk:[R] clk:[R] 0.000 0.000 0.709
9 0.709 u_drv/step_cnt_11_s0/Q u_drv/step_cnt_11_s0/D clk:[R] clk:[R] 0.000 0.000 0.709
10 0.709 d1_0_s1/Q d1_0_s1/D clk:[R] clk:[R] 0.000 0.000 0.709
11 0.709 d3_1_s0/Q d3_1_s0/D clk:[R] clk:[R] 0.000 0.000 0.709
12 0.709 d2_3_s0/Q d2_3_s0/D clk:[R] clk:[R] 0.000 0.000 0.709
13 0.709 d1_2_s0/Q d1_2_s0/D clk:[R] clk:[R] 0.000 0.000 0.709
14 0.709 div_cnt_11_s0/Q div_cnt_11_s0/D clk:[R] clk:[R] 0.000 0.000 0.709
15 0.709 div_cnt_13_s0/Q div_cnt_13_s0/D clk:[R] clk:[R] 0.000 0.000 0.709
16 0.709 div_cnt_15_s0/Q div_cnt_15_s0/D clk:[R] clk:[R] 0.000 0.000 0.709
17 0.709 div_cnt_17_s0/Q div_cnt_17_s0/D clk:[R] clk:[R] 0.000 0.000 0.709
18 0.709 div_cnt_20_s0/Q div_cnt_20_s0/D clk:[R] clk:[R] 0.000 0.000 0.709
19 0.709 div_cnt_22_s0/Q div_cnt_22_s0/D clk:[R] clk:[R] 0.000 0.000 0.709
20 0.710 d2_0_s1/Q d2_0_s1/D clk:[R] clk:[R] 0.000 0.000 0.710
21 0.710 d3_2_s0/Q d3_2_s0/D clk:[R] clk:[R] 0.000 0.000 0.710
22 0.710 d2_1_s0/Q d2_1_s0/D clk:[R] clk:[R] 0.000 0.000 0.710
23 0.710 d0_1_s0/Q d0_1_s0/D clk:[R] clk:[R] 0.000 0.000 0.710
24 0.710 div_cnt_0_s0/Q div_cnt_0_s0/D clk:[R] clk:[R] 0.000 0.000 0.710
25 0.710 div_cnt_4_s0/Q div_cnt_4_s0/D clk:[R] clk:[R] 0.000 0.000 0.710

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 6.521 7.771 1.250 High Pulse Width clk div_cnt_23_s0
2 6.521 7.771 1.250 High Pulse Width clk div_cnt_22_s0
3 6.521 7.771 1.250 High Pulse Width clk div_cnt_20_s0
4 6.521 7.771 1.250 High Pulse Width clk div_cnt_16_s0
5 6.521 7.771 1.250 High Pulse Width clk div_cnt_8_s0
6 6.521 7.771 1.250 High Pulse Width clk d1_1_s0
7 6.521 7.771 1.250 High Pulse Width clk d1_2_s0
8 6.521 7.771 1.250 High Pulse Width clk div_cnt_9_s0
9 6.521 7.771 1.250 High Pulse Width clk d1_3_s0
10 6.521 7.771 1.250 High Pulse Width clk d0_0_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 10.737
Data Arrival Time 14.454
Data Required Time 25.191
From div_cnt_0_s0
To div_cnt_22_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
4.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
5.591 1.361 tNET RR 1 R12C17[0][A] div_cnt_0_s0/CLK
6.049 0.458 tC2Q RF 10 R12C17[0][A] div_cnt_0_s0/Q
7.698 1.648 tNET FF 1 R9C13[1][B] n68_s3/I0
8.797 1.099 tINS FF 7 R9C13[1][B] n68_s3/F
9.795 0.998 tNET FF 1 R11C11[2][B] n59_s3/I0
10.894 1.099 tINS FF 7 R11C11[2][B] n59_s3/F
11.883 0.989 tNET FF 1 R12C10[2][B] n55_s3/I0
12.915 1.032 tINS FF 4 R12C10[2][B] n55_s3/F
13.422 0.506 tNET FF 1 R11C10[0][A] n55_s2/I0
14.454 1.032 tINS FF 1 R11C10[0][A] n55_s2/F
14.454 0.000 tNET FF 1 R11C10[0][A] div_cnt_22_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
24.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
25.591 1.361 tNET RR 1 R11C10[0][A] div_cnt_22_s0/CLK
25.191 -0.400 tSu 1 R11C10[0][A] div_cnt_22_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay cell: 4.262, 48.090%; route: 4.142, 46.739%; tC2Q: 0.458, 5.172%
Required Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%

Path2

Path Summary:

Slack 11.222
Data Arrival Time 13.969
Data Required Time 25.191
From div_cnt_0_s0
To div_cnt_19_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
4.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
5.591 1.361 tNET RR 1 R12C17[0][A] div_cnt_0_s0/CLK
6.049 0.458 tC2Q RF 10 R12C17[0][A] div_cnt_0_s0/Q
7.698 1.648 tNET FF 1 R9C13[1][B] n68_s3/I0
8.797 1.099 tINS FF 7 R9C13[1][B] n68_s3/F
9.795 0.998 tNET FF 1 R11C11[2][B] n59_s3/I0
10.894 1.099 tINS FF 7 R11C11[2][B] n59_s3/F
11.883 0.989 tNET FF 1 R12C10[2][B] n55_s3/I0
12.915 1.032 tINS FF 4 R12C10[2][B] n55_s3/F
12.937 0.022 tNET FF 1 R12C10[1][B] n58_s2/I1
13.969 1.032 tINS FF 1 R12C10[1][B] n58_s2/F
13.969 0.000 tNET FF 1 R12C10[1][B] div_cnt_19_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
24.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
25.591 1.361 tNET RR 1 R12C10[1][B] div_cnt_19_s0/CLK
25.191 -0.400 tSu 1 R12C10[1][B] div_cnt_19_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay cell: 4.262, 50.871%; route: 3.658, 43.658%; tC2Q: 0.458, 5.471%
Required Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%

Path3

Path Summary:

Slack 11.222
Data Arrival Time 13.969
Data Required Time 25.191
From div_cnt_0_s0
To div_cnt_20_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
4.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
5.591 1.361 tNET RR 1 R12C17[0][A] div_cnt_0_s0/CLK
6.049 0.458 tC2Q RF 10 R12C17[0][A] div_cnt_0_s0/Q
7.698 1.648 tNET FF 1 R9C13[1][B] n68_s3/I0
8.797 1.099 tINS FF 7 R9C13[1][B] n68_s3/F
9.795 0.998 tNET FF 1 R11C11[2][B] n59_s3/I0
10.894 1.099 tINS FF 7 R11C11[2][B] n59_s3/F
11.883 0.989 tNET FF 1 R12C10[2][B] n55_s3/I0
12.915 1.032 tINS FF 4 R12C10[2][B] n55_s3/F
12.937 0.022 tNET FF 1 R12C10[1][A] n57_s2/I0
13.969 1.032 tINS FF 1 R12C10[1][A] n57_s2/F
13.969 0.000 tNET FF 1 R12C10[1][A] div_cnt_20_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
24.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
25.591 1.361 tNET RR 1 R12C10[1][A] div_cnt_20_s0/CLK
25.191 -0.400 tSu 1 R12C10[1][A] div_cnt_20_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay cell: 4.262, 50.871%; route: 3.658, 43.658%; tC2Q: 0.458, 5.471%
Required Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%

Path4

Path Summary:

Slack 11.222
Data Arrival Time 13.969
Data Required Time 25.191
From div_cnt_0_s0
To div_cnt_21_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
4.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
5.591 1.361 tNET RR 1 R12C17[0][A] div_cnt_0_s0/CLK
6.049 0.458 tC2Q RF 10 R12C17[0][A] div_cnt_0_s0/Q
7.698 1.648 tNET FF 1 R9C13[1][B] n68_s3/I0
8.797 1.099 tINS FF 7 R9C13[1][B] n68_s3/F
9.795 0.998 tNET FF 1 R11C11[2][B] n59_s3/I0
10.894 1.099 tINS FF 7 R11C11[2][B] n59_s3/F
11.883 0.989 tNET FF 1 R12C10[2][B] n55_s3/I0
12.915 1.032 tINS FF 4 R12C10[2][B] n55_s3/F
12.937 0.022 tNET FF 1 R12C10[0][B] n56_s3/I0
13.969 1.032 tINS FF 1 R12C10[0][B] n56_s3/F
13.969 0.000 tNET FF 1 R12C10[0][B] div_cnt_21_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
24.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
25.591 1.361 tNET RR 1 R12C10[0][B] div_cnt_21_s0/CLK
25.191 -0.400 tSu 1 R12C10[0][B] div_cnt_21_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay cell: 4.262, 50.871%; route: 3.658, 43.658%; tC2Q: 0.458, 5.471%
Required Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%

Path5

Path Summary:

Slack 11.439
Data Arrival Time 13.752
Data Required Time 25.191
From div_cnt_0_s0
To div_cnt_17_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
4.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
5.591 1.361 tNET RR 1 R12C17[0][A] div_cnt_0_s0/CLK
6.049 0.458 tC2Q RF 10 R12C17[0][A] div_cnt_0_s0/Q
7.698 1.648 tNET FF 1 R9C13[1][B] n68_s3/I0
8.797 1.099 tINS FF 7 R9C13[1][B] n68_s3/F
9.795 0.998 tNET FF 1 R11C11[2][B] n59_s3/I0
10.894 1.099 tINS FF 7 R11C11[2][B] n59_s3/F
11.403 0.509 tNET FF 1 R11C9[2][A] n60_s4/I0
12.435 1.032 tINS FF 2 R11C9[2][A] n60_s4/F
12.930 0.495 tNET FF 1 R11C11[1][A] n60_s2/I0
13.752 0.822 tINS FF 1 R11C11[1][A] n60_s2/F
13.752 0.000 tNET FF 1 R11C11[1][A] div_cnt_17_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
24.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
25.591 1.361 tNET RR 1 R11C11[1][A] div_cnt_17_s0/CLK
25.191 -0.400 tSu 1 R11C11[1][A] div_cnt_17_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay cell: 4.052, 49.652%; route: 3.650, 44.731%; tC2Q: 0.458, 5.616%
Required Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%

Path6

Path Summary:

Slack 11.439
Data Arrival Time 13.752
Data Required Time 25.191
From div_cnt_0_s0
To div_cnt_16_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
4.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
5.591 1.361 tNET RR 1 R12C17[0][A] div_cnt_0_s0/CLK
6.049 0.458 tC2Q RF 10 R12C17[0][A] div_cnt_0_s0/Q
7.698 1.648 tNET FF 1 R9C13[1][B] n68_s3/I0
8.797 1.099 tINS FF 7 R9C13[1][B] n68_s3/F
9.795 0.998 tNET FF 1 R11C11[2][B] n59_s3/I0
10.894 1.099 tINS FF 7 R11C11[2][B] n59_s3/F
11.403 0.509 tNET FF 1 R11C9[2][A] n60_s4/I0
12.435 1.032 tINS FF 2 R11C9[2][A] n60_s4/F
12.930 0.495 tNET FF 1 R11C11[1][B] n61_s2/I1
13.752 0.822 tINS FF 1 R11C11[1][B] n61_s2/F
13.752 0.000 tNET FF 1 R11C11[1][B] div_cnt_16_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
24.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
25.591 1.361 tNET RR 1 R11C11[1][B] div_cnt_16_s0/CLK
25.191 -0.400 tSu 1 R11C11[1][B] div_cnt_16_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay cell: 4.052, 49.652%; route: 3.650, 44.731%; tC2Q: 0.458, 5.616%
Required Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%

Path7

Path Summary:

Slack 11.443
Data Arrival Time 13.748
Data Required Time 25.191
From div_cnt_0_s0
To div_cnt_23_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
4.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
5.591 1.361 tNET RR 1 R12C17[0][A] div_cnt_0_s0/CLK
6.049 0.458 tC2Q RF 10 R12C17[0][A] div_cnt_0_s0/Q
7.698 1.648 tNET FF 1 R9C13[1][B] n68_s3/I0
8.797 1.099 tINS FF 7 R9C13[1][B] n68_s3/F
9.795 0.998 tNET FF 1 R11C11[2][B] n59_s3/I0
10.894 1.099 tINS FF 7 R11C11[2][B] n59_s3/F
11.883 0.989 tNET FF 1 R12C10[3][A] n53_s3/I0
12.915 1.032 tINS FF 2 R12C10[3][A] n53_s3/F
12.926 0.011 tNET FF 1 R12C10[2][A] n54_s2/I1
13.748 0.822 tINS FF 1 R12C10[2][A] n54_s2/F
13.748 0.000 tNET FF 1 R12C10[2][A] div_cnt_23_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
24.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
25.591 1.361 tNET RR 1 R12C10[2][A] div_cnt_23_s0/CLK
25.191 -0.400 tSu 1 R12C10[2][A] div_cnt_23_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay cell: 4.052, 49.675%; route: 3.647, 44.707%; tC2Q: 0.458, 5.619%
Required Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%

Path8

Path Summary:

Slack 11.443
Data Arrival Time 13.748
Data Required Time 25.191
From div_cnt_0_s0
To div_cnt_24_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
4.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
5.591 1.361 tNET RR 1 R12C17[0][A] div_cnt_0_s0/CLK
6.049 0.458 tC2Q RF 10 R12C17[0][A] div_cnt_0_s0/Q
7.698 1.648 tNET FF 1 R9C13[1][B] n68_s3/I0
8.797 1.099 tINS FF 7 R9C13[1][B] n68_s3/F
9.795 0.998 tNET FF 1 R11C11[2][B] n59_s3/I0
10.894 1.099 tINS FF 7 R11C11[2][B] n59_s3/F
11.883 0.989 tNET FF 1 R12C10[3][A] n53_s3/I0
12.915 1.032 tINS FF 2 R12C10[3][A] n53_s3/F
12.926 0.011 tNET FF 1 R12C10[0][A] n53_s2/I0
13.748 0.822 tINS FF 1 R12C10[0][A] n53_s2/F
13.748 0.000 tNET FF 1 R12C10[0][A] div_cnt_24_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
24.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
25.591 1.361 tNET RR 1 R12C10[0][A] div_cnt_24_s0/CLK
25.191 -0.400 tSu 1 R12C10[0][A] div_cnt_24_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay cell: 4.052, 49.675%; route: 3.647, 44.707%; tC2Q: 0.458, 5.619%
Required Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%

Path9

Path Summary:

Slack 11.718
Data Arrival Time 13.473
Data Required Time 25.191
From div_cnt_0_s0
To div_cnt_15_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
4.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
5.591 1.361 tNET RR 1 R12C17[0][A] div_cnt_0_s0/CLK
6.049 0.458 tC2Q RF 10 R12C17[0][A] div_cnt_0_s0/Q
7.698 1.648 tNET FF 1 R9C13[1][B] n68_s3/I0
8.797 1.099 tINS FF 7 R9C13[1][B] n68_s3/F
9.795 0.998 tNET FF 1 R11C11[2][B] n59_s3/I0
10.894 1.099 tINS FF 7 R11C11[2][B] n59_s3/F
11.403 0.509 tNET FF 1 R11C9[2][B] n62_s3/I0
12.435 1.032 tINS FF 1 R11C9[2][B] n62_s3/F
12.441 0.005 tNET FF 1 R11C9[1][A] n62_s2/I1
13.473 1.032 tINS FF 1 R11C9[1][A] n62_s2/F
13.473 0.000 tNET FF 1 R11C9[1][A] div_cnt_15_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
24.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
25.591 1.361 tNET RR 1 R11C9[1][A] div_cnt_15_s0/CLK
25.191 -0.400 tSu 1 R11C9[1][A] div_cnt_15_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay cell: 4.262, 54.075%; route: 3.161, 40.110%; tC2Q: 0.458, 5.815%
Required Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%

Path10

Path Summary:

Slack 11.729
Data Arrival Time 13.462
Data Required Time 25.191
From div_cnt_0_s0
To div_cnt_12_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
4.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
5.591 1.361 tNET RR 1 R12C17[0][A] div_cnt_0_s0/CLK
6.049 0.458 tC2Q RF 10 R12C17[0][A] div_cnt_0_s0/Q
7.698 1.648 tNET FF 1 R9C13[1][B] n68_s3/I0
8.797 1.099 tINS FF 7 R9C13[1][B] n68_s3/F
9.607 0.810 tNET FF 1 R11C12[0][B] n26_s3/I0
10.233 0.626 tINS FF 3 R11C12[0][B] n26_s3/F
10.727 0.495 tNET FF 1 R11C10[3][B] n26_s1/I1
11.826 1.099 tINS FF 15 R11C10[3][B] n26_s1/F
12.363 0.537 tNET FF 1 R9C10[2][A] n65_s2/I2
13.462 1.099 tINS FF 1 R9C10[2][A] n65_s2/F
13.462 0.000 tNET FF 1 R9C10[2][A] div_cnt_12_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
24.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
25.591 1.361 tNET RR 1 R9C10[2][A] div_cnt_12_s0/CLK
25.191 -0.400 tSu 1 R9C10[2][A] div_cnt_12_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay cell: 3.923, 49.843%; route: 3.489, 44.333%; tC2Q: 0.458, 5.823%
Required Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%

Path11

Path Summary:

Slack 11.796
Data Arrival Time 13.395
Data Required Time 25.191
From div_cnt_0_s0
To div_cnt_6_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
4.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
5.591 1.361 tNET RR 1 R12C17[0][A] div_cnt_0_s0/CLK
6.049 0.458 tC2Q RF 10 R12C17[0][A] div_cnt_0_s0/Q
7.698 1.648 tNET FF 1 R9C13[1][B] n68_s3/I0
8.797 1.099 tINS FF 7 R9C13[1][B] n68_s3/F
9.607 0.810 tNET FF 1 R11C12[0][B] n26_s3/I0
10.233 0.626 tINS FF 3 R11C12[0][B] n26_s3/F
10.727 0.495 tNET FF 1 R11C10[3][B] n26_s1/I1
11.826 1.099 tINS FF 15 R11C10[3][B] n26_s1/F
12.363 0.537 tNET FF 1 R9C10[0][B] n71_s2/I0
13.395 1.032 tINS FF 1 R9C10[0][B] n71_s2/F
13.395 0.000 tNET FF 1 R9C10[0][B] div_cnt_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
24.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
25.591 1.361 tNET RR 1 R9C10[0][B] div_cnt_6_s0/CLK
25.191 -0.400 tSu 1 R9C10[0][B] div_cnt_6_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay cell: 3.856, 49.413%; route: 3.489, 44.714%; tC2Q: 0.458, 5.873%
Required Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%

Path12

Path Summary:

Slack 11.796
Data Arrival Time 13.395
Data Required Time 25.191
From div_cnt_0_s0
To div_cnt_10_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
4.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
5.591 1.361 tNET RR 1 R12C17[0][A] div_cnt_0_s0/CLK
6.049 0.458 tC2Q RF 10 R12C17[0][A] div_cnt_0_s0/Q
7.698 1.648 tNET FF 1 R9C13[1][B] n68_s3/I0
8.797 1.099 tINS FF 7 R9C13[1][B] n68_s3/F
9.607 0.810 tNET FF 1 R11C12[0][B] n26_s3/I0
10.233 0.626 tINS FF 3 R11C12[0][B] n26_s3/F
10.727 0.495 tNET FF 1 R11C10[3][B] n26_s1/I1
11.826 1.099 tINS FF 15 R11C10[3][B] n26_s1/F
12.363 0.537 tNET FF 1 R9C10[1][B] n67_s2/I0
13.395 1.032 tINS FF 1 R9C10[1][B] n67_s2/F
13.395 0.000 tNET FF 1 R9C10[1][B] div_cnt_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
24.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
25.591 1.361 tNET RR 1 R9C10[1][B] div_cnt_10_s0/CLK
25.191 -0.400 tSu 1 R9C10[1][B] div_cnt_10_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay cell: 3.856, 49.413%; route: 3.489, 44.714%; tC2Q: 0.458, 5.873%
Required Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%

Path13

Path Summary:

Slack 11.796
Data Arrival Time 13.395
Data Required Time 25.191
From div_cnt_0_s0
To div_cnt_11_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
4.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
5.591 1.361 tNET RR 1 R12C17[0][A] div_cnt_0_s0/CLK
6.049 0.458 tC2Q RF 10 R12C17[0][A] div_cnt_0_s0/Q
7.698 1.648 tNET FF 1 R9C13[1][B] n68_s3/I0
8.797 1.099 tINS FF 7 R9C13[1][B] n68_s3/F
9.607 0.810 tNET FF 1 R11C12[0][B] n26_s3/I0
10.233 0.626 tINS FF 3 R11C12[0][B] n26_s3/F
10.727 0.495 tNET FF 1 R11C10[3][B] n26_s1/I1
11.826 1.099 tINS FF 15 R11C10[3][B] n26_s1/F
12.363 0.537 tNET FF 1 R9C10[1][A] n66_s2/I2
13.395 1.032 tINS FF 1 R9C10[1][A] n66_s2/F
13.395 0.000 tNET FF 1 R9C10[1][A] div_cnt_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
24.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
25.591 1.361 tNET RR 1 R9C10[1][A] div_cnt_11_s0/CLK
25.191 -0.400 tSu 1 R9C10[1][A] div_cnt_11_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay cell: 3.856, 49.413%; route: 3.489, 44.714%; tC2Q: 0.458, 5.873%
Required Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%

Path14

Path Summary:

Slack 11.885
Data Arrival Time 13.306
Data Required Time 25.191
From div_cnt_0_s0
To tick_1hz_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
4.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
5.591 1.361 tNET RR 1 R12C17[0][A] div_cnt_0_s0/CLK
6.049 0.458 tC2Q RF 10 R12C17[0][A] div_cnt_0_s0/Q
7.698 1.648 tNET FF 1 R9C13[1][B] n68_s3/I0
8.797 1.099 tINS FF 7 R9C13[1][B] n68_s3/F
9.607 0.810 tNET FF 1 R11C12[0][B] n26_s3/I0
10.233 0.626 tINS FF 3 R11C12[0][B] n26_s3/F
10.727 0.495 tNET FF 1 R11C10[3][B] n26_s1/I1
11.826 1.099 tINS FF 15 R11C10[3][B] n26_s1/F
13.306 1.480 tNET FF 1 R11C12[0][A] tick_1hz_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
24.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
25.591 1.361 tNET RR 1 R11C12[0][A] tick_1hz_s0/CLK
25.191 -0.400 tSu 1 R11C12[0][A] tick_1hz_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 4
Arrival Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay cell: 2.824, 36.605%; route: 4.432, 57.454%; tC2Q: 0.458, 5.941%
Required Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%

Path15

Path Summary:

Slack 11.936
Data Arrival Time 13.255
Data Required Time 25.191
From div_cnt_0_s0
To div_cnt_7_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
4.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
5.591 1.361 tNET RR 1 R12C17[0][A] div_cnt_0_s0/CLK
6.049 0.458 tC2Q RF 10 R12C17[0][A] div_cnt_0_s0/Q
7.698 1.648 tNET FF 1 R9C13[1][B] n68_s3/I0
8.797 1.099 tINS FF 7 R9C13[1][B] n68_s3/F
9.607 0.810 tNET FF 1 R11C12[0][B] n26_s3/I0
10.233 0.626 tINS FF 3 R11C12[0][B] n26_s3/F
10.727 0.495 tNET FF 1 R11C10[3][B] n26_s1/I1
11.788 1.061 tINS FR 15 R11C10[3][B] n26_s1/F
12.223 0.434 tNET RR 1 R11C11[2][A] n70_s2/I2
13.255 1.032 tINS RF 1 R11C11[2][A] n70_s2/F
13.255 0.000 tNET FF 1 R11C11[2][A] div_cnt_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
24.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
25.591 1.361 tNET RR 1 R11C11[2][A] div_cnt_7_s0/CLK
25.191 -0.400 tSu 1 R11C11[2][A] div_cnt_7_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay cell: 3.818, 49.820%; route: 3.387, 44.199%; tC2Q: 0.458, 5.981%
Required Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%

Path16

Path Summary:

Slack 12.143
Data Arrival Time 13.049
Data Required Time 25.191
From div_cnt_0_s0
To div_cnt_13_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
4.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
5.591 1.361 tNET RR 1 R12C17[0][A] div_cnt_0_s0/CLK
6.049 0.458 tC2Q RF 10 R12C17[0][A] div_cnt_0_s0/Q
7.698 1.648 tNET FF 1 R9C13[1][B] n68_s3/I0
8.797 1.099 tINS FF 7 R9C13[1][B] n68_s3/F
9.607 0.810 tNET FF 1 R11C12[0][B] n26_s3/I0
10.233 0.626 tINS FF 3 R11C12[0][B] n26_s3/F
10.727 0.495 tNET FF 1 R11C10[3][B] n26_s1/I1
11.788 1.061 tINS FR 15 R11C10[3][B] n26_s1/F
12.227 0.438 tNET RR 1 R11C9[0][A] n64_s2/I0
13.049 0.822 tINS RF 1 R11C9[0][A] n64_s2/F
13.049 0.000 tNET FF 1 R11C9[0][A] div_cnt_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
24.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
25.591 1.361 tNET RR 1 R11C9[0][A] div_cnt_13_s0/CLK
25.191 -0.400 tSu 1 R11C9[0][A] div_cnt_13_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay cell: 3.608, 48.381%; route: 3.391, 45.473%; tC2Q: 0.458, 6.146%
Required Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%

Path17

Path Summary:

Slack 12.143
Data Arrival Time 13.049
Data Required Time 25.191
From div_cnt_0_s0
To div_cnt_14_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
4.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
5.591 1.361 tNET RR 1 R12C17[0][A] div_cnt_0_s0/CLK
6.049 0.458 tC2Q RF 10 R12C17[0][A] div_cnt_0_s0/Q
7.698 1.648 tNET FF 1 R9C13[1][B] n68_s3/I0
8.797 1.099 tINS FF 7 R9C13[1][B] n68_s3/F
9.607 0.810 tNET FF 1 R11C12[0][B] n26_s3/I0
10.233 0.626 tINS FF 3 R11C12[0][B] n26_s3/F
10.727 0.495 tNET FF 1 R11C10[3][B] n26_s1/I1
11.788 1.061 tINS FR 15 R11C10[3][B] n26_s1/F
12.227 0.438 tNET RR 1 R11C9[0][B] n63_s2/I2
13.049 0.822 tINS RF 1 R11C9[0][B] n63_s2/F
13.049 0.000 tNET FF 1 R11C9[0][B] div_cnt_14_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
24.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
25.591 1.361 tNET RR 1 R11C9[0][B] div_cnt_14_s0/CLK
25.191 -0.400 tSu 1 R11C9[0][B] div_cnt_14_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay cell: 3.608, 48.381%; route: 3.391, 45.473%; tC2Q: 0.458, 6.146%
Required Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%

Path18

Path Summary:

Slack 12.644
Data Arrival Time 12.547
Data Required Time 25.191
From div_cnt_0_s0
To div_cnt_18_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
4.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
5.591 1.361 tNET RR 1 R12C17[0][A] div_cnt_0_s0/CLK
6.049 0.458 tC2Q RF 10 R12C17[0][A] div_cnt_0_s0/Q
7.698 1.648 tNET FF 1 R9C13[1][B] n68_s3/I0
8.797 1.099 tINS FF 7 R9C13[1][B] n68_s3/F
9.795 0.998 tNET FF 1 R11C11[2][B] n59_s3/I0
10.894 1.099 tINS FF 7 R11C11[2][B] n59_s3/F
11.725 0.831 tNET FF 1 R12C11[0][A] n59_s2/I0
12.547 0.822 tINS FF 1 R12C11[0][A] n59_s2/F
12.547 0.000 tNET FF 1 R12C11[0][A] div_cnt_18_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
24.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
25.591 1.361 tNET RR 1 R12C11[0][A] div_cnt_18_s0/CLK
25.191 -0.400 tSu 1 R12C11[0][A] div_cnt_18_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 4
Arrival Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay cell: 3.020, 43.417%; route: 3.477, 49.994%; tC2Q: 0.458, 6.589%
Required Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%

Path19

Path Summary:

Slack 12.941
Data Arrival Time 12.250
Data Required Time 25.191
From div_cnt_0_s0
To u_drv/step_cnt_10_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
4.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
5.591 1.361 tNET RR 1 R12C17[0][A] div_cnt_0_s0/CLK
6.049 0.458 tC2Q RF 10 R12C17[0][A] div_cnt_0_s0/Q
6.878 0.829 tNET FF 1 R12C16[3][A] u_drv/n41_s3/I0
7.680 0.802 tINS FR 4 R12C16[3][A] u_drv/n41_s3/F
8.107 0.427 tNET RR 1 R11C16[2][B] u_drv/n38_s3/I0
9.139 1.032 tINS RF 4 R11C16[2][B] u_drv/n38_s3/F
9.971 0.832 tNET FF 1 R11C17[0][B] u_drv/n35_s3/I0
10.597 0.626 tINS FF 3 R11C17[0][B] u_drv/n35_s3/F
11.428 0.831 tNET FF 1 R9C17[1][B] u_drv/n35_s2/I0
12.250 0.822 tINS FF 1 R9C17[1][B] u_drv/n35_s2/F
12.250 0.000 tNET FF 1 R9C17[1][B] u_drv/step_cnt_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
24.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
25.591 1.361 tNET RR 1 R9C17[1][B] u_drv/step_cnt_10_s0/CLK
25.191 -0.400 tSu 1 R9C17[1][B] u_drv/step_cnt_10_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay cell: 3.282, 49.288%; route: 2.918, 43.829%; tC2Q: 0.458, 6.883%
Required Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%

Path20

Path Summary:

Slack 12.995
Data Arrival Time 12.196
Data Required Time 25.191
From div_cnt_0_s0
To u_drv/step_cnt_11_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
4.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
5.591 1.361 tNET RR 1 R12C17[0][A] div_cnt_0_s0/CLK
6.049 0.458 tC2Q RF 10 R12C17[0][A] div_cnt_0_s0/Q
6.878 0.829 tNET FF 1 R12C16[3][A] u_drv/n41_s3/I0
7.680 0.802 tINS FR 4 R12C16[3][A] u_drv/n41_s3/F
8.107 0.427 tNET RR 1 R11C16[2][B] u_drv/n38_s3/I0
9.139 1.032 tINS RF 4 R11C16[2][B] u_drv/n38_s3/F
9.971 0.832 tNET FF 1 R11C17[0][B] u_drv/n35_s3/I0
10.597 0.626 tINS FF 3 R11C17[0][B] u_drv/n35_s3/F
11.097 0.500 tNET FF 1 R9C17[1][A] u_drv/n34_s2/I0
12.196 1.099 tINS FF 1 R9C17[1][A] u_drv/n34_s2/F
12.196 0.000 tNET FF 1 R9C17[1][A] u_drv/step_cnt_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
24.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
25.591 1.361 tNET RR 1 R9C17[1][A] u_drv/step_cnt_11_s0/CLK
25.191 -0.400 tSu 1 R9C17[1][A] u_drv/step_cnt_11_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay cell: 3.559, 53.884%; route: 2.588, 39.177%; tC2Q: 0.458, 6.939%
Required Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%

Path21

Path Summary:

Slack 13.142
Data Arrival Time 12.049
Data Required Time 25.191
From div_cnt_0_s0
To u_drv/step_cnt_12_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
4.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
5.591 1.361 tNET RR 1 R12C17[0][A] div_cnt_0_s0/CLK
6.049 0.458 tC2Q RF 10 R12C17[0][A] div_cnt_0_s0/Q
6.878 0.829 tNET FF 1 R12C16[3][A] u_drv/n41_s3/I0
7.680 0.802 tINS FR 4 R12C16[3][A] u_drv/n41_s3/F
8.107 0.427 tNET RR 1 R11C16[2][B] u_drv/n38_s3/I0
9.139 1.032 tINS RF 4 R11C16[2][B] u_drv/n38_s3/F
9.971 0.832 tNET FF 1 R11C17[0][B] u_drv/n35_s3/I0
10.596 0.625 tINS FR 3 R11C17[0][B] u_drv/n35_s3/F
11.017 0.421 tNET RR 1 R11C16[0][B] u_drv/n33_s2/I0
12.049 1.032 tINS RF 1 R11C16[0][B] u_drv/n33_s2/F
12.049 0.000 tNET FF 1 R11C16[0][B] u_drv/step_cnt_12_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
24.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
25.591 1.361 tNET RR 1 R11C16[0][B] u_drv/step_cnt_12_s0/CLK
25.191 -0.400 tSu 1 R11C16[0][B] u_drv/step_cnt_12_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay cell: 3.491, 54.059%; route: 2.508, 38.843%; tC2Q: 0.458, 7.097%
Required Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%

Path22

Path Summary:

Slack 13.573
Data Arrival Time 11.618
Data Required Time 25.191
From u_drv/step_cnt_10_s0
To u_drv/step_cnt_4_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
4.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
5.591 1.361 tNET RR 1 R9C17[1][B] u_drv/step_cnt_10_s0/CLK
6.049 0.458 tC2Q RF 4 R9C17[1][B] u_drv/step_cnt_10_s0/Q
7.350 1.300 tNET FF 1 R11C16[2][A] u_drv/n15_s2/I1
8.152 0.802 tINS FR 2 R11C16[2][A] u_drv/n15_s2/F
8.573 0.421 tNET RR 1 R12C16[1][B] u_drv/n15_s1/I0
9.672 1.099 tINS RF 9 R12C16[1][B] u_drv/n15_s1/F
10.519 0.848 tNET FF 1 R9C16[1][A] u_drv/n41_s2/I0
11.618 1.099 tINS FF 1 R9C16[1][A] u_drv/n41_s2/F
11.618 0.000 tNET FF 1 R9C16[1][A] u_drv/step_cnt_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
24.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
25.591 1.361 tNET RR 1 R9C16[1][A] u_drv/step_cnt_4_s0/CLK
25.191 -0.400 tSu 1 R9C16[1][A] u_drv/step_cnt_4_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 4
Arrival Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay cell: 3.000, 49.775%; route: 2.569, 42.620%; tC2Q: 0.458, 7.605%
Required Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%

Path23

Path Summary:

Slack 13.644
Data Arrival Time 11.547
Data Required Time 25.191
From u_drv/step_cnt_10_s0
To u_drv/step_cnt_6_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
4.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
5.591 1.361 tNET RR 1 R9C17[1][B] u_drv/step_cnt_10_s0/CLK
6.049 0.458 tC2Q RF 4 R9C17[1][B] u_drv/step_cnt_10_s0/Q
7.350 1.300 tNET FF 1 R11C16[2][A] u_drv/n15_s2/I1
8.152 0.802 tINS FR 2 R11C16[2][A] u_drv/n15_s2/F
8.573 0.421 tNET RR 1 R12C16[1][B] u_drv/n15_s1/I0
9.672 1.099 tINS RF 9 R12C16[1][B] u_drv/n15_s1/F
10.515 0.843 tNET FF 1 R9C16[1][B] u_drv/n39_s2/I0
11.547 1.032 tINS FF 1 R9C16[1][B] u_drv/n39_s2/F
11.547 0.000 tNET FF 1 R9C16[1][B] u_drv/step_cnt_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
24.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
25.591 1.361 tNET RR 1 R9C16[1][B] u_drv/step_cnt_6_s0/CLK
25.191 -0.400 tSu 1 R9C16[1][B] u_drv/step_cnt_6_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 4
Arrival Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay cell: 2.933, 49.248%; route: 2.564, 43.056%; tC2Q: 0.458, 7.696%
Required Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%

Path24

Path Summary:

Slack 14.097
Data Arrival Time 11.094
Data Required Time 25.191
From u_drv/step_cnt_10_s0
To u_drv/step_cnt_1_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
4.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
5.591 1.361 tNET RR 1 R9C17[1][B] u_drv/step_cnt_10_s0/CLK
6.049 0.458 tC2Q RF 4 R9C17[1][B] u_drv/step_cnt_10_s0/Q
7.350 1.300 tNET FF 1 R11C16[2][A] u_drv/n15_s2/I1
8.152 0.802 tINS FR 2 R11C16[2][A] u_drv/n15_s2/F
8.573 0.421 tNET RR 1 R12C16[1][B] u_drv/n15_s1/I0
9.634 1.061 tINS RR 9 R12C16[1][B] u_drv/n15_s1/F
10.062 0.429 tNET RR 1 R12C17[0][B] u_drv/n44_s2/I0
11.094 1.032 tINS RF 1 R12C17[0][B] u_drv/n44_s2/F
11.094 0.000 tNET FF 1 R12C17[0][B] u_drv/step_cnt_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
24.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
25.591 1.361 tNET RR 1 R12C17[0][B] u_drv/step_cnt_1_s0/CLK
25.191 -0.400 tSu 1 R12C17[0][B] u_drv/step_cnt_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 4
Arrival Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay cell: 2.895, 52.608%; route: 2.150, 39.064%; tC2Q: 0.458, 8.329%
Required Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%

Path25

Path Summary:

Slack 14.133
Data Arrival Time 11.058
Data Required Time 25.191
From div_cnt_0_s0
To u_drv/step_cnt_9_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
4.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
5.591 1.361 tNET RR 1 R12C17[0][A] div_cnt_0_s0/CLK
6.049 0.458 tC2Q RF 10 R12C17[0][A] div_cnt_0_s0/Q
6.878 0.829 tNET FF 1 R12C16[3][A] u_drv/n41_s3/I0
7.680 0.802 tINS FR 4 R12C16[3][A] u_drv/n41_s3/F
8.107 0.427 tNET RR 1 R11C16[2][B] u_drv/n38_s3/I0
9.139 1.032 tINS RF 4 R11C16[2][B] u_drv/n38_s3/F
9.959 0.820 tNET FF 1 R12C17[2][B] u_drv/n36_s5/I1
11.058 1.099 tINS FF 1 R12C17[2][B] u_drv/n36_s5/F
11.058 0.000 tNET FF 1 R12C17[2][B] u_drv/step_cnt_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
24.230 4.230 tINS RR 56 IOT13[A] clk_ibuf/O
25.591 1.361 tNET RR 1 R12C17[2][B] u_drv/step_cnt_9_s0/CLK
25.191 -0.400 tSu 1 R12C17[2][B] u_drv/step_cnt_9_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 4
Arrival Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay cell: 2.933, 53.650%; route: 2.076, 37.967%; tC2Q: 0.458, 8.384%
Required Clock Path Delay cell: 4.230, 75.653%; route: 1.361, 24.347%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.708
Data Arrival Time 4.800
Data Required Time 4.093
From u_drv/step_cnt_4_s0
To u_drv/step_cnt_4_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R9C16[1][A] u_drv/step_cnt_4_s0/CLK
4.426 0.333 tC2Q RR 5 R9C16[1][A] u_drv/step_cnt_4_s0/Q
4.428 0.002 tNET RR 1 R9C16[1][A] u_drv/n41_s2/I2
4.800 0.372 tINS RF 1 R9C16[1][A] u_drv/n41_s2/F
4.800 0.000 tNET FF 1 R9C16[1][A] u_drv/step_cnt_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R9C16[1][A] u_drv/step_cnt_4_s0/CLK
4.093 0.000 tHld 1 R9C16[1][A] u_drv/step_cnt_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%

Path2

Path Summary:

Slack 0.708
Data Arrival Time 4.800
Data Required Time 4.093
From div_cnt_24_s0
To div_cnt_24_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R12C10[0][A] div_cnt_24_s0/CLK
4.426 0.333 tC2Q RR 2 R12C10[0][A] div_cnt_24_s0/Q
4.428 0.002 tNET RR 1 R12C10[0][A] n53_s2/I3
4.800 0.372 tINS RF 1 R12C10[0][A] n53_s2/F
4.800 0.000 tNET FF 1 R12C10[0][A] div_cnt_24_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R12C10[0][A] div_cnt_24_s0/CLK
4.093 0.000 tHld 1 R12C10[0][A] div_cnt_24_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%

Path3

Path Summary:

Slack 0.708
Data Arrival Time 4.800
Data Required Time 4.093
From div_cnt_1_s0
To div_cnt_1_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R9C13[1][A] div_cnt_1_s0/CLK
4.426 0.333 tC2Q RR 4 R9C13[1][A] div_cnt_1_s0/Q
4.428 0.002 tNET RR 1 R9C13[1][A] n76_s2/I1
4.800 0.372 tINS RF 1 R9C13[1][A] n76_s2/F
4.800 0.000 tNET FF 1 R9C13[1][A] div_cnt_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R9C13[1][A] div_cnt_1_s0/CLK
4.093 0.000 tHld 1 R9C13[1][A] div_cnt_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%

Path4

Path Summary:

Slack 0.708
Data Arrival Time 4.800
Data Required Time 4.093
From div_cnt_3_s0
To div_cnt_3_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R9C13[0][A] div_cnt_3_s0/CLK
4.426 0.333 tC2Q RR 2 R9C13[0][A] div_cnt_3_s0/Q
4.428 0.002 tNET RR 1 R9C13[0][A] n74_s2/I3
4.800 0.372 tINS RF 1 R9C13[0][A] n74_s2/F
4.800 0.000 tNET FF 1 R9C13[0][A] div_cnt_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R9C13[0][A] div_cnt_3_s0/CLK
4.093 0.000 tHld 1 R9C13[0][A] div_cnt_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%

Path5

Path Summary:

Slack 0.708
Data Arrival Time 4.800
Data Required Time 4.093
From div_cnt_18_s0
To div_cnt_18_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R12C11[0][A] div_cnt_18_s0/CLK
4.426 0.333 tC2Q RR 4 R12C11[0][A] div_cnt_18_s0/Q
4.428 0.002 tNET RR 1 R12C11[0][A] n59_s2/I3
4.800 0.372 tINS RF 1 R12C11[0][A] n59_s2/F
4.800 0.000 tNET FF 1 R12C11[0][A] div_cnt_18_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R12C11[0][A] div_cnt_18_s0/CLK
4.093 0.000 tHld 1 R12C11[0][A] div_cnt_18_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%

Path6

Path Summary:

Slack 0.709
Data Arrival Time 4.802
Data Required Time 4.093
From u_drv/step_cnt_2_s0
To u_drv/step_cnt_2_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R12C16[1][A] u_drv/step_cnt_2_s0/CLK
4.426 0.333 tC2Q RR 4 R12C16[1][A] u_drv/step_cnt_2_s0/Q
4.430 0.004 tNET RR 1 R12C16[1][A] u_drv/n43_s2/I3
4.802 0.372 tINS RF 1 R12C16[1][A] u_drv/n43_s2/F
4.802 0.000 tNET FF 1 R12C16[1][A] u_drv/step_cnt_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R12C16[1][A] u_drv/step_cnt_2_s0/CLK
4.093 0.000 tHld 1 R12C16[1][A] u_drv/step_cnt_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%

Path7

Path Summary:

Slack 0.709
Data Arrival Time 4.802
Data Required Time 4.093
From u_drv/step_cnt_5_s0
To u_drv/step_cnt_5_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R11C16[0][A] u_drv/step_cnt_5_s0/CLK
4.426 0.333 tC2Q RR 4 R11C16[0][A] u_drv/step_cnt_5_s0/Q
4.430 0.004 tNET RR 1 R11C16[0][A] u_drv/n40_s2/I2
4.802 0.372 tINS RF 1 R11C16[0][A] u_drv/n40_s2/F
4.802 0.000 tNET FF 1 R11C16[0][A] u_drv/step_cnt_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R11C16[0][A] u_drv/step_cnt_5_s0/CLK
4.093 0.000 tHld 1 R11C16[0][A] u_drv/step_cnt_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%

Path8

Path Summary:

Slack 0.709
Data Arrival Time 4.802
Data Required Time 4.093
From u_drv/step_cnt_8_s0
To u_drv/step_cnt_8_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R12C17[1][A] u_drv/step_cnt_8_s0/CLK
4.426 0.333 tC2Q RR 4 R12C17[1][A] u_drv/step_cnt_8_s0/Q
4.430 0.004 tNET RR 1 R12C17[1][A] u_drv/n37_s2/I2
4.802 0.372 tINS RF 1 R12C17[1][A] u_drv/n37_s2/F
4.802 0.000 tNET FF 1 R12C17[1][A] u_drv/step_cnt_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R12C17[1][A] u_drv/step_cnt_8_s0/CLK
4.093 0.000 tHld 1 R12C17[1][A] u_drv/step_cnt_8_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%

Path9

Path Summary:

Slack 0.709
Data Arrival Time 4.802
Data Required Time 4.093
From u_drv/step_cnt_11_s0
To u_drv/step_cnt_11_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R9C17[1][A] u_drv/step_cnt_11_s0/CLK
4.426 0.333 tC2Q RR 3 R9C17[1][A] u_drv/step_cnt_11_s0/Q
4.430 0.004 tNET RR 1 R9C17[1][A] u_drv/n34_s2/I3
4.802 0.372 tINS RF 1 R9C17[1][A] u_drv/n34_s2/F
4.802 0.000 tNET FF 1 R9C17[1][A] u_drv/step_cnt_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R9C17[1][A] u_drv/step_cnt_11_s0/CLK
4.093 0.000 tHld 1 R9C17[1][A] u_drv/step_cnt_11_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%

Path10

Path Summary:

Slack 0.709
Data Arrival Time 4.802
Data Required Time 4.093
From d1_0_s1
To d1_0_s1
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R11C14[0][A] d1_0_s1/CLK
4.426 0.333 tC2Q RR 6 R11C14[0][A] d1_0_s1/Q
4.430 0.004 tNET RR 1 R11C14[0][A] n150_s7/I0
4.802 0.372 tINS RF 1 R11C14[0][A] n150_s7/F
4.802 0.000 tNET FF 1 R11C14[0][A] d1_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R11C14[0][A] d1_0_s1/CLK
4.093 0.000 tHld 1 R11C14[0][A] d1_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%

Path11

Path Summary:

Slack 0.709
Data Arrival Time 4.802
Data Required Time 4.093
From d3_1_s0
To d3_1_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R11C15[1][A] d3_1_s0/CLK
4.426 0.333 tC2Q RR 4 R11C15[1][A] d3_1_s0/Q
4.430 0.004 tNET RR 1 R11C15[1][A] n127_s2/I2
4.802 0.372 tINS RF 1 R11C15[1][A] n127_s2/F
4.802 0.000 tNET FF 1 R11C15[1][A] d3_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R11C15[1][A] d3_1_s0/CLK
4.093 0.000 tHld 1 R11C15[1][A] d3_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%

Path12

Path Summary:

Slack 0.709
Data Arrival Time 4.802
Data Required Time 4.093
From d2_3_s0
To d2_3_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R12C15[0][A] d2_3_s0/CLK
4.426 0.333 tC2Q RR 3 R12C15[0][A] d2_3_s0/Q
4.430 0.004 tNET RR 1 R12C15[0][A] n134_s2/I3
4.802 0.372 tINS RF 1 R12C15[0][A] n134_s2/F
4.802 0.000 tNET FF 1 R12C15[0][A] d2_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R12C15[0][A] d2_3_s0/CLK
4.093 0.000 tHld 1 R12C15[0][A] d2_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%

Path13

Path Summary:

Slack 0.709
Data Arrival Time 4.802
Data Required Time 4.093
From d1_2_s0
To d1_2_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R11C14[1][A] d1_2_s0/CLK
4.426 0.333 tC2Q RR 4 R11C14[1][A] d1_2_s0/Q
4.430 0.004 tNET RR 1 R11C14[1][A] n148_s2/I2
4.802 0.372 tINS RF 1 R11C14[1][A] n148_s2/F
4.802 0.000 tNET FF 1 R11C14[1][A] d1_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R11C14[1][A] d1_2_s0/CLK
4.093 0.000 tHld 1 R11C14[1][A] d1_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%

Path14

Path Summary:

Slack 0.709
Data Arrival Time 4.802
Data Required Time 4.093
From div_cnt_11_s0
To div_cnt_11_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R9C10[1][A] div_cnt_11_s0/CLK
4.426 0.333 tC2Q RR 4 R9C10[1][A] div_cnt_11_s0/Q
4.430 0.004 tNET RR 1 R9C10[1][A] n66_s2/I3
4.802 0.372 tINS RF 1 R9C10[1][A] n66_s2/F
4.802 0.000 tNET FF 1 R9C10[1][A] div_cnt_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R9C10[1][A] div_cnt_11_s0/CLK
4.093 0.000 tHld 1 R9C10[1][A] div_cnt_11_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%

Path15

Path Summary:

Slack 0.709
Data Arrival Time 4.802
Data Required Time 4.093
From div_cnt_13_s0
To div_cnt_13_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R11C9[0][A] div_cnt_13_s0/CLK
4.426 0.333 tC2Q RR 5 R11C9[0][A] div_cnt_13_s0/Q
4.430 0.004 tNET RR 1 R11C9[0][A] n64_s2/I2
4.802 0.372 tINS RF 1 R11C9[0][A] n64_s2/F
4.802 0.000 tNET FF 1 R11C9[0][A] div_cnt_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R11C9[0][A] div_cnt_13_s0/CLK
4.093 0.000 tHld 1 R11C9[0][A] div_cnt_13_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%

Path16

Path Summary:

Slack 0.709
Data Arrival Time 4.802
Data Required Time 4.093
From div_cnt_15_s0
To div_cnt_15_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R11C9[1][A] div_cnt_15_s0/CLK
4.426 0.333 tC2Q RR 3 R11C9[1][A] div_cnt_15_s0/Q
4.430 0.004 tNET RR 1 R11C9[1][A] n62_s2/I0
4.802 0.372 tINS RF 1 R11C9[1][A] n62_s2/F
4.802 0.000 tNET FF 1 R11C9[1][A] div_cnt_15_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R11C9[1][A] div_cnt_15_s0/CLK
4.093 0.000 tHld 1 R11C9[1][A] div_cnt_15_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%

Path17

Path Summary:

Slack 0.709
Data Arrival Time 4.802
Data Required Time 4.093
From div_cnt_17_s0
To div_cnt_17_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R11C11[1][A] div_cnt_17_s0/CLK
4.426 0.333 tC2Q RR 3 R11C11[1][A] div_cnt_17_s0/Q
4.430 0.004 tNET RR 1 R11C11[1][A] n60_s2/I3
4.802 0.372 tINS RF 1 R11C11[1][A] n60_s2/F
4.802 0.000 tNET FF 1 R11C11[1][A] div_cnt_17_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R11C11[1][A] div_cnt_17_s0/CLK
4.093 0.000 tHld 1 R11C11[1][A] div_cnt_17_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%

Path18

Path Summary:

Slack 0.709
Data Arrival Time 4.802
Data Required Time 4.093
From div_cnt_20_s0
To div_cnt_20_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R12C10[1][A] div_cnt_20_s0/CLK
4.426 0.333 tC2Q RR 4 R12C10[1][A] div_cnt_20_s0/Q
4.430 0.004 tNET RR 1 R12C10[1][A] n57_s2/I3
4.802 0.372 tINS RF 1 R12C10[1][A] n57_s2/F
4.802 0.000 tNET FF 1 R12C10[1][A] div_cnt_20_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R12C10[1][A] div_cnt_20_s0/CLK
4.093 0.000 tHld 1 R12C10[1][A] div_cnt_20_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%

Path19

Path Summary:

Slack 0.709
Data Arrival Time 4.802
Data Required Time 4.093
From div_cnt_22_s0
To div_cnt_22_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R11C10[0][A] div_cnt_22_s0/CLK
4.426 0.333 tC2Q RR 3 R11C10[0][A] div_cnt_22_s0/Q
4.430 0.004 tNET RR 1 R11C10[0][A] n55_s2/I3
4.802 0.372 tINS RF 1 R11C10[0][A] n55_s2/F
4.802 0.000 tNET FF 1 R11C10[0][A] div_cnt_22_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R11C10[0][A] div_cnt_22_s0/CLK
4.093 0.000 tHld 1 R11C10[0][A] div_cnt_22_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%

Path20

Path Summary:

Slack 0.710
Data Arrival Time 4.803
Data Required Time 4.093
From d2_0_s1
To d2_0_s1
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R12C15[1][A] d2_0_s1/CLK
4.426 0.333 tC2Q RR 6 R12C15[1][A] d2_0_s1/Q
4.431 0.005 tNET RR 1 R12C15[1][A] n137_s7/I3
4.803 0.372 tINS RF 1 R12C15[1][A] n137_s7/F
4.803 0.000 tNET FF 1 R12C15[1][A] d2_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R12C15[1][A] d2_0_s1/CLK
4.093 0.000 tHld 1 R12C15[1][A] d2_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%

Path21

Path Summary:

Slack 0.710
Data Arrival Time 4.803
Data Required Time 4.093
From d3_2_s0
To d3_2_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R11C15[0][A] d3_2_s0/CLK
4.426 0.333 tC2Q RR 4 R11C15[0][A] d3_2_s0/Q
4.431 0.005 tNET RR 1 R11C15[0][A] n126_s2/I2
4.803 0.372 tINS RF 1 R11C15[0][A] n126_s2/F
4.803 0.000 tNET FF 1 R11C15[0][A] d3_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R11C15[0][A] d3_2_s0/CLK
4.093 0.000 tHld 1 R11C15[0][A] d3_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%

Path22

Path Summary:

Slack 0.710
Data Arrival Time 4.803
Data Required Time 4.093
From d2_1_s0
To d2_1_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R12C14[0][A] d2_1_s0/CLK
4.426 0.333 tC2Q RR 5 R12C14[0][A] d2_1_s0/Q
4.431 0.005 tNET RR 1 R12C14[0][A] n136_s2/I2
4.803 0.372 tINS RF 1 R12C14[0][A] n136_s2/F
4.803 0.000 tNET FF 1 R12C14[0][A] d2_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R12C14[0][A] d2_1_s0/CLK
4.093 0.000 tHld 1 R12C14[0][A] d2_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%

Path23

Path Summary:

Slack 0.710
Data Arrival Time 4.803
Data Required Time 4.093
From d0_1_s0
To d0_1_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R12C14[1][A] d0_1_s0/CLK
4.426 0.333 tC2Q RR 5 R12C14[1][A] d0_1_s0/Q
4.431 0.005 tNET RR 1 R12C14[1][A] n166_s2/I2
4.803 0.372 tINS RF 1 R12C14[1][A] n166_s2/F
4.803 0.000 tNET FF 1 R12C14[1][A] d0_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R12C14[1][A] d0_1_s0/CLK
4.093 0.000 tHld 1 R12C14[1][A] d0_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%

Path24

Path Summary:

Slack 0.710
Data Arrival Time 4.803
Data Required Time 4.093
From div_cnt_0_s0
To div_cnt_0_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R12C17[0][A] div_cnt_0_s0/CLK
4.426 0.333 tC2Q RR 10 R12C17[0][A] div_cnt_0_s0/Q
4.431 0.005 tNET RR 1 R12C17[0][A] u_drv/n45_s4/I0
4.803 0.372 tINS RF 1 R12C17[0][A] u_drv/n45_s4/F
4.803 0.000 tNET FF 1 R12C17[0][A] div_cnt_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R12C17[0][A] div_cnt_0_s0/CLK
4.093 0.000 tHld 1 R12C17[0][A] div_cnt_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%

Path25

Path Summary:

Slack 0.710
Data Arrival Time 4.803
Data Required Time 4.093
From div_cnt_4_s0
To div_cnt_4_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R11C13[0][A] div_cnt_4_s0/CLK
4.426 0.333 tC2Q RR 4 R11C13[0][A] div_cnt_4_s0/Q
4.431 0.005 tNET RR 1 R11C13[0][A] n73_s2/I1
4.803 0.372 tINS RF 1 R11C13[0][A] n73_s2/F
4.803 0.000 tNET FF 1 R11C13[0][A] div_cnt_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOT13[A] clk_ibuf/I
3.126 3.126 tINS RR 56 IOT13[A] clk_ibuf/O
4.093 0.966 tNET RR 1 R11C13[0][A] div_cnt_4_s0/CLK
4.093 0.000 tHld 1 R11C13[0][A] div_cnt_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay cell: 3.126, 76.388%; route: 0.966, 23.612%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 6.521
Actual Width: 7.771
Required Width: 1.250
Type: High Pulse Width
Clock: clk
Objects: div_cnt_23_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR clk_ibuf/I
4.230 4.230 tINS RR clk_ibuf/O
5.591 1.361 tNET RR div_cnt_23_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF clk_ibuf/I
12.140 2.140 tINS FF clk_ibuf/O
13.362 1.222 tNET FF div_cnt_23_s0/CLK

MPW2

MPW Summary:

Slack: 6.521
Actual Width: 7.771
Required Width: 1.250
Type: High Pulse Width
Clock: clk
Objects: div_cnt_22_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR clk_ibuf/I
4.230 4.230 tINS RR clk_ibuf/O
5.591 1.361 tNET RR div_cnt_22_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF clk_ibuf/I
12.140 2.140 tINS FF clk_ibuf/O
13.362 1.222 tNET FF div_cnt_22_s0/CLK

MPW3

MPW Summary:

Slack: 6.521
Actual Width: 7.771
Required Width: 1.250
Type: High Pulse Width
Clock: clk
Objects: div_cnt_20_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR clk_ibuf/I
4.230 4.230 tINS RR clk_ibuf/O
5.591 1.361 tNET RR div_cnt_20_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF clk_ibuf/I
12.140 2.140 tINS FF clk_ibuf/O
13.362 1.222 tNET FF div_cnt_20_s0/CLK

MPW4

MPW Summary:

Slack: 6.521
Actual Width: 7.771
Required Width: 1.250
Type: High Pulse Width
Clock: clk
Objects: div_cnt_16_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR clk_ibuf/I
4.230 4.230 tINS RR clk_ibuf/O
5.591 1.361 tNET RR div_cnt_16_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF clk_ibuf/I
12.140 2.140 tINS FF clk_ibuf/O
13.362 1.222 tNET FF div_cnt_16_s0/CLK

MPW5

MPW Summary:

Slack: 6.521
Actual Width: 7.771
Required Width: 1.250
Type: High Pulse Width
Clock: clk
Objects: div_cnt_8_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR clk_ibuf/I
4.230 4.230 tINS RR clk_ibuf/O
5.591 1.361 tNET RR div_cnt_8_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF clk_ibuf/I
12.140 2.140 tINS FF clk_ibuf/O
13.362 1.222 tNET FF div_cnt_8_s0/CLK

MPW6

MPW Summary:

Slack: 6.521
Actual Width: 7.771
Required Width: 1.250
Type: High Pulse Width
Clock: clk
Objects: d1_1_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR clk_ibuf/I
4.230 4.230 tINS RR clk_ibuf/O
5.591 1.361 tNET RR d1_1_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF clk_ibuf/I
12.140 2.140 tINS FF clk_ibuf/O
13.362 1.222 tNET FF d1_1_s0/CLK

MPW7

MPW Summary:

Slack: 6.521
Actual Width: 7.771
Required Width: 1.250
Type: High Pulse Width
Clock: clk
Objects: d1_2_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR clk_ibuf/I
4.230 4.230 tINS RR clk_ibuf/O
5.591 1.361 tNET RR d1_2_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF clk_ibuf/I
12.140 2.140 tINS FF clk_ibuf/O
13.362 1.222 tNET FF d1_2_s0/CLK

MPW8

MPW Summary:

Slack: 6.521
Actual Width: 7.771
Required Width: 1.250
Type: High Pulse Width
Clock: clk
Objects: div_cnt_9_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR clk_ibuf/I
4.230 4.230 tINS RR clk_ibuf/O
5.591 1.361 tNET RR div_cnt_9_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF clk_ibuf/I
12.140 2.140 tINS FF clk_ibuf/O
13.362 1.222 tNET FF div_cnt_9_s0/CLK

MPW9

MPW Summary:

Slack: 6.521
Actual Width: 7.771
Required Width: 1.250
Type: High Pulse Width
Clock: clk
Objects: d1_3_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR clk_ibuf/I
4.230 4.230 tINS RR clk_ibuf/O
5.591 1.361 tNET RR d1_3_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF clk_ibuf/I
12.140 2.140 tINS FF clk_ibuf/O
13.362 1.222 tNET FF d1_3_s0/CLK

MPW10

MPW Summary:

Slack: 6.521
Actual Width: 7.771
Required Width: 1.250
Type: High Pulse Width
Clock: clk
Objects: d0_0_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR clk_ibuf/I
4.230 4.230 tINS RR clk_ibuf/O
5.591 1.361 tNET RR d0_0_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF clk_ibuf/I
12.140 2.140 tINS FF clk_ibuf/O
13.362 1.222 tNET FF d0_0_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
56 clk_d 10.737 1.727
15 n26_5 11.729 1.480
14 scan_idx[0] 18.091 1.347
10 div_cnt[0] 10.737 1.648
9 scan_idx[1] 18.018 1.313
9 tick_1hz 15.649 1.311
9 n15_4 13.171 1.316
7 n59_7 10.737 0.989
7 n68_7 10.737 1.329
6 n282_4 14.419 0.843

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R11C14 84.72%
R11C15 76.39%
R12C14 75.00%
R11C11 73.61%
R12C17 69.44%
R12C10 68.06%
R9C16 56.94%
R11C16 56.94%
R9C10 54.17%
R11C9 48.61%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command