Synthesis Messages

Report Title	GowinSynthesis Report
Design File	/home/quang1806/Desktop/hex84k/led7segmentled7segment/src/hex.v
GowinSynthesis Constraints File	---
Tool Version	V1.9.11
Part Number	GW1NSR-LV4CQN48PC6/I5
Device	GW1NSR-4C
Created Time	Fri Aug 22 11:55:41 2025
Legal Announcement	Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module	top_7seg_demo
Synthesis Process	Running parser:     CPU time = 0h 0m 0.061s, Elapsed time = 0h 0m 0.055s, Peak memory usage = 337.613MB Running netlist conversion:     CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization:     Optimizing Phase 0: CPU time = 0h 0m 0.003s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 337.613MB     Optimizing Phase 1: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 337.613MB     Optimizing Phase 2: CPU time = 0h 0m 0.003s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 337.613MB Running inference:     Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 337.613MB     Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 337.613MB     Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 337.613MB     Inferring Phase 3: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0s, Peak memory usage = 337.613MB Running technical mapping:     Tech-Mapping Phase 0: CPU time = 0h 0m 0.007s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 337.613MB     Tech-Mapping Phase 1: CPU time = 0h 0m 0.002s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 337.613MB     Tech-Mapping Phase 2: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 337.613MB     Tech-Mapping Phase 3: CPU time = 0h 0m 0.501s, Elapsed time = 0h 0m 0.494s, Peak memory usage = 337.613MB     Tech-Mapping Phase 4: CPU time = 0h 0m 0.041s, Elapsed time = 0h 0m 0.039s, Peak memory usage = 337.613MB Generate output files:     CPU time = 0h 0m 0.036s, Elapsed time = 0h 0m 0.034s, Peak memory usage = 337.613MB
Total Time and Memory Usage	CPU time = 0h 0m 0.657s, Elapsed time = 0h 0m 0.634s, Peak memory usage = 337.613MB

Resource

Resource Usage Summary

Resource	Usage
I/O Port	14
I/O Buf	14
IBUF	2
OBUF	12
Register	56
DFFC	41
DFFCE	15
LUT	109
LUT2	15
LUT3	39
LUT4	55
INV	4
INV	4

Resource Utilization Summary

Resource	Usage	Utilization
Logic	113(113 LUT, 0 ALU) / 4608	3%
Register	56 / 3573	2%
--Register as Latch	0 / 3573	0%
--Register as FF	56 / 3573	2%
BSRAM	0 / 10	0%

Timing

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Object
1	clk	Base	20.000	50.000	0.000	10.000			clk_ibuf/I

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk	50.000(MHz)	100.127(MHz)	5	TOP

Detail Timing Paths Information

Path 1

Path Summary:

Slack	10.013
Data Arrival Time	10.313
Data Required Time	20.326
From	div_cnt_20_s0
To	div_cnt_23_s0
Launch Clk	clk[R]
Latch Clk	clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.000	0.000	tINS	RR	56	clk_ibuf/O
0.726	0.726	tNET	RR	1	div_cnt_20_s0/CLK
1.184	0.458	tC2Q	RF	4	div_cnt_20_s0/Q
2.144	0.960	tNET	FF	1	n55_s4/I1
3.243	1.099	tINS	FF	2	n55_s4/F
4.203	0.960	tNET	FF	1	n53_s4/I0
5.235	1.032	tINS	FF	1	n53_s4/F
6.195	0.960	tNET	FF	1	n53_s3/I1
7.294	1.099	tINS	FF	2	n53_s3/F
8.254	0.960	tNET	FF	1	n54_s2/I1
9.353	1.099	tINS	FF	1	n54_s2/F
10.313	0.960	tNET	FF	1	div_cnt_23_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	0.000				clk
20.000	0.000	tCL	RR	1	clk_ibuf/I
20.000	0.000	tINS	RR	56	clk_ibuf/O
20.726	0.726	tNET	RR	1	div_cnt_23_s0/CLK
20.326	-0.400	tSu		1	div_cnt_23_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay:	cell: 4.329, 45.153%; route: 4.800, 50.066%; tC2Q: 0.458, 4.781%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 2

Path Summary:

Slack	10.013
Data Arrival Time	10.313
Data Required Time	20.326
From	div_cnt_5_s0
To	div_cnt_19_s0
Launch Clk	clk[R]
Latch Clk	clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.000	0.000	tINS	RR	56	clk_ibuf/O
0.726	0.726	tNET	RR	1	div_cnt_5_s0/CLK
1.184	0.458	tC2Q	RF	3	div_cnt_5_s0/Q
2.144	0.960	tNET	FF	1	n68_s4/I1
3.243	1.099	tINS	FF	4	n68_s4/F
4.203	0.960	tNET	FF	1	n59_s3/I1
5.302	1.099	tINS	FF	7	n59_s3/F
6.262	0.960	tNET	FF	1	n55_s3/I0
7.294	1.032	tINS	FF	4	n55_s3/F
8.254	0.960	tNET	FF	1	n58_s2/I1
9.353	1.099	tINS	FF	1	n58_s2/F
10.313	0.960	tNET	FF	1	div_cnt_19_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	0.000				clk
20.000	0.000	tCL	RR	1	clk_ibuf/I
20.000	0.000	tINS	RR	56	clk_ibuf/O
20.726	0.726	tNET	RR	1	div_cnt_19_s0/CLK
20.326	-0.400	tSu		1	div_cnt_19_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay:	cell: 4.329, 45.153%; route: 4.800, 50.066%; tC2Q: 0.458, 4.781%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 3

Path Summary:

Slack	10.013
Data Arrival Time	10.313
Data Required Time	20.326
From	div_cnt_5_s0
To	div_cnt_16_s0
Launch Clk	clk[R]
Latch Clk	clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.000	0.000	tINS	RR	56	clk_ibuf/O
0.726	0.726	tNET	RR	1	div_cnt_5_s0/CLK
1.184	0.458	tC2Q	RF	3	div_cnt_5_s0/Q
2.144	0.960	tNET	FF	1	n68_s4/I1
3.243	1.099	tINS	FF	4	n68_s4/F
4.203	0.960	tNET	FF	1	n59_s3/I1
5.302	1.099	tINS	FF	7	n59_s3/F
6.262	0.960	tNET	FF	1	n60_s4/I0
7.294	1.032	tINS	FF	2	n60_s4/F
8.254	0.960	tNET	FF	1	n61_s2/I1
9.353	1.099	tINS	FF	1	n61_s2/F
10.313	0.960	tNET	FF	1	div_cnt_16_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	0.000				clk
20.000	0.000	tCL	RR	1	clk_ibuf/I
20.000	0.000	tINS	RR	56	clk_ibuf/O
20.726	0.726	tNET	RR	1	div_cnt_16_s0/CLK
20.326	-0.400	tSu		1	div_cnt_16_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay:	cell: 4.329, 45.153%; route: 4.800, 50.066%; tC2Q: 0.458, 4.781%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 4

Path Summary:

Slack	10.013
Data Arrival Time	10.313
Data Required Time	20.326
From	div_cnt_5_s0
To	div_cnt_15_s0
Launch Clk	clk[R]
Latch Clk	clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.000	0.000	tINS	RR	56	clk_ibuf/O
0.726	0.726	tNET	RR	1	div_cnt_5_s0/CLK
1.184	0.458	tC2Q	RF	3	div_cnt_5_s0/Q
2.144	0.960	tNET	FF	1	n68_s4/I1
3.243	1.099	tINS	FF	4	n68_s4/F
4.203	0.960	tNET	FF	1	n59_s3/I1
5.302	1.099	tINS	FF	7	n59_s3/F
6.262	0.960	tNET	FF	1	n62_s3/I0
7.294	1.032	tINS	FF	1	n62_s3/F
8.254	0.960	tNET	FF	1	n62_s2/I1
9.353	1.099	tINS	FF	1	n62_s2/F
10.313	0.960	tNET	FF	1	div_cnt_15_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	0.000				clk
20.000	0.000	tCL	RR	1	clk_ibuf/I
20.000	0.000	tINS	RR	56	clk_ibuf/O
20.726	0.726	tNET	RR	1	div_cnt_15_s0/CLK
20.326	-0.400	tSu		1	div_cnt_15_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay:	cell: 4.329, 45.153%; route: 4.800, 50.066%; tC2Q: 0.458, 4.781%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 5

Path Summary:

Slack	10.013
Data Arrival Time	10.313
Data Required Time	20.326
From	div_cnt_5_s0
To	div_cnt_12_s0
Launch Clk	clk[R]
Latch Clk	clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.000	0.000	tINS	RR	56	clk_ibuf/O
0.726	0.726	tNET	RR	1	div_cnt_5_s0/CLK
1.184	0.458	tC2Q	RF	3	div_cnt_5_s0/Q
2.144	0.960	tNET	FF	1	n68_s4/I1
3.243	1.099	tINS	FF	4	n68_s4/F
4.203	0.960	tNET	FF	1	n66_s3/I1
5.302	1.099	tINS	FF	3	n66_s3/F
6.262	0.960	tNET	FF	1	n65_s3/I0
7.294	1.032	tINS	FF	1	n65_s3/F
8.254	0.960	tNET	FF	1	n65_s2/I1
9.353	1.099	tINS	FF	1	n65_s2/F
10.313	0.960	tNET	FF	1	div_cnt_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	0.000				clk
20.000	0.000	tCL	RR	1	clk_ibuf/I
20.000	0.000	tINS	RR	56	clk_ibuf/O
20.726	0.726	tNET	RR	1	div_cnt_12_s0/CLK
20.326	-0.400	tSu		1	div_cnt_12_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay:	cell: 4.329, 45.153%; route: 4.800, 50.066%; tC2Q: 0.458, 4.781%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%