Timing Messages

Report Title	Timing Analysis Report
Design File	/home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/hdmi_720p/impl/gwsynthesis/hdmi.vg
Physical Constraints File	/home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/hdmi_720p/src/hdmi.cst
Timing Constraint File	/home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/hdmi_720p/src/hdmi.sdc
Tool Version	V1.9.11
Part Number	GW1NSR-LV4CQN48PC6/I5
Device	GW1NSR-4C
Created Time	Tue Apr 8 14:17:08 2025
Legal Announcement	Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 1.14V 85C C6/I5
Hold Delay Model	Fast 1.26V 0C C6/I5
Numbers of Paths Analyzed	3018
Numbers of Endpoints Analyzed	1491
Numbers of Falling Endpoints	3
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	clk_osc	Base	37.037	27.000	0.000	18.518			clk
2	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk	Generated	7.936	126.000	0.000	3.968	clk_ibuf/I	clk_osc	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
3	Gowin_PLLVR_inst/pllvr_inst/CLKOUTP.default_gen_clk	Generated	7.936	126.000	0.000	3.968	clk_ibuf/I	clk_osc	Gowin_PLLVR_inst/pllvr_inst/CLKOUTP
4	Gowin_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk	Generated	15.873	63.000	0.000	7.936	clk_ibuf/I	clk_osc	Gowin_PLLVR_inst/pllvr_inst/CLKOUTD
5	Gowin_PLLVR_inst/pllvr_inst/CLKOUTD3.default_gen_clk	Generated	23.809	42.000	0.000	11.905	clk_ibuf/I	clk_osc	Gowin_PLLVR_inst/pllvr_inst/CLKOUTD3
6	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk	Generated	39.682	25.200	0.000	19.841	Gowin_PLLVR_inst/pllvr_inst/CLKOUT	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk	u_div_5/clkdiv_inst/CLKOUT

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk	25.200(MHz)	37.505(MHz)	17	TOP

No timing paths to get frequency of clk_osc!

No timing paths to get frequency of Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk!

No timing paths to get frequency of Gowin_PLLVR_inst/pllvr_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of Gowin_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk!

No timing paths to get frequency of Gowin_PLLVR_inst/pllvr_inst/CLKOUTD3.default_gen_clk!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk_osc	Setup	0.000	0
clk_osc	Hold	0.000	0
Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk	Setup	0.000	0
Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk	Hold	0.000	0
Gowin_PLLVR_inst/pllvr_inst/CLKOUTP.default_gen_clk	Setup	0.000	0
Gowin_PLLVR_inst/pllvr_inst/CLKOUTP.default_gen_clk	Hold	0.000	0
Gowin_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk	Setup	0.000	0
Gowin_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk	Hold	0.000	0
Gowin_PLLVR_inst/pllvr_inst/CLKOUTD3.default_gen_clk	Setup	0.000	0
Gowin_PLLVR_inst/pllvr_inst/CLKOUTD3.default_gen_clk	Hold	0.000	0
u_div_5/clkdiv_inst/CLKOUT.default_gen_clk	Setup	0.000	0
u_div_5/clkdiv_inst/CLKOUT.default_gen_clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	13.020	svo_hdmi_inst/svo_enc/out_axis_tdata_3_s0/Q	svo_hdmi_inst/svo_tmds_2/cnt_4_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	39.682	0.000	26.263
2	14.193	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0/Q	svo_hdmi_inst/svo_tmds_0/cnt_4_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	39.682	0.000	25.090
3	14.646	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0/Q	svo_hdmi_inst/svo_tmds_0/cnt_6_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	39.682	0.000	24.637
4	14.706	svo_hdmi_inst/svo_enc/out_axis_tdata_3_s0/Q	svo_hdmi_inst/svo_tmds_2/cnt_5_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	39.682	0.000	24.577
5	14.706	svo_hdmi_inst/svo_enc/out_axis_tdata_11_s0/Q	svo_hdmi_inst/svo_tmds_1/cnt_7_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	39.682	0.000	24.576
6	14.881	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0/Q	svo_hdmi_inst/svo_tmds_0/cnt_7_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	39.682	0.000	24.402
7	15.160	svo_hdmi_inst/svo_enc/out_axis_tdata_11_s0/Q	svo_hdmi_inst/svo_tmds_1/cnt_6_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	39.682	0.000	24.122
8	15.187	svo_hdmi_inst/svo_enc/out_axis_tdata_3_s0/Q	svo_hdmi_inst/svo_tmds_2/cnt_7_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	39.682	0.000	24.095
9	15.217	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0/Q	svo_hdmi_inst/svo_tmds_0/cnt_5_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	39.682	0.000	24.065
10	15.246	svo_hdmi_inst/svo_enc/out_axis_tdata_11_s0/Q	svo_hdmi_inst/svo_tmds_1/cnt_5_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	39.682	0.000	24.037
11	15.502	svo_hdmi_inst/svo_enc/out_axis_tdata_3_s0/Q	svo_hdmi_inst/svo_tmds_2/cnt_6_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	39.682	0.000	23.781
12	15.652	svo_hdmi_inst/svo_enc/out_axis_tdata_11_s0/Q	svo_hdmi_inst/svo_tmds_1/cnt_4_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	39.682	0.000	23.630
13	16.000	svo_hdmi_inst/svo_enc/out_axis_tdata_3_s0/Q	svo_hdmi_inst/svo_tmds_2/cnt_3_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	39.682	0.000	23.282
14	16.258	svo_hdmi_inst/svo_enc/out_axis_tdata_3_s0/Q	svo_hdmi_inst/svo_tmds_2/cnt_2_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	39.682	0.000	23.025
15	16.465	svo_hdmi_inst/svo_enc/out_axis_tdata_11_s0/Q	svo_hdmi_inst/svo_tmds_1/cnt_3_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	39.682	0.000	22.818
16	16.555	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0/Q	svo_hdmi_inst/svo_tmds_0/cnt_1_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	39.682	0.000	22.727
17	16.582	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0/Q	svo_hdmi_inst/svo_tmds_0/cnt_3_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	39.682	0.000	22.701
18	16.677	svo_hdmi_inst/svo_enc/out_axis_tdata_11_s0/Q	svo_hdmi_inst/svo_tmds_1/cnt_2_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	39.682	0.000	22.606
19	16.970	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0/Q	svo_hdmi_inst/svo_tmds_0/q_out_4_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	39.682	0.000	22.312
20	16.999	svo_hdmi_inst/svo_enc/out_axis_tdata_3_s0/Q	svo_hdmi_inst/svo_tmds_2/cnt_1_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	39.682	0.000	22.283
21	17.147	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0/Q	svo_hdmi_inst/svo_tmds_0/cnt_2_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	39.682	0.000	22.135
22	17.199	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0/Q	svo_hdmi_inst/svo_tmds_0/q_out_1_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	39.682	0.000	22.083
23	17.236	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0/Q	svo_hdmi_inst/svo_tmds_0/q_out_3_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	39.682	0.000	22.047
24	17.464	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0/Q	svo_hdmi_inst/svo_tmds_0/q_out_9_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	39.682	0.000	21.818
25	17.543	svo_hdmi_inst/svo_enc/out_axis_tdata_3_s0/Q	svo_hdmi_inst/svo_tmds_2/q_out_4_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	39.682	0.000	21.740

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.417	svo_hdmi_inst/svo_tcard/xoff_3_s0/Q	svo_hdmi_inst/svo_tcard/vdma_tdata_0_s135/AD[3]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.571
2	0.688	svo_hdmi_inst/svo_tcard/xoff_1_s0/Q	svo_hdmi_inst/svo_tcard/vdma_tdata_0_s135/AD[1]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.842
3	0.708	svo_hdmi_inst/svo_enc/vcursor_13_s0/Q	svo_hdmi_inst/svo_enc/vcursor_13_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.708
4	0.708	svo_hdmi_inst/svo_enc/hcursor_3_s0/Q	svo_hdmi_inst/svo_enc/hcursor_3_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.708
5	0.708	svo_hdmi_inst/svo_enc/hcursor_11_s0/Q	svo_hdmi_inst/svo_enc/hcursor_11_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.708
6	0.708	svo_hdmi_inst/svo_enc/hcursor_13_s0/Q	svo_hdmi_inst/svo_enc/hcursor_13_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.708
7	0.708	svo_hdmi_inst/svo_tcard/hcursor_13_s0/Q	svo_hdmi_inst/svo_tcard/hcursor_13_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.708
8	0.708	svo_hdmi_inst/svo_tcard/b_3_s0/Q	svo_hdmi_inst/svo_tcard/b_3_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.708
9	0.708	svo_hdmi_inst/svo_tcard/x_8_s0/Q	svo_hdmi_inst/svo_tcard/x_8_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.708
10	0.708	svo_hdmi_inst/svo_tcard/vcursor_9_s0/Q	svo_hdmi_inst/svo_tcard/vcursor_9_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.708
11	0.708	svo_hdmi_inst/svo_tcard/vcursor_11_s0/Q	svo_hdmi_inst/svo_tcard/vcursor_11_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.708
12	0.708	svo_hdmi_inst/svo_tcard/hcursor_6_s0/Q	svo_hdmi_inst/svo_tcard/hcursor_6_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.708
13	0.709	svo_hdmi_inst/svo_enc/wait_for_fifos_1_s1/Q	svo_hdmi_inst/svo_enc/wait_for_fifos_1_s1/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.709
14	0.709	svo_hdmi_inst/svo_enc/out_fifo_rdaddr_0_s0/Q	svo_hdmi_inst/svo_enc/out_fifo_rdaddr_0_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.709
15	0.709	svo_hdmi_inst/svo_enc/out_fifo_rdaddr_1_s0/Q	svo_hdmi_inst/svo_enc/out_fifo_rdaddr_1_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.709
16	0.709	svo_hdmi_inst/svo_enc/vcursor_7_s0/Q	svo_hdmi_inst/svo_enc/vcursor_7_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.709
17	0.709	svo_hdmi_inst/svo_enc/vcursor_10_s0/Q	svo_hdmi_inst/svo_enc/vcursor_10_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.709
18	0.709	svo_hdmi_inst/svo_enc/vcursor_11_s0/Q	svo_hdmi_inst/svo_enc/vcursor_11_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.709
19	0.709	svo_hdmi_inst/svo_enc/hcursor_7_s0/Q	svo_hdmi_inst/svo_enc/hcursor_7_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.709
20	0.709	svo_hdmi_inst/svo_tcard/hcursor_0_s1/Q	svo_hdmi_inst/svo_tcard/hcursor_0_s1/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.709
21	0.709	svo_hdmi_inst/svo_tcard/rng_26_s0/Q	svo_hdmi_inst/svo_tcard/rng_26_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.709
22	0.709	svo_hdmi_inst/svo_tcard/yoff_0_s0/Q	svo_hdmi_inst/svo_tcard/yoff_0_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.709
23	0.709	svo_hdmi_inst/svo_tcard/yoff_3_s0/Q	svo_hdmi_inst/svo_tcard/yoff_3_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.709
24	0.709	svo_hdmi_inst/svo_tcard/x_3_s0/Q	svo_hdmi_inst/svo_tcard/x_3_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.709
25	0.709	svo_hdmi_inst/svo_tcard/x_5_s0/Q	svo_hdmi_inst/svo_tcard/x_5_s0/D	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.709

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.384	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q	svo_hdmi_inst/tmds_serdes[2]/RESET	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[F]	3.968	-1.823	5.332
2	0.384	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q	svo_hdmi_inst/tmds_serdes[1]/RESET	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[F]	3.968	-1.823	5.332
3	0.384	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q	svo_hdmi_inst/tmds_serdes[0]/RESET	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[F]	3.968	-1.823	5.332
4	4.345	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q	svo_hdmi_inst/tmds_serdes[0]/RESET	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	7.936	-1.816	5.332
5	4.345	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q	svo_hdmi_inst/tmds_serdes[1]/RESET	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	7.936	-1.816	5.332
6	4.345	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q	svo_hdmi_inst/tmds_serdes[2]/RESET	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	7.936	-1.816	5.332
7	34.305	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q	svo_hdmi_inst/tmds_serdes[0]/RESET	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	39.682	0.000	5.332
8	34.305	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q	svo_hdmi_inst/tmds_serdes[1]/RESET	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	39.682	0.000	5.332
9	34.305	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q	svo_hdmi_inst/tmds_serdes[2]/RESET	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	39.682	0.000	5.332

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	1.500	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q	svo_hdmi_inst/tmds_serdes[0]/RESET	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	-1.845	3.387
2	1.500	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q	svo_hdmi_inst/tmds_serdes[1]/RESET	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	-1.845	3.387
3	1.500	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q	svo_hdmi_inst/tmds_serdes[2]/RESET	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	-1.845	3.387
4	3.375	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q	svo_hdmi_inst/tmds_serdes[2]/RESET	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	3.387
5	3.375	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q	svo_hdmi_inst/tmds_serdes[1]/RESET	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	3.387
6	3.375	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q	svo_hdmi_inst/tmds_serdes[0]/RESET	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	0.000	0.000	3.387
7	5.463	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q	svo_hdmi_inst/tmds_serdes[2]/RESET	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[F]	-3.968	-1.850	3.387
8	5.463	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q	svo_hdmi_inst/tmds_serdes[1]/RESET	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[F]	-3.968	-1.850	3.387
9	5.463	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q	svo_hdmi_inst/tmds_serdes[0]/RESET	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[F]	-3.968	-1.850	3.387

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	18.517	19.767	1.250	Low Pulse Width	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk	u_Reset_Sync/reset_cnt_2_s0
2	18.517	19.767	1.250	Low Pulse Width	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk	u_Reset_Sync/reset_cnt_0_s0
3	18.517	19.767	1.250	Low Pulse Width	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk	svo_hdmi_inst/resetn_clk_pixel_q_1_s0
4	18.517	19.767	1.250	Low Pulse Width	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk	svo_hdmi_inst/svo_tcard/hcursor_5_s0
5	18.517	19.767	1.250	Low Pulse Width	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk	svo_hdmi_inst/svo_tcard/vcursor_0_s0
6	18.517	19.767	1.250	Low Pulse Width	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk	svo_hdmi_inst/svo_tcard/rng_30_s0
7	18.517	19.767	1.250	Low Pulse Width	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk	svo_hdmi_inst/svo_tcard/vdma_tdata_0_s232
8	18.517	19.767	1.250	Low Pulse Width	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk	svo_hdmi_inst/svo_enc/pixel_fifo_pixel_fifo_RAMREG_1_G[2]_s1
9	18.517	19.767	1.250	Low Pulse Width	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk	svo_hdmi_inst/svo_enc/out_fifo_out_fifo_RAMREG_3_G[22]_s0
10	18.517	19.767	1.250	Low Pulse Width	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk	svo_hdmi_inst/svo_enc/out_fifo_out_fifo_RAMREG_3_G[21]_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	13.020
Data Arrival Time	26.835
Data Required Time	39.855
From	svo_hdmi_inst/svo_enc/out_axis_tdata_3_s0
To	svo_hdmi_inst/svo_tmds_2/cnt_4_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R8C16[1][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_3_s0/CLK
1.030	0.458	tC2Q	RF	4	R8C16[1][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_3_s0/Q
2.992	1.962	tNET	FF	1	R8C28[0][A]	svo_hdmi_inst/svo_tmds_2/n146_s15/I2
3.814	0.822	tINS	FF	12	R8C28[0][A]	svo_hdmi_inst/svo_tmds_2/n146_s15/F
3.853	0.038	tNET	FF	1	R8C28[3][A]	svo_hdmi_inst/svo_tmds_2/n406_s2/I1
4.479	0.626	tINS	FF	1	R8C28[3][A]	svo_hdmi_inst/svo_tmds_2/n406_s2/F
4.484	0.005	tNET	FF	1	R8C28[2][A]	svo_hdmi_inst/svo_tmds_2/n88_s4/I3
5.306	0.822	tINS	FF	3	R8C28[2][A]	svo_hdmi_inst/svo_tmds_2/n88_s4/F
6.142	0.836	tNET	FF	1	R8C29[3][B]	svo_hdmi_inst/svo_tmds_2/n88_s2/I2
7.174	1.032	tINS	FF	8	R8C29[3][B]	svo_hdmi_inst/svo_tmds_2/n88_s2/F
8.018	0.843	tNET	FF	1	R8C30[3][A]	svo_hdmi_inst/svo_tmds_2/n407_s3/I0
9.117	1.099	tINS	FF	3	R8C30[3][A]	svo_hdmi_inst/svo_tmds_2/n407_s3/F
9.943	0.826	tNET	FF	1	R9C30[2][A]	svo_hdmi_inst/svo_tmds_2/n175_s16/I3
10.969	1.026	tINS	FR	3	R9C30[2][A]	svo_hdmi_inst/svo_tmds_2/n175_s16/F
11.394	0.425	tNET	RR	1	R9C31[2][B]	svo_hdmi_inst/svo_tmds_2/n175_s14/I1
12.020	0.626	tINS	RF	4	R9C31[2][B]	svo_hdmi_inst/svo_tmds_2/n175_s14/F
13.331	1.311	tNET	FF	1	R6C33[3][A]	svo_hdmi_inst/svo_tmds_2/n176_s13/I1
14.153	0.822	tINS	FF	4	R6C33[3][A]	svo_hdmi_inst/svo_tmds_2/n176_s13/F
15.458	1.305	tNET	FF	2	R6C30[0][A]	svo_hdmi_inst/svo_tmds_2/n245_s/I1
16.008	0.550	tINS	FR	1	R6C30[0][A]	svo_hdmi_inst/svo_tmds_2/n245_s/COUT
16.008	0.000	tNET	RR	2	R6C30[0][B]	svo_hdmi_inst/svo_tmds_2/n326_s/CIN
16.571	0.563	tINS	RF	1	R6C30[0][B]	svo_hdmi_inst/svo_tmds_2/n326_s/SUM
18.345	1.773	tNET	FF	2	R7C30[0][B]	svo_hdmi_inst/svo_tmds_2/n326_s0/I0
19.303	0.958	tINS	FF	1	R7C30[0][B]	svo_hdmi_inst/svo_tmds_2/n326_s0/COUT
19.303	0.000	tNET	FF	2	R7C30[1][A]	svo_hdmi_inst/svo_tmds_2/n325_s0/CIN
19.831	0.528	tINS	FR	4	R7C30[1][A]	svo_hdmi_inst/svo_tmds_2/n325_s0/SUM
20.254	0.423	tNET	RR	1	R7C29[0][A]	svo_hdmi_inst/svo_tmds_2/n377_s5/I1
21.353	1.099	tINS	RF	4	R7C29[0][A]	svo_hdmi_inst/svo_tmds_2/n377_s5/F
22.173	0.821	tNET	FF	1	R7C32[1][A]	svo_hdmi_inst/svo_tmds_2/n380_s3/I1
23.272	1.099	tINS	FF	1	R7C32[1][A]	svo_hdmi_inst/svo_tmds_2/n380_s3/F
24.093	0.821	tNET	FF	1	R7C33[3][B]	svo_hdmi_inst/svo_tmds_2/n380_s1/I0
25.192	1.099	tINS	FF	1	R7C33[3][B]	svo_hdmi_inst/svo_tmds_2/n380_s1/F
26.013	0.821	tNET	FF	1	R7C32[0][B]	svo_hdmi_inst/svo_tmds_2/n380_s0/I0
26.835	0.822	tINS	FF	1	R7C32[0][B]	svo_hdmi_inst/svo_tmds_2/n380_s0/F
26.835	0.000	tNET	FF	1	R7C32[0][B]	svo_hdmi_inst/svo_tmds_2/cnt_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
39.682	39.682					active clock edge time
39.682	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
40.255	0.242	tNET	RR	1	R7C32[0][B]	svo_hdmi_inst/svo_tmds_2/cnt_4_s0/CLK
39.855	-0.400	tSu		1	R7C32[0][B]	svo_hdmi_inst/svo_tmds_2/cnt_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	39.682
Logic Level	17
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 13.593, 51.757%; route: 12.212, 46.498%; tC2Q: 0.458, 1.745%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path2

Path Summary:

Slack	14.193
Data Arrival Time	25.662
Data Required Time	39.855
From	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0
To	svo_hdmi_inst/svo_tmds_0/cnt_4_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R9C18[0][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0/CLK
1.030	0.458	tC2Q	RF	8	R9C18[0][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0/Q
3.326	2.296	tNET	FF	1	R15C24[0][B]	svo_hdmi_inst/svo_tmds_0/n404_s4/I3
3.952	0.626	tINS	FF	9	R15C24[0][B]	svo_hdmi_inst/svo_tmds_0/n404_s4/F
4.799	0.847	tNET	FF	1	R16C23[2][B]	svo_hdmi_inst/svo_tmds_0/n406_s2/I1
5.825	1.026	tINS	FR	3	R16C23[2][B]	svo_hdmi_inst/svo_tmds_0/n406_s2/F
6.248	0.423	tNET	RR	1	R16C24[1][B]	svo_hdmi_inst/svo_tmds_0/n88_s7/I3
7.347	1.099	tINS	RF	2	R16C24[1][B]	svo_hdmi_inst/svo_tmds_0/n88_s7/F
7.358	0.011	tNET	FF	1	R16C24[3][A]	svo_hdmi_inst/svo_tmds_0/n88_s3/I1
8.457	1.099	tINS	FF	1	R16C24[3][A]	svo_hdmi_inst/svo_tmds_0/n88_s3/F
8.462	0.005	tNET	FF	1	R16C24[3][B]	svo_hdmi_inst/svo_tmds_0/n88_s0/I3
9.264	0.802	tINS	FR	30	R16C24[3][B]	svo_hdmi_inst/svo_tmds_0/n88_s0/F
9.703	0.438	tNET	RR	1	R16C23[2][A]	svo_hdmi_inst/svo_tmds_0/n146_s13/I2
10.525	0.822	tINS	RF	3	R16C23[2][A]	svo_hdmi_inst/svo_tmds_0/n146_s13/F
11.338	0.813	tNET	FF	1	R15C22[3][B]	svo_hdmi_inst/svo_tmds_0/n145_s12/I2
12.370	1.032	tINS	FF	3	R15C22[3][B]	svo_hdmi_inst/svo_tmds_0/n145_s12/F
14.174	1.804	tNET	FF	1	R16C19[0][B]	svo_hdmi_inst/svo_tmds_0/n145_s11/I1
15.206	1.032	tINS	FF	3	R16C19[0][B]	svo_hdmi_inst/svo_tmds_0/n145_s11/F
16.512	1.306	tNET	FF	2	R15C16[1][A]	svo_hdmi_inst/svo_tmds_0/n288_s/I1
17.213	0.701	tINS	FR	1	R15C16[1][A]	svo_hdmi_inst/svo_tmds_0/n288_s/SUM
17.999	0.786	tNET	RR	2	R15C14[1][A]	svo_hdmi_inst/svo_tmds_0/n288_s0/I0
18.957	0.958	tINS	RF	1	R15C14[1][A]	svo_hdmi_inst/svo_tmds_0/n288_s0/COUT
18.957	0.000	tNET	FF	2	R15C14[1][B]	svo_hdmi_inst/svo_tmds_0/n287_s0/CIN
19.485	0.528	tINS	FR	3	R15C14[1][B]	svo_hdmi_inst/svo_tmds_0/n287_s0/SUM
19.906	0.421	tNET	RR	1	R15C13[3][B]	svo_hdmi_inst/svo_tmds_0/n377_s7/I3
20.532	0.626	tINS	RF	4	R15C13[3][B]	svo_hdmi_inst/svo_tmds_0/n377_s7/F
21.347	0.815	tNET	FF	1	R15C14[3][A]	svo_hdmi_inst/svo_tmds_0/n380_s4/I1
22.446	1.099	tINS	FF	1	R15C14[3][A]	svo_hdmi_inst/svo_tmds_0/n380_s4/F
23.735	1.289	tNET	FF	1	R15C15[3][A]	svo_hdmi_inst/svo_tmds_0/n380_s1/I1
24.834	1.099	tINS	FF	1	R15C15[3][A]	svo_hdmi_inst/svo_tmds_0/n380_s1/F
24.840	0.005	tNET	FF	1	R15C15[1][B]	svo_hdmi_inst/svo_tmds_0/n380_s0/I0
25.662	0.822	tINS	FF	1	R15C15[1][B]	svo_hdmi_inst/svo_tmds_0/n380_s0/F
25.662	0.000	tNET	FF	1	R15C15[1][B]	svo_hdmi_inst/svo_tmds_0/cnt_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
39.682	39.682					active clock edge time
39.682	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
40.255	0.242	tNET	RR	1	R15C15[1][B]	svo_hdmi_inst/svo_tmds_0/cnt_4_s0/CLK
39.855	-0.400	tSu		1	R15C15[1][B]	svo_hdmi_inst/svo_tmds_0/cnt_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	39.682
Logic Level	16
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 13.371, 53.293%; route: 11.260, 44.880%; tC2Q: 0.458, 1.827%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path3

Path Summary:

Slack	14.646
Data Arrival Time	25.209
Data Required Time	39.855
From	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0
To	svo_hdmi_inst/svo_tmds_0/cnt_6_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R9C18[0][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0/CLK
1.030	0.458	tC2Q	RF	8	R9C18[0][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0/Q
3.326	2.296	tNET	FF	1	R15C24[0][B]	svo_hdmi_inst/svo_tmds_0/n404_s4/I3
3.952	0.626	tINS	FF	9	R15C24[0][B]	svo_hdmi_inst/svo_tmds_0/n404_s4/F
4.799	0.847	tNET	FF	1	R16C23[2][B]	svo_hdmi_inst/svo_tmds_0/n406_s2/I1
5.825	1.026	tINS	FR	3	R16C23[2][B]	svo_hdmi_inst/svo_tmds_0/n406_s2/F
6.248	0.423	tNET	RR	1	R16C24[1][B]	svo_hdmi_inst/svo_tmds_0/n88_s7/I3
7.347	1.099	tINS	RF	2	R16C24[1][B]	svo_hdmi_inst/svo_tmds_0/n88_s7/F
7.358	0.011	tNET	FF	1	R16C24[3][A]	svo_hdmi_inst/svo_tmds_0/n88_s3/I1
8.457	1.099	tINS	FF	1	R16C24[3][A]	svo_hdmi_inst/svo_tmds_0/n88_s3/F
8.462	0.005	tNET	FF	1	R16C24[3][B]	svo_hdmi_inst/svo_tmds_0/n88_s0/I3
9.264	0.802	tINS	FR	30	R16C24[3][B]	svo_hdmi_inst/svo_tmds_0/n88_s0/F
9.703	0.438	tNET	RR	1	R16C23[2][A]	svo_hdmi_inst/svo_tmds_0/n146_s13/I2
10.525	0.822	tINS	RF	3	R16C23[2][A]	svo_hdmi_inst/svo_tmds_0/n146_s13/F
11.338	0.813	tNET	FF	1	R15C22[3][B]	svo_hdmi_inst/svo_tmds_0/n145_s12/I2
12.370	1.032	tINS	FF	3	R15C22[3][B]	svo_hdmi_inst/svo_tmds_0/n145_s12/F
14.174	1.804	tNET	FF	1	R16C19[0][B]	svo_hdmi_inst/svo_tmds_0/n145_s11/I1
15.206	1.032	tINS	FF	3	R16C19[0][B]	svo_hdmi_inst/svo_tmds_0/n145_s11/F
16.512	1.306	tNET	FF	2	R15C16[1][A]	svo_hdmi_inst/svo_tmds_0/n288_s/I1
17.213	0.701	tINS	FR	1	R15C16[1][A]	svo_hdmi_inst/svo_tmds_0/n288_s/SUM
17.999	0.786	tNET	RR	2	R15C14[1][A]	svo_hdmi_inst/svo_tmds_0/n288_s0/I0
18.957	0.958	tINS	RF	1	R15C14[1][A]	svo_hdmi_inst/svo_tmds_0/n288_s0/COUT
18.957	0.000	tNET	FF	2	R15C14[1][B]	svo_hdmi_inst/svo_tmds_0/n287_s0/CIN
19.485	0.528	tINS	FR	3	R15C14[1][B]	svo_hdmi_inst/svo_tmds_0/n287_s0/SUM
19.906	0.421	tNET	RR	1	R15C13[3][B]	svo_hdmi_inst/svo_tmds_0/n377_s7/I3
20.532	0.626	tINS	RF	4	R15C13[3][B]	svo_hdmi_inst/svo_tmds_0/n377_s7/F
22.008	1.476	tNET	FF	1	R15C18[1][B]	svo_hdmi_inst/svo_tmds_0/n378_s4/I2
22.830	0.822	tINS	FF	1	R15C18[1][B]	svo_hdmi_inst/svo_tmds_0/n378_s4/F
23.166	0.336	tNET	FF	1	R15C18[3][A]	svo_hdmi_inst/svo_tmds_0/n378_s1/I1
23.968	0.802	tINS	FR	1	R15C18[3][A]	svo_hdmi_inst/svo_tmds_0/n378_s1/F
24.387	0.419	tNET	RR	1	R16C18[0][A]	svo_hdmi_inst/svo_tmds_0/n378_s0/I0
25.209	0.822	tINS	RF	1	R16C18[0][A]	svo_hdmi_inst/svo_tmds_0/n378_s0/F
25.209	0.000	tNET	FF	1	R16C18[0][A]	svo_hdmi_inst/svo_tmds_0/cnt_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
39.682	39.682					active clock edge time
39.682	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
40.255	0.242	tNET	RR	1	R16C18[0][A]	svo_hdmi_inst/svo_tmds_0/cnt_6_s0/CLK
39.855	-0.400	tSu		1	R16C18[0][A]	svo_hdmi_inst/svo_tmds_0/cnt_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	39.682
Logic Level	16
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 12.797, 51.943%; route: 11.382, 46.197%; tC2Q: 0.458, 1.860%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path4

Path Summary:

Slack	14.706
Data Arrival Time	25.149
Data Required Time	39.855
From	svo_hdmi_inst/svo_enc/out_axis_tdata_3_s0
To	svo_hdmi_inst/svo_tmds_2/cnt_5_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R8C16[1][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_3_s0/CLK
1.030	0.458	tC2Q	RF	4	R8C16[1][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_3_s0/Q
2.992	1.962	tNET	FF	1	R8C28[0][A]	svo_hdmi_inst/svo_tmds_2/n146_s15/I2
3.814	0.822	tINS	FF	12	R8C28[0][A]	svo_hdmi_inst/svo_tmds_2/n146_s15/F
3.853	0.038	tNET	FF	1	R8C28[3][A]	svo_hdmi_inst/svo_tmds_2/n406_s2/I1
4.479	0.626	tINS	FF	1	R8C28[3][A]	svo_hdmi_inst/svo_tmds_2/n406_s2/F
4.484	0.005	tNET	FF	1	R8C28[2][A]	svo_hdmi_inst/svo_tmds_2/n88_s4/I3
5.306	0.822	tINS	FF	3	R8C28[2][A]	svo_hdmi_inst/svo_tmds_2/n88_s4/F
6.142	0.836	tNET	FF	1	R8C29[3][B]	svo_hdmi_inst/svo_tmds_2/n88_s2/I2
7.174	1.032	tINS	FF	8	R8C29[3][B]	svo_hdmi_inst/svo_tmds_2/n88_s2/F
8.018	0.843	tNET	FF	1	R8C30[3][A]	svo_hdmi_inst/svo_tmds_2/n407_s3/I0
9.117	1.099	tINS	FF	3	R8C30[3][A]	svo_hdmi_inst/svo_tmds_2/n407_s3/F
9.943	0.826	tNET	FF	1	R9C30[2][A]	svo_hdmi_inst/svo_tmds_2/n175_s16/I3
10.969	1.026	tINS	FR	3	R9C30[2][A]	svo_hdmi_inst/svo_tmds_2/n175_s16/F
11.394	0.425	tNET	RR	1	R9C31[2][B]	svo_hdmi_inst/svo_tmds_2/n175_s14/I1
12.020	0.626	tINS	RF	4	R9C31[2][B]	svo_hdmi_inst/svo_tmds_2/n175_s14/F
13.331	1.311	tNET	FF	1	R6C33[3][A]	svo_hdmi_inst/svo_tmds_2/n176_s13/I1
14.153	0.822	tINS	FF	4	R6C33[3][A]	svo_hdmi_inst/svo_tmds_2/n176_s13/F
15.458	1.305	tNET	FF	2	R6C30[0][A]	svo_hdmi_inst/svo_tmds_2/n245_s/I1
16.008	0.550	tINS	FR	1	R6C30[0][A]	svo_hdmi_inst/svo_tmds_2/n245_s/COUT
16.008	0.000	tNET	RR	2	R6C30[0][B]	svo_hdmi_inst/svo_tmds_2/n326_s/CIN
16.571	0.563	tINS	RF	1	R6C30[0][B]	svo_hdmi_inst/svo_tmds_2/n326_s/SUM
18.345	1.773	tNET	FF	2	R7C30[0][B]	svo_hdmi_inst/svo_tmds_2/n326_s0/I0
19.303	0.958	tINS	FF	1	R7C30[0][B]	svo_hdmi_inst/svo_tmds_2/n326_s0/COUT
19.303	0.000	tNET	FF	2	R7C30[1][A]	svo_hdmi_inst/svo_tmds_2/n325_s0/CIN
19.831	0.528	tINS	FR	4	R7C30[1][A]	svo_hdmi_inst/svo_tmds_2/n325_s0/SUM
20.254	0.423	tNET	RR	1	R7C29[0][A]	svo_hdmi_inst/svo_tmds_2/n377_s5/I1
21.353	1.099	tINS	RF	4	R7C29[0][A]	svo_hdmi_inst/svo_tmds_2/n377_s5/F
22.658	1.305	tNET	FF	1	R6C32[3][B]	svo_hdmi_inst/svo_tmds_2/n379_s3/I1
23.480	0.822	tINS	FF	1	R6C32[3][B]	svo_hdmi_inst/svo_tmds_2/n379_s3/F
23.485	0.005	tNET	FF	1	R6C32[0][A]	svo_hdmi_inst/svo_tmds_2/n379_s1/I0
24.517	1.032	tINS	FF	1	R6C32[0][A]	svo_hdmi_inst/svo_tmds_2/n379_s1/F
24.523	0.005	tNET	FF	1	R6C32[1][B]	svo_hdmi_inst/svo_tmds_2/n379_s0/I0
25.149	0.626	tINS	FF	1	R6C32[1][B]	svo_hdmi_inst/svo_tmds_2/n379_s0/F
25.149	0.000	tNET	FF	1	R6C32[1][B]	svo_hdmi_inst/svo_tmds_2/cnt_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
39.682	39.682					active clock edge time
39.682	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
40.255	0.242	tNET	RR	1	R6C32[1][B]	svo_hdmi_inst/svo_tmds_2/cnt_5_s0/CLK
39.855	-0.400	tSu		1	R6C32[1][B]	svo_hdmi_inst/svo_tmds_2/cnt_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	39.682
Logic Level	17
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 13.053, 53.111%; route: 11.065, 45.024%; tC2Q: 0.458, 1.865%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path5

Path Summary:

Slack	14.706
Data Arrival Time	25.148
Data Required Time	39.855
From	svo_hdmi_inst/svo_enc/out_axis_tdata_11_s0
To	svo_hdmi_inst/svo_tmds_1/cnt_7_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R9C15[2][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_11_s0/CLK
1.030	0.458	tC2Q	RF	6	R9C15[2][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_11_s0/Q
4.103	3.073	tNET	FF	1	R16C34[3][A]	svo_hdmi_inst/svo_tmds_1/n407_s3/I2
4.729	0.626	tINS	FF	8	R16C34[3][A]	svo_hdmi_inst/svo_tmds_1/n407_s3/F
5.561	0.832	tNET	FF	1	R15C33[1][A]	svo_hdmi_inst/svo_tmds_1/n404_s3/I3
6.383	0.822	tINS	FF	5	R15C33[1][A]	svo_hdmi_inst/svo_tmds_1/n404_s3/F
6.405	0.022	tNET	FF	1	R15C33[3][A]	svo_hdmi_inst/svo_tmds_1/n88_s7/I3
7.031	0.626	tINS	FF	2	R15C33[3][A]	svo_hdmi_inst/svo_tmds_1/n88_s7/F
7.042	0.011	tNET	FF	1	R15C33[1][B]	svo_hdmi_inst/svo_tmds_1/n88_s3/I1
7.864	0.822	tINS	FF	1	R15C33[1][B]	svo_hdmi_inst/svo_tmds_1/n88_s3/F
7.869	0.005	tNET	FF	1	R15C33[2][A]	svo_hdmi_inst/svo_tmds_1/n88_s0/I3
8.968	1.099	tINS	FF	30	R15C33[2][A]	svo_hdmi_inst/svo_tmds_1/n88_s0/F
9.817	0.848	tNET	FF	1	R14C33[3][B]	svo_hdmi_inst/svo_tmds_1/n146_s13/I2
10.916	1.099	tINS	FF	3	R14C33[3][B]	svo_hdmi_inst/svo_tmds_1/n146_s13/F
11.729	0.813	tNET	FF	1	R13C32[3][B]	svo_hdmi_inst/svo_tmds_1/n146_s10/I2
12.761	1.032	tINS	FF	4	R13C32[3][B]	svo_hdmi_inst/svo_tmds_1/n146_s10/F
13.582	0.821	tNET	FF	1	R14C31[1][B]	svo_hdmi_inst/svo_tmds_1/n147_s18/I0
14.384	0.802	tINS	FR	4	R14C31[1][B]	svo_hdmi_inst/svo_tmds_1/n147_s18/F
14.811	0.427	tNET	RR	2	R14C32[0][A]	svo_hdmi_inst/svo_tmds_1/n223_s/I1
15.512	0.701	tINS	RR	1	R14C32[0][A]	svo_hdmi_inst/svo_tmds_1/n223_s/SUM
17.000	1.488	tNET	RR	2	R15C32[0][A]	svo_hdmi_inst/svo_tmds_1/n223_s0/I0
17.958	0.958	tINS	RF	1	R15C32[0][A]	svo_hdmi_inst/svo_tmds_1/n223_s0/COUT
17.958	0.000	tNET	FF	2	R15C32[0][B]	svo_hdmi_inst/svo_tmds_1/n289_s0/CIN
18.015	0.057	tINS	FF	1	R15C32[0][B]	svo_hdmi_inst/svo_tmds_1/n289_s0/COUT
18.015	0.000	tNET	FF	2	R15C32[1][A]	svo_hdmi_inst/svo_tmds_1/n288_s0/CIN
18.072	0.057	tINS	FF	1	R15C32[1][A]	svo_hdmi_inst/svo_tmds_1/n288_s0/COUT
18.072	0.000	tNET	FF	2	R15C32[1][B]	svo_hdmi_inst/svo_tmds_1/n287_s0/CIN
18.635	0.563	tINS	FF	3	R15C32[1][B]	svo_hdmi_inst/svo_tmds_1/n287_s0/SUM
20.265	1.629	tNET	FF	1	R13C31[3][B]	svo_hdmi_inst/svo_tmds_1/n377_s7/I3
21.297	1.032	tINS	FF	4	R13C31[3][B]	svo_hdmi_inst/svo_tmds_1/n377_s7/F
22.117	0.821	tNET	FF	1	R12C30[1][B]	svo_hdmi_inst/svo_tmds_1/n377_s4/I0
23.216	1.099	tINS	FF	1	R12C30[1][B]	svo_hdmi_inst/svo_tmds_1/n377_s4/F
23.222	0.005	tNET	FF	1	R12C30[3][A]	svo_hdmi_inst/svo_tmds_1/n377_s1/I1
24.321	1.099	tINS	FF	1	R12C30[3][A]	svo_hdmi_inst/svo_tmds_1/n377_s1/F
24.326	0.005	tNET	FF	1	R12C30[0][B]	svo_hdmi_inst/svo_tmds_1/n377_s0/I0
25.148	0.822	tINS	FF	1	R12C30[0][B]	svo_hdmi_inst/svo_tmds_1/n377_s0/F
25.148	0.000	tNET	FF	1	R12C30[0][B]	svo_hdmi_inst/svo_tmds_1/cnt_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
39.682	39.682					active clock edge time
39.682	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
40.255	0.242	tNET	RR	1	R12C30[0][B]	svo_hdmi_inst/svo_tmds_1/cnt_7_s0/CLK
39.855	-0.400	tSu		1	R12C30[0][B]	svo_hdmi_inst/svo_tmds_1/cnt_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	39.682
Logic Level	17
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 13.316, 54.182%; route: 10.802, 43.953%; tC2Q: 0.458, 1.865%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path6

Path Summary:

Slack	14.881
Data Arrival Time	24.974
Data Required Time	39.855
From	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0
To	svo_hdmi_inst/svo_tmds_0/cnt_7_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R9C18[0][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0/CLK
1.030	0.458	tC2Q	RF	8	R9C18[0][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0/Q
3.326	2.296	tNET	FF	1	R15C24[0][B]	svo_hdmi_inst/svo_tmds_0/n404_s4/I3
3.952	0.626	tINS	FF	9	R15C24[0][B]	svo_hdmi_inst/svo_tmds_0/n404_s4/F
4.799	0.847	tNET	FF	1	R16C23[2][B]	svo_hdmi_inst/svo_tmds_0/n406_s2/I1
5.825	1.026	tINS	FR	3	R16C23[2][B]	svo_hdmi_inst/svo_tmds_0/n406_s2/F
6.248	0.423	tNET	RR	1	R16C24[1][B]	svo_hdmi_inst/svo_tmds_0/n88_s7/I3
7.347	1.099	tINS	RF	2	R16C24[1][B]	svo_hdmi_inst/svo_tmds_0/n88_s7/F
7.358	0.011	tNET	FF	1	R16C24[3][A]	svo_hdmi_inst/svo_tmds_0/n88_s3/I1
8.457	1.099	tINS	FF	1	R16C24[3][A]	svo_hdmi_inst/svo_tmds_0/n88_s3/F
8.462	0.005	tNET	FF	1	R16C24[3][B]	svo_hdmi_inst/svo_tmds_0/n88_s0/I3
9.264	0.802	tINS	FR	30	R16C24[3][B]	svo_hdmi_inst/svo_tmds_0/n88_s0/F
9.703	0.438	tNET	RR	1	R16C23[2][A]	svo_hdmi_inst/svo_tmds_0/n146_s13/I2
10.525	0.822	tINS	RF	3	R16C23[2][A]	svo_hdmi_inst/svo_tmds_0/n146_s13/F
11.338	0.813	tNET	FF	1	R15C22[3][B]	svo_hdmi_inst/svo_tmds_0/n145_s12/I2
12.370	1.032	tINS	FF	3	R15C22[3][B]	svo_hdmi_inst/svo_tmds_0/n145_s12/F
14.174	1.804	tNET	FF	1	R16C19[0][B]	svo_hdmi_inst/svo_tmds_0/n145_s11/I1
15.206	1.032	tINS	FF	3	R16C19[0][B]	svo_hdmi_inst/svo_tmds_0/n145_s11/F
16.512	1.306	tNET	FF	2	R15C16[1][A]	svo_hdmi_inst/svo_tmds_0/n288_s/I1
17.062	0.550	tINS	FR	1	R15C16[1][A]	svo_hdmi_inst/svo_tmds_0/n288_s/COUT
17.062	0.000	tNET	RR	2	R15C16[1][B]	svo_hdmi_inst/svo_tmds_0/n287_s/CIN
17.119	0.057	tINS	RF	1	R15C16[1][B]	svo_hdmi_inst/svo_tmds_0/n287_s/COUT
17.119	0.000	tNET	FF	2	R15C16[2][A]	svo_hdmi_inst/svo_tmds_0/n286_s/CIN
17.682	0.563	tINS	FF	1	R15C16[2][A]	svo_hdmi_inst/svo_tmds_0/n286_s/SUM
18.503	0.821	tNET	FF	2	R15C14[2][A]	svo_hdmi_inst/svo_tmds_0/n286_s0/I0
19.461	0.958	tINS	FF	1	R15C14[2][A]	svo_hdmi_inst/svo_tmds_0/n286_s0/COUT
19.461	0.000	tNET	FF	2	R15C14[2][B]	svo_hdmi_inst/svo_tmds_0/n285_s0/CIN
19.518	0.057	tINS	FF	1	R15C14[2][B]	svo_hdmi_inst/svo_tmds_0/n285_s0/COUT
19.518	0.000	tNET	FF	2	R15C15[0][A]	svo_hdmi_inst/svo_tmds_0/n284_s0/CIN
20.081	0.563	tINS	FF	3	R15C15[0][A]	svo_hdmi_inst/svo_tmds_0/n284_s0/SUM
20.894	0.813	tNET	FF	1	R15C18[3][B]	svo_hdmi_inst/svo_tmds_0/n377_s8/I0
21.993	1.099	tINS	FF	1	R15C18[3][B]	svo_hdmi_inst/svo_tmds_0/n377_s8/F
21.998	0.005	tNET	FF	1	R15C18[0][A]	svo_hdmi_inst/svo_tmds_0/n377_s4/I1
23.030	1.032	tINS	FF	1	R15C18[0][A]	svo_hdmi_inst/svo_tmds_0/n377_s4/F
23.521	0.490	tNET	FF	1	R15C20[3][A]	svo_hdmi_inst/svo_tmds_0/n377_s1/I1
24.147	0.626	tINS	FF	1	R15C20[3][A]	svo_hdmi_inst/svo_tmds_0/n377_s1/F
24.152	0.005	tNET	FF	1	R15C20[1][A]	svo_hdmi_inst/svo_tmds_0/n377_s0/I0
24.974	0.822	tINS	FF	1	R15C20[1][A]	svo_hdmi_inst/svo_tmds_0/n377_s0/F
24.974	0.000	tNET	FF	1	R15C20[1][A]	svo_hdmi_inst/svo_tmds_0/cnt_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
39.682	39.682					active clock edge time
39.682	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
40.255	0.242	tNET	RR	1	R15C20[1][A]	svo_hdmi_inst/svo_tmds_0/cnt_7_s0/CLK
39.855	-0.400	tSu		1	R15C20[1][A]	svo_hdmi_inst/svo_tmds_0/cnt_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	39.682
Logic Level	17
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 13.865, 56.819%; route: 10.079, 41.302%; tC2Q: 0.458, 1.878%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path7

Path Summary:

Slack	15.160
Data Arrival Time	24.694
Data Required Time	39.855
From	svo_hdmi_inst/svo_enc/out_axis_tdata_11_s0
To	svo_hdmi_inst/svo_tmds_1/cnt_6_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R9C15[2][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_11_s0/CLK
1.030	0.458	tC2Q	RF	6	R9C15[2][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_11_s0/Q
4.103	3.073	tNET	FF	1	R16C34[3][A]	svo_hdmi_inst/svo_tmds_1/n407_s3/I2
4.729	0.626	tINS	FF	8	R16C34[3][A]	svo_hdmi_inst/svo_tmds_1/n407_s3/F
5.561	0.832	tNET	FF	1	R15C33[1][A]	svo_hdmi_inst/svo_tmds_1/n404_s3/I3
6.383	0.822	tINS	FF	5	R15C33[1][A]	svo_hdmi_inst/svo_tmds_1/n404_s3/F
6.405	0.022	tNET	FF	1	R15C33[3][A]	svo_hdmi_inst/svo_tmds_1/n88_s7/I3
7.031	0.626	tINS	FF	2	R15C33[3][A]	svo_hdmi_inst/svo_tmds_1/n88_s7/F
7.042	0.011	tNET	FF	1	R15C33[1][B]	svo_hdmi_inst/svo_tmds_1/n88_s3/I1
7.864	0.822	tINS	FF	1	R15C33[1][B]	svo_hdmi_inst/svo_tmds_1/n88_s3/F
7.869	0.005	tNET	FF	1	R15C33[2][A]	svo_hdmi_inst/svo_tmds_1/n88_s0/I3
8.968	1.099	tINS	FF	30	R15C33[2][A]	svo_hdmi_inst/svo_tmds_1/n88_s0/F
9.817	0.848	tNET	FF	1	R14C33[3][B]	svo_hdmi_inst/svo_tmds_1/n146_s13/I2
10.916	1.099	tINS	FF	3	R14C33[3][B]	svo_hdmi_inst/svo_tmds_1/n146_s13/F
11.729	0.813	tNET	FF	1	R13C32[3][B]	svo_hdmi_inst/svo_tmds_1/n146_s10/I2
12.761	1.032	tINS	FF	4	R13C32[3][B]	svo_hdmi_inst/svo_tmds_1/n146_s10/F
13.582	0.821	tNET	FF	1	R14C31[1][B]	svo_hdmi_inst/svo_tmds_1/n147_s18/I0
14.384	0.802	tINS	FR	4	R14C31[1][B]	svo_hdmi_inst/svo_tmds_1/n147_s18/F
14.811	0.427	tNET	RR	2	R14C32[0][A]	svo_hdmi_inst/svo_tmds_1/n223_s/I1
15.361	0.550	tINS	RR	1	R14C32[0][A]	svo_hdmi_inst/svo_tmds_1/n223_s/COUT
15.361	0.000	tNET	RR	2	R14C32[0][B]	svo_hdmi_inst/svo_tmds_1/n289_s/CIN
15.418	0.057	tINS	RF	1	R14C32[0][B]	svo_hdmi_inst/svo_tmds_1/n289_s/COUT
15.418	0.000	tNET	FF	2	R14C32[1][A]	svo_hdmi_inst/svo_tmds_1/n288_s/CIN
15.475	0.057	tINS	FF	1	R14C32[1][A]	svo_hdmi_inst/svo_tmds_1/n288_s/COUT
15.475	0.000	tNET	FF	2	R14C32[1][B]	svo_hdmi_inst/svo_tmds_1/n287_s/CIN
15.532	0.057	tINS	FF	1	R14C32[1][B]	svo_hdmi_inst/svo_tmds_1/n287_s/COUT
15.532	0.000	tNET	FF	2	R14C32[2][A]	svo_hdmi_inst/svo_tmds_1/n286_s/CIN
16.095	0.563	tINS	FF	1	R14C32[2][A]	svo_hdmi_inst/svo_tmds_1/n286_s/SUM
18.050	1.955	tNET	FF	2	R15C32[2][A]	svo_hdmi_inst/svo_tmds_1/n286_s0/I0
19.008	0.958	tINS	FF	1	R15C32[2][A]	svo_hdmi_inst/svo_tmds_1/n286_s0/COUT
19.008	0.000	tNET	FF	2	R15C32[2][B]	svo_hdmi_inst/svo_tmds_1/n285_s0/CIN
19.065	0.057	tINS	FF	1	R15C32[2][B]	svo_hdmi_inst/svo_tmds_1/n285_s0/COUT
19.065	0.000	tNET	FF	2	R15C33[0][A]	svo_hdmi_inst/svo_tmds_1/n284_s0/CIN
19.628	0.563	tINS	FF	3	R15C33[0][A]	svo_hdmi_inst/svo_tmds_1/n284_s0/SUM
21.588	1.960	tNET	FF	1	R13C30[2][B]	svo_hdmi_inst/svo_tmds_1/n378_s4/I3
22.620	1.032	tINS	FF	1	R13C30[2][B]	svo_hdmi_inst/svo_tmds_1/n378_s4/F
22.625	0.005	tNET	FF	1	R13C30[3][B]	svo_hdmi_inst/svo_tmds_1/n378_s1/I1
23.657	1.032	tINS	FF	1	R13C30[3][B]	svo_hdmi_inst/svo_tmds_1/n378_s1/F
23.662	0.005	tNET	FF	1	R13C30[0][B]	svo_hdmi_inst/svo_tmds_1/n378_s0/I0
24.694	1.032	tINS	FF	1	R13C30[0][B]	svo_hdmi_inst/svo_tmds_1/n378_s0/F
24.694	0.000	tNET	FF	1	R13C30[0][B]	svo_hdmi_inst/svo_tmds_1/cnt_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
39.682	39.682					active clock edge time
39.682	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
40.255	0.242	tNET	RR	1	R13C30[0][B]	svo_hdmi_inst/svo_tmds_1/cnt_6_s0/CLK
39.855	-0.400	tSu		1	R13C30[0][B]	svo_hdmi_inst/svo_tmds_1/cnt_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	39.682
Logic Level	16
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 12.886, 53.419%; route: 10.778, 44.681%; tC2Q: 0.458, 1.900%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path8

Path Summary:

Slack	15.187
Data Arrival Time	24.667
Data Required Time	39.855
From	svo_hdmi_inst/svo_enc/out_axis_tdata_3_s0
To	svo_hdmi_inst/svo_tmds_2/cnt_7_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R8C16[1][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_3_s0/CLK
1.030	0.458	tC2Q	RF	4	R8C16[1][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_3_s0/Q
2.992	1.962	tNET	FF	1	R8C28[0][A]	svo_hdmi_inst/svo_tmds_2/n146_s15/I2
3.814	0.822	tINS	FF	12	R8C28[0][A]	svo_hdmi_inst/svo_tmds_2/n146_s15/F
3.853	0.038	tNET	FF	1	R8C28[3][A]	svo_hdmi_inst/svo_tmds_2/n406_s2/I1
4.479	0.626	tINS	FF	1	R8C28[3][A]	svo_hdmi_inst/svo_tmds_2/n406_s2/F
4.484	0.005	tNET	FF	1	R8C28[2][A]	svo_hdmi_inst/svo_tmds_2/n88_s4/I3
5.306	0.822	tINS	FF	3	R8C28[2][A]	svo_hdmi_inst/svo_tmds_2/n88_s4/F
6.142	0.836	tNET	FF	1	R8C29[3][B]	svo_hdmi_inst/svo_tmds_2/n88_s2/I2
7.174	1.032	tINS	FF	8	R8C29[3][B]	svo_hdmi_inst/svo_tmds_2/n88_s2/F
8.012	0.837	tNET	FF	1	R9C29[2][B]	svo_hdmi_inst/svo_tmds_2/n88_s0/I1
8.638	0.626	tINS	FF	22	R9C29[2][B]	svo_hdmi_inst/svo_tmds_2/n88_s0/F
9.642	1.005	tNET	FF	1	R8C31[3][B]	svo_hdmi_inst/svo_tmds_2/n146_s13/I0
10.741	1.099	tINS	FF	3	R8C31[3][B]	svo_hdmi_inst/svo_tmds_2/n146_s13/F
10.758	0.016	tNET	FF	1	R8C31[2][A]	svo_hdmi_inst/svo_tmds_2/n145_s12/I2
11.790	1.032	tINS	FF	2	R8C31[2][A]	svo_hdmi_inst/svo_tmds_2/n145_s12/F
12.615	0.825	tNET	FF	1	R6C31[3][A]	svo_hdmi_inst/svo_tmds_2/n145_s11/I1
13.647	1.032	tINS	FF	3	R6C31[3][A]	svo_hdmi_inst/svo_tmds_2/n145_s11/F
14.947	1.300	tNET	FF	2	R6C33[1][A]	svo_hdmi_inst/svo_tmds_2/n288_s/I1
15.497	0.550	tINS	FR	1	R6C33[1][A]	svo_hdmi_inst/svo_tmds_2/n288_s/COUT
15.497	0.000	tNET	RR	2	R6C33[1][B]	svo_hdmi_inst/svo_tmds_2/n287_s/CIN
15.554	0.057	tINS	RF	1	R6C33[1][B]	svo_hdmi_inst/svo_tmds_2/n287_s/COUT
15.554	0.000	tNET	FF	2	R6C33[2][A]	svo_hdmi_inst/svo_tmds_2/n286_s/CIN
16.117	0.563	tINS	FF	1	R6C33[2][A]	svo_hdmi_inst/svo_tmds_2/n286_s/SUM
16.921	0.804	tNET	FF	2	R7C33[2][A]	svo_hdmi_inst/svo_tmds_2/n286_s0/I0
17.879	0.958	tINS	FF	1	R7C33[2][A]	svo_hdmi_inst/svo_tmds_2/n286_s0/COUT
17.879	0.000	tNET	FF	2	R7C33[2][B]	svo_hdmi_inst/svo_tmds_2/n285_s0/CIN
17.936	0.057	tINS	FF	1	R7C33[2][B]	svo_hdmi_inst/svo_tmds_2/n285_s0/COUT
17.936	0.000	tNET	FF	2	R7C34[0][A]	svo_hdmi_inst/svo_tmds_2/n284_s0/CIN
18.499	0.563	tINS	FF	3	R7C34[0][A]	svo_hdmi_inst/svo_tmds_2/n284_s0/SUM
19.799	1.300	tNET	FF	1	R6C31[2][B]	svo_hdmi_inst/svo_tmds_2/n377_s8/I0
20.831	1.032	tINS	FF	1	R6C31[2][B]	svo_hdmi_inst/svo_tmds_2/n377_s8/F
20.837	0.005	tNET	FF	1	R6C31[1][A]	svo_hdmi_inst/svo_tmds_2/n377_s4/I1
21.869	1.032	tINS	FF	1	R6C31[1][A]	svo_hdmi_inst/svo_tmds_2/n377_s4/F
23.004	1.135	tNET	FF	1	R6C29[1][A]	svo_hdmi_inst/svo_tmds_2/n377_s1/I1
24.036	1.032	tINS	FF	1	R6C29[1][A]	svo_hdmi_inst/svo_tmds_2/n377_s1/F
24.041	0.005	tNET	FF	1	R6C29[0][A]	svo_hdmi_inst/svo_tmds_2/n377_s0/I0
24.667	0.626	tINS	FF	1	R6C29[0][A]	svo_hdmi_inst/svo_tmds_2/n377_s0/F
24.667	0.000	tNET	FF	1	R6C29[0][A]	svo_hdmi_inst/svo_tmds_2/cnt_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
39.682	39.682					active clock edge time
39.682	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
40.255	0.242	tNET	RR	1	R6C29[0][A]	svo_hdmi_inst/svo_tmds_2/cnt_7_s0/CLK
39.855	-0.400	tSu		1	R6C29[0][A]	svo_hdmi_inst/svo_tmds_2/cnt_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	39.682
Logic Level	17
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 13.561, 56.281%; route: 10.076, 41.817%; tC2Q: 0.458, 1.902%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path9

Path Summary:

Slack	15.217
Data Arrival Time	24.637
Data Required Time	39.855
From	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0
To	svo_hdmi_inst/svo_tmds_0/cnt_5_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R9C18[0][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0/CLK
1.030	0.458	tC2Q	RF	8	R9C18[0][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0/Q
3.326	2.296	tNET	FF	1	R15C24[0][B]	svo_hdmi_inst/svo_tmds_0/n404_s4/I3
3.952	0.626	tINS	FF	9	R15C24[0][B]	svo_hdmi_inst/svo_tmds_0/n404_s4/F
4.799	0.847	tNET	FF	1	R16C23[2][B]	svo_hdmi_inst/svo_tmds_0/n406_s2/I1
5.825	1.026	tINS	FR	3	R16C23[2][B]	svo_hdmi_inst/svo_tmds_0/n406_s2/F
6.248	0.423	tNET	RR	1	R16C24[1][B]	svo_hdmi_inst/svo_tmds_0/n88_s7/I3
7.347	1.099	tINS	RF	2	R16C24[1][B]	svo_hdmi_inst/svo_tmds_0/n88_s7/F
7.358	0.011	tNET	FF	1	R16C24[3][A]	svo_hdmi_inst/svo_tmds_0/n88_s3/I1
8.457	1.099	tINS	FF	1	R16C24[3][A]	svo_hdmi_inst/svo_tmds_0/n88_s3/F
8.462	0.005	tNET	FF	1	R16C24[3][B]	svo_hdmi_inst/svo_tmds_0/n88_s0/I3
9.264	0.802	tINS	FR	30	R16C24[3][B]	svo_hdmi_inst/svo_tmds_0/n88_s0/F
9.703	0.438	tNET	RR	1	R16C23[2][A]	svo_hdmi_inst/svo_tmds_0/n146_s13/I2
10.525	0.822	tINS	RF	3	R16C23[2][A]	svo_hdmi_inst/svo_tmds_0/n146_s13/F
11.338	0.813	tNET	FF	1	R15C22[3][B]	svo_hdmi_inst/svo_tmds_0/n145_s12/I2
12.370	1.032	tINS	FF	3	R15C22[3][B]	svo_hdmi_inst/svo_tmds_0/n145_s12/F
14.174	1.804	tNET	FF	1	R16C19[0][B]	svo_hdmi_inst/svo_tmds_0/n145_s11/I1
15.206	1.032	tINS	FF	3	R16C19[0][B]	svo_hdmi_inst/svo_tmds_0/n145_s11/F
16.512	1.306	tNET	FF	2	R15C16[1][A]	svo_hdmi_inst/svo_tmds_0/n288_s/I1
17.213	0.701	tINS	FR	1	R15C16[1][A]	svo_hdmi_inst/svo_tmds_0/n288_s/SUM
17.999	0.786	tNET	RR	2	R15C14[1][A]	svo_hdmi_inst/svo_tmds_0/n288_s0/I0
18.957	0.958	tINS	RF	1	R15C14[1][A]	svo_hdmi_inst/svo_tmds_0/n288_s0/COUT
18.957	0.000	tNET	FF	2	R15C14[1][B]	svo_hdmi_inst/svo_tmds_0/n287_s0/CIN
19.485	0.528	tINS	FR	3	R15C14[1][B]	svo_hdmi_inst/svo_tmds_0/n287_s0/SUM
19.906	0.421	tNET	RR	1	R15C13[3][B]	svo_hdmi_inst/svo_tmds_0/n377_s7/I3
20.532	0.626	tINS	RF	4	R15C13[3][B]	svo_hdmi_inst/svo_tmds_0/n377_s7/F
21.347	0.815	tNET	FF	1	R15C16[3][B]	svo_hdmi_inst/svo_tmds_0/n379_s4/I1
21.973	0.626	tINS	FF	1	R15C16[3][B]	svo_hdmi_inst/svo_tmds_0/n379_s4/F
21.979	0.005	tNET	FF	1	R15C16[3][A]	svo_hdmi_inst/svo_tmds_0/n379_s1/I1
23.011	1.032	tINS	FF	1	R15C16[3][A]	svo_hdmi_inst/svo_tmds_0/n379_s1/F
23.815	0.804	tNET	FF	1	R16C15[0][B]	svo_hdmi_inst/svo_tmds_0/n379_s0/I0
24.637	0.822	tINS	FF	1	R16C15[0][B]	svo_hdmi_inst/svo_tmds_0/n379_s0/F
24.637	0.000	tNET	FF	1	R16C15[0][B]	svo_hdmi_inst/svo_tmds_0/cnt_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
39.682	39.682					active clock edge time
39.682	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
40.255	0.242	tNET	RR	1	R16C15[0][B]	svo_hdmi_inst/svo_tmds_0/cnt_5_s0/CLK
39.855	-0.400	tSu		1	R16C15[0][B]	svo_hdmi_inst/svo_tmds_0/cnt_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	39.682
Logic Level	16
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 12.831, 53.318%; route: 10.776, 44.777%; tC2Q: 0.458, 1.905%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path10

Path Summary:

Slack	15.246
Data Arrival Time	24.609
Data Required Time	39.855
From	svo_hdmi_inst/svo_enc/out_axis_tdata_11_s0
To	svo_hdmi_inst/svo_tmds_1/cnt_5_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R9C15[2][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_11_s0/CLK
1.030	0.458	tC2Q	RF	6	R9C15[2][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_11_s0/Q
4.103	3.073	tNET	FF	1	R16C34[3][A]	svo_hdmi_inst/svo_tmds_1/n407_s3/I2
4.729	0.626	tINS	FF	8	R16C34[3][A]	svo_hdmi_inst/svo_tmds_1/n407_s3/F
5.561	0.832	tNET	FF	1	R15C33[1][A]	svo_hdmi_inst/svo_tmds_1/n404_s3/I3
6.383	0.822	tINS	FF	5	R15C33[1][A]	svo_hdmi_inst/svo_tmds_1/n404_s3/F
6.405	0.022	tNET	FF	1	R15C33[3][A]	svo_hdmi_inst/svo_tmds_1/n88_s7/I3
7.031	0.626	tINS	FF	2	R15C33[3][A]	svo_hdmi_inst/svo_tmds_1/n88_s7/F
7.042	0.011	tNET	FF	1	R15C33[1][B]	svo_hdmi_inst/svo_tmds_1/n88_s3/I1
7.864	0.822	tINS	FF	1	R15C33[1][B]	svo_hdmi_inst/svo_tmds_1/n88_s3/F
7.869	0.005	tNET	FF	1	R15C33[2][A]	svo_hdmi_inst/svo_tmds_1/n88_s0/I3
8.968	1.099	tINS	FF	30	R15C33[2][A]	svo_hdmi_inst/svo_tmds_1/n88_s0/F
9.817	0.848	tNET	FF	1	R14C33[3][B]	svo_hdmi_inst/svo_tmds_1/n146_s13/I2
10.916	1.099	tINS	FF	3	R14C33[3][B]	svo_hdmi_inst/svo_tmds_1/n146_s13/F
11.729	0.813	tNET	FF	1	R13C32[3][B]	svo_hdmi_inst/svo_tmds_1/n146_s10/I2
12.761	1.032	tINS	FF	4	R13C32[3][B]	svo_hdmi_inst/svo_tmds_1/n146_s10/F
13.582	0.821	tNET	FF	1	R14C31[1][B]	svo_hdmi_inst/svo_tmds_1/n147_s18/I0
14.384	0.802	tINS	FR	4	R14C31[1][B]	svo_hdmi_inst/svo_tmds_1/n147_s18/F
14.811	0.427	tNET	RR	2	R14C32[0][A]	svo_hdmi_inst/svo_tmds_1/n223_s/I1
15.512	0.701	tINS	RR	1	R14C32[0][A]	svo_hdmi_inst/svo_tmds_1/n223_s/SUM
17.000	1.488	tNET	RR	2	R15C32[0][A]	svo_hdmi_inst/svo_tmds_1/n223_s0/I0
17.958	0.958	tINS	RF	1	R15C32[0][A]	svo_hdmi_inst/svo_tmds_1/n223_s0/COUT
17.958	0.000	tNET	FF	2	R15C32[0][B]	svo_hdmi_inst/svo_tmds_1/n289_s0/CIN
18.015	0.057	tINS	FF	1	R15C32[0][B]	svo_hdmi_inst/svo_tmds_1/n289_s0/COUT
18.015	0.000	tNET	FF	2	R15C32[1][A]	svo_hdmi_inst/svo_tmds_1/n288_s0/CIN
18.072	0.057	tINS	FF	1	R15C32[1][A]	svo_hdmi_inst/svo_tmds_1/n288_s0/COUT
18.072	0.000	tNET	FF	2	R15C32[1][B]	svo_hdmi_inst/svo_tmds_1/n287_s0/CIN
18.635	0.563	tINS	FF	3	R15C32[1][B]	svo_hdmi_inst/svo_tmds_1/n287_s0/SUM
20.265	1.629	tNET	FF	1	R13C31[3][B]	svo_hdmi_inst/svo_tmds_1/n377_s7/I3
21.297	1.032	tINS	FF	4	R13C31[3][B]	svo_hdmi_inst/svo_tmds_1/n377_s7/F
21.319	0.022	tNET	FF	1	R13C31[2][A]	svo_hdmi_inst/svo_tmds_1/n379_s4/I1
22.351	1.032	tINS	FF	1	R13C31[2][A]	svo_hdmi_inst/svo_tmds_1/n379_s4/F
22.356	0.005	tNET	FF	1	R13C31[3][A]	svo_hdmi_inst/svo_tmds_1/n379_s1/I1
23.158	0.802	tINS	FR	1	R13C31[3][A]	svo_hdmi_inst/svo_tmds_1/n379_s1/F
23.577	0.419	tNET	RR	1	R12C31[2][A]	svo_hdmi_inst/svo_tmds_1/n379_s0/I0
24.609	1.032	tINS	RF	1	R12C31[2][A]	svo_hdmi_inst/svo_tmds_1/n379_s0/F
24.609	0.000	tNET	FF	1	R12C31[2][A]	svo_hdmi_inst/svo_tmds_1/cnt_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
39.682	39.682					active clock edge time
39.682	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
40.255	0.242	tNET	RR	1	R12C31[2][A]	svo_hdmi_inst/svo_tmds_1/cnt_5_s0/CLK
39.855	-0.400	tSu		1	R12C31[2][A]	svo_hdmi_inst/svo_tmds_1/cnt_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	39.682
Logic Level	17
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 13.162, 54.758%; route: 10.416, 43.336%; tC2Q: 0.458, 1.907%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path11

Path Summary:

Slack	15.502
Data Arrival Time	24.353
Data Required Time	39.855
From	svo_hdmi_inst/svo_enc/out_axis_tdata_3_s0
To	svo_hdmi_inst/svo_tmds_2/cnt_6_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R8C16[1][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_3_s0/CLK
1.030	0.458	tC2Q	RF	4	R8C16[1][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_3_s0/Q
2.992	1.962	tNET	FF	1	R8C28[0][A]	svo_hdmi_inst/svo_tmds_2/n146_s15/I2
3.814	0.822	tINS	FF	12	R8C28[0][A]	svo_hdmi_inst/svo_tmds_2/n146_s15/F
3.853	0.038	tNET	FF	1	R8C28[3][A]	svo_hdmi_inst/svo_tmds_2/n406_s2/I1
4.479	0.626	tINS	FF	1	R8C28[3][A]	svo_hdmi_inst/svo_tmds_2/n406_s2/F
4.484	0.005	tNET	FF	1	R8C28[2][A]	svo_hdmi_inst/svo_tmds_2/n88_s4/I3
5.306	0.822	tINS	FF	3	R8C28[2][A]	svo_hdmi_inst/svo_tmds_2/n88_s4/F
6.142	0.836	tNET	FF	1	R8C29[3][B]	svo_hdmi_inst/svo_tmds_2/n88_s2/I2
7.174	1.032	tINS	FF	8	R8C29[3][B]	svo_hdmi_inst/svo_tmds_2/n88_s2/F
8.018	0.843	tNET	FF	1	R8C30[3][A]	svo_hdmi_inst/svo_tmds_2/n407_s3/I0
9.117	1.099	tINS	FF	3	R8C30[3][A]	svo_hdmi_inst/svo_tmds_2/n407_s3/F
9.943	0.826	tNET	FF	1	R9C30[2][A]	svo_hdmi_inst/svo_tmds_2/n175_s16/I3
10.969	1.026	tINS	FR	3	R9C30[2][A]	svo_hdmi_inst/svo_tmds_2/n175_s16/F
11.394	0.425	tNET	RR	1	R9C31[2][B]	svo_hdmi_inst/svo_tmds_2/n175_s14/I1
12.020	0.626	tINS	RF	4	R9C31[2][B]	svo_hdmi_inst/svo_tmds_2/n175_s14/F
13.331	1.311	tNET	FF	1	R6C33[3][A]	svo_hdmi_inst/svo_tmds_2/n176_s13/I1
14.153	0.822	tINS	FF	4	R6C33[3][A]	svo_hdmi_inst/svo_tmds_2/n176_s13/F
15.458	1.305	tNET	FF	2	R6C30[0][A]	svo_hdmi_inst/svo_tmds_2/n245_s/I1
16.008	0.550	tINS	FR	1	R6C30[0][A]	svo_hdmi_inst/svo_tmds_2/n245_s/COUT
16.008	0.000	tNET	RR	2	R6C30[0][B]	svo_hdmi_inst/svo_tmds_2/n326_s/CIN
16.065	0.057	tINS	RF	1	R6C30[0][B]	svo_hdmi_inst/svo_tmds_2/n326_s/COUT
16.065	0.000	tNET	FF	2	R6C30[1][A]	svo_hdmi_inst/svo_tmds_2/n325_s/CIN
16.628	0.563	tINS	FF	1	R6C30[1][A]	svo_hdmi_inst/svo_tmds_2/n325_s/SUM
18.418	1.790	tNET	FF	2	R7C30[1][A]	svo_hdmi_inst/svo_tmds_2/n325_s0/I0
19.376	0.958	tINS	FF	1	R7C30[1][A]	svo_hdmi_inst/svo_tmds_2/n325_s0/COUT
19.376	0.000	tNET	FF	2	R7C30[1][B]	svo_hdmi_inst/svo_tmds_2/n324_s0/CIN
19.433	0.057	tINS	FF	1	R7C30[1][B]	svo_hdmi_inst/svo_tmds_2/n324_s0/COUT
19.433	0.000	tNET	FF	2	R7C30[2][A]	svo_hdmi_inst/svo_tmds_2/n323_s0/CIN
19.490	0.057	tINS	FF	1	R7C30[2][A]	svo_hdmi_inst/svo_tmds_2/n323_s0/COUT
19.490	0.000	tNET	FF	2	R7C30[2][B]	svo_hdmi_inst/svo_tmds_2/n322_s0/CIN
19.547	0.057	tINS	FF	1	R7C30[2][B]	svo_hdmi_inst/svo_tmds_2/n322_s0/COUT
19.547	0.000	tNET	FF	2	R7C31[0][A]	svo_hdmi_inst/svo_tmds_2/n321_s0/CIN
20.110	0.563	tINS	FF	3	R7C31[0][A]	svo_hdmi_inst/svo_tmds_2/n321_s0/SUM
20.946	0.836	tNET	FF	1	R7C29[0][B]	svo_hdmi_inst/svo_tmds_2/n378_s3/I3
22.045	1.099	tINS	FF	1	R7C29[0][B]	svo_hdmi_inst/svo_tmds_2/n378_s3/F
22.051	0.005	tNET	FF	1	R7C29[1][B]	svo_hdmi_inst/svo_tmds_2/n378_s1/I0
23.112	1.061	tINS	FR	1	R7C29[1][B]	svo_hdmi_inst/svo_tmds_2/n378_s1/F
23.531	0.419	tNET	RR	1	R7C28[2][B]	svo_hdmi_inst/svo_tmds_2/n378_s0/I0
24.353	0.822	tINS	RF	1	R7C28[2][B]	svo_hdmi_inst/svo_tmds_2/n378_s0/F
24.353	0.000	tNET	FF	1	R7C28[2][B]	svo_hdmi_inst/svo_tmds_2/cnt_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
39.682	39.682					active clock edge time
39.682	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
40.255	0.242	tNET	RR	1	R7C28[2][B]	svo_hdmi_inst/svo_tmds_2/cnt_6_s0/CLK
39.855	-0.400	tSu		1	R7C28[2][B]	svo_hdmi_inst/svo_tmds_2/cnt_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	39.682
Logic Level	16
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 12.719, 53.485%; route: 10.603, 44.588%; tC2Q: 0.458, 1.927%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path12

Path Summary:

Slack	15.652
Data Arrival Time	24.202
Data Required Time	39.855
From	svo_hdmi_inst/svo_enc/out_axis_tdata_11_s0
To	svo_hdmi_inst/svo_tmds_1/cnt_4_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R9C15[2][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_11_s0/CLK
1.030	0.458	tC2Q	RF	6	R9C15[2][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_11_s0/Q
4.103	3.073	tNET	FF	1	R16C34[3][A]	svo_hdmi_inst/svo_tmds_1/n407_s3/I2
4.729	0.626	tINS	FF	8	R16C34[3][A]	svo_hdmi_inst/svo_tmds_1/n407_s3/F
5.561	0.832	tNET	FF	1	R15C33[1][A]	svo_hdmi_inst/svo_tmds_1/n404_s3/I3
6.383	0.822	tINS	FF	5	R15C33[1][A]	svo_hdmi_inst/svo_tmds_1/n404_s3/F
6.405	0.022	tNET	FF	1	R15C33[3][A]	svo_hdmi_inst/svo_tmds_1/n88_s7/I3
7.031	0.626	tINS	FF	2	R15C33[3][A]	svo_hdmi_inst/svo_tmds_1/n88_s7/F
7.042	0.011	tNET	FF	1	R15C33[1][B]	svo_hdmi_inst/svo_tmds_1/n88_s3/I1
7.864	0.822	tINS	FF	1	R15C33[1][B]	svo_hdmi_inst/svo_tmds_1/n88_s3/F
7.869	0.005	tNET	FF	1	R15C33[2][A]	svo_hdmi_inst/svo_tmds_1/n88_s0/I3
8.968	1.099	tINS	FF	30	R15C33[2][A]	svo_hdmi_inst/svo_tmds_1/n88_s0/F
9.817	0.848	tNET	FF	1	R14C33[3][B]	svo_hdmi_inst/svo_tmds_1/n146_s13/I2
10.916	1.099	tINS	FF	3	R14C33[3][B]	svo_hdmi_inst/svo_tmds_1/n146_s13/F
11.729	0.813	tNET	FF	1	R13C32[3][B]	svo_hdmi_inst/svo_tmds_1/n146_s10/I2
12.761	1.032	tINS	FF	4	R13C32[3][B]	svo_hdmi_inst/svo_tmds_1/n146_s10/F
13.582	0.821	tNET	FF	1	R14C31[1][B]	svo_hdmi_inst/svo_tmds_1/n147_s18/I0
14.384	0.802	tINS	FR	4	R14C31[1][B]	svo_hdmi_inst/svo_tmds_1/n147_s18/F
14.811	0.427	tNET	RR	2	R14C32[0][A]	svo_hdmi_inst/svo_tmds_1/n223_s/I1
15.512	0.701	tINS	RR	1	R14C32[0][A]	svo_hdmi_inst/svo_tmds_1/n223_s/SUM
17.000	1.488	tNET	RR	2	R15C32[0][A]	svo_hdmi_inst/svo_tmds_1/n223_s0/I0
17.958	0.958	tINS	RF	1	R15C32[0][A]	svo_hdmi_inst/svo_tmds_1/n223_s0/COUT
17.958	0.000	tNET	FF	2	R15C32[0][B]	svo_hdmi_inst/svo_tmds_1/n289_s0/CIN
18.015	0.057	tINS	FF	1	R15C32[0][B]	svo_hdmi_inst/svo_tmds_1/n289_s0/COUT
18.015	0.000	tNET	FF	2	R15C32[1][A]	svo_hdmi_inst/svo_tmds_1/n288_s0/CIN
18.072	0.057	tINS	FF	1	R15C32[1][A]	svo_hdmi_inst/svo_tmds_1/n288_s0/COUT
18.072	0.000	tNET	FF	2	R15C32[1][B]	svo_hdmi_inst/svo_tmds_1/n287_s0/CIN
18.635	0.563	tINS	FF	3	R15C32[1][B]	svo_hdmi_inst/svo_tmds_1/n287_s0/SUM
20.265	1.629	tNET	FF	1	R13C31[3][B]	svo_hdmi_inst/svo_tmds_1/n377_s7/I3
21.297	1.032	tINS	FF	4	R13C31[3][B]	svo_hdmi_inst/svo_tmds_1/n377_s7/F
22.117	0.821	tNET	FF	1	R13C28[1][A]	svo_hdmi_inst/svo_tmds_1/n380_s4/I1
22.743	0.626	tINS	FF	1	R13C28[1][A]	svo_hdmi_inst/svo_tmds_1/n380_s4/F
22.749	0.005	tNET	FF	1	R13C28[2][A]	svo_hdmi_inst/svo_tmds_1/n380_s1/I1
23.375	0.626	tINS	FF	1	R13C28[2][A]	svo_hdmi_inst/svo_tmds_1/n380_s1/F
23.380	0.005	tNET	FF	1	R13C28[0][A]	svo_hdmi_inst/svo_tmds_1/n380_s0/I0
24.202	0.822	tINS	FF	1	R13C28[0][A]	svo_hdmi_inst/svo_tmds_1/n380_s0/F
24.202	0.000	tNET	FF	1	R13C28[0][A]	svo_hdmi_inst/svo_tmds_1/cnt_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
39.682	39.682					active clock edge time
39.682	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
40.255	0.242	tNET	RR	1	R13C28[0][A]	svo_hdmi_inst/svo_tmds_1/cnt_4_s0/CLK
39.855	-0.400	tSu		1	R13C28[0][A]	svo_hdmi_inst/svo_tmds_1/cnt_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	39.682
Logic Level	17
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 12.370, 52.348%; route: 10.802, 45.712%; tC2Q: 0.458, 1.940%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path13

Path Summary:

Slack	16.000
Data Arrival Time	23.854
Data Required Time	39.855
From	svo_hdmi_inst/svo_enc/out_axis_tdata_3_s0
To	svo_hdmi_inst/svo_tmds_2/cnt_3_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R8C16[1][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_3_s0/CLK
1.030	0.458	tC2Q	RF	4	R8C16[1][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_3_s0/Q
2.992	1.962	tNET	FF	1	R8C28[0][A]	svo_hdmi_inst/svo_tmds_2/n146_s15/I2
3.814	0.822	tINS	FF	12	R8C28[0][A]	svo_hdmi_inst/svo_tmds_2/n146_s15/F
3.853	0.038	tNET	FF	1	R8C28[3][A]	svo_hdmi_inst/svo_tmds_2/n406_s2/I1
4.479	0.626	tINS	FF	1	R8C28[3][A]	svo_hdmi_inst/svo_tmds_2/n406_s2/F
4.484	0.005	tNET	FF	1	R8C28[2][A]	svo_hdmi_inst/svo_tmds_2/n88_s4/I3
5.306	0.822	tINS	FF	3	R8C28[2][A]	svo_hdmi_inst/svo_tmds_2/n88_s4/F
6.142	0.836	tNET	FF	1	R8C29[3][B]	svo_hdmi_inst/svo_tmds_2/n88_s2/I2
7.174	1.032	tINS	FF	8	R8C29[3][B]	svo_hdmi_inst/svo_tmds_2/n88_s2/F
8.018	0.843	tNET	FF	1	R8C30[3][A]	svo_hdmi_inst/svo_tmds_2/n407_s3/I0
9.117	1.099	tINS	FF	3	R8C30[3][A]	svo_hdmi_inst/svo_tmds_2/n407_s3/F
9.943	0.826	tNET	FF	1	R9C30[2][A]	svo_hdmi_inst/svo_tmds_2/n175_s16/I3
10.969	1.026	tINS	FR	3	R9C30[2][A]	svo_hdmi_inst/svo_tmds_2/n175_s16/F
11.394	0.425	tNET	RR	1	R9C31[2][B]	svo_hdmi_inst/svo_tmds_2/n175_s14/I1
12.020	0.626	tINS	RF	4	R9C31[2][B]	svo_hdmi_inst/svo_tmds_2/n175_s14/F
13.331	1.311	tNET	FF	1	R6C33[3][A]	svo_hdmi_inst/svo_tmds_2/n176_s13/I1
14.153	0.822	tINS	FF	4	R6C33[3][A]	svo_hdmi_inst/svo_tmds_2/n176_s13/F
14.506	0.353	tNET	FF	2	R6C33[0][A]	svo_hdmi_inst/svo_tmds_2/n223_s/I1
15.056	0.550	tINS	FR	1	R6C33[0][A]	svo_hdmi_inst/svo_tmds_2/n223_s/COUT
15.056	0.000	tNET	RR	2	R6C33[0][B]	svo_hdmi_inst/svo_tmds_2/n289_s/CIN
15.113	0.057	tINS	RF	1	R6C33[0][B]	svo_hdmi_inst/svo_tmds_2/n289_s/COUT
15.113	0.000	tNET	FF	2	R6C33[1][A]	svo_hdmi_inst/svo_tmds_2/n288_s/CIN
15.676	0.563	tINS	FF	1	R6C33[1][A]	svo_hdmi_inst/svo_tmds_2/n288_s/SUM
16.497	0.821	tNET	FF	2	R7C33[1][A]	svo_hdmi_inst/svo_tmds_2/n288_s0/I0
17.455	0.958	tINS	FF	1	R7C33[1][A]	svo_hdmi_inst/svo_tmds_2/n288_s0/COUT
17.455	0.000	tNET	FF	2	R7C33[1][B]	svo_hdmi_inst/svo_tmds_2/n287_s0/CIN
18.018	0.563	tINS	FF	3	R7C33[1][B]	svo_hdmi_inst/svo_tmds_2/n287_s0/SUM
20.142	2.125	tNET	FF	1	R7C30[3][A]	svo_hdmi_inst/svo_tmds_2/n381_s4/I3
21.174	1.032	tINS	FF	1	R7C30[3][A]	svo_hdmi_inst/svo_tmds_2/n381_s4/F
21.995	0.821	tNET	FF	1	R7C28[3][A]	svo_hdmi_inst/svo_tmds_2/n381_s1/I1
23.027	1.032	tINS	FF	1	R7C28[3][A]	svo_hdmi_inst/svo_tmds_2/n381_s1/F
23.032	0.005	tNET	FF	1	R7C28[0][A]	svo_hdmi_inst/svo_tmds_2/n381_s0/I0
23.854	0.822	tINS	FF	1	R7C28[0][A]	svo_hdmi_inst/svo_tmds_2/n381_s0/F
23.854	0.000	tNET	FF	1	R7C28[0][A]	svo_hdmi_inst/svo_tmds_2/cnt_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
39.682	39.682					active clock edge time
39.682	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
40.255	0.242	tNET	RR	1	R7C28[0][A]	svo_hdmi_inst/svo_tmds_2/cnt_3_s0/CLK
39.855	-0.400	tSu		1	R7C28[0][A]	svo_hdmi_inst/svo_tmds_2/cnt_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	39.682
Logic Level	16
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 12.452, 53.483%; route: 10.372, 44.549%; tC2Q: 0.458, 1.969%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path14

Path Summary:

Slack	16.258
Data Arrival Time	23.597
Data Required Time	39.855
From	svo_hdmi_inst/svo_enc/out_axis_tdata_3_s0
To	svo_hdmi_inst/svo_tmds_2/cnt_2_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R8C16[1][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_3_s0/CLK
1.030	0.458	tC2Q	RF	4	R8C16[1][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_3_s0/Q
2.992	1.962	tNET	FF	1	R8C28[0][A]	svo_hdmi_inst/svo_tmds_2/n146_s15/I2
3.814	0.822	tINS	FF	12	R8C28[0][A]	svo_hdmi_inst/svo_tmds_2/n146_s15/F
3.853	0.038	tNET	FF	1	R8C28[3][A]	svo_hdmi_inst/svo_tmds_2/n406_s2/I1
4.479	0.626	tINS	FF	1	R8C28[3][A]	svo_hdmi_inst/svo_tmds_2/n406_s2/F
4.484	0.005	tNET	FF	1	R8C28[2][A]	svo_hdmi_inst/svo_tmds_2/n88_s4/I3
5.306	0.822	tINS	FF	3	R8C28[2][A]	svo_hdmi_inst/svo_tmds_2/n88_s4/F
6.142	0.836	tNET	FF	1	R8C29[3][B]	svo_hdmi_inst/svo_tmds_2/n88_s2/I2
7.174	1.032	tINS	FF	8	R8C29[3][B]	svo_hdmi_inst/svo_tmds_2/n88_s2/F
8.018	0.843	tNET	FF	1	R8C30[3][A]	svo_hdmi_inst/svo_tmds_2/n407_s3/I0
9.117	1.099	tINS	FF	3	R8C30[3][A]	svo_hdmi_inst/svo_tmds_2/n407_s3/F
9.943	0.826	tNET	FF	1	R9C30[2][A]	svo_hdmi_inst/svo_tmds_2/n175_s16/I3
10.969	1.026	tINS	FR	3	R9C30[2][A]	svo_hdmi_inst/svo_tmds_2/n175_s16/F
11.394	0.425	tNET	RR	1	R9C31[2][B]	svo_hdmi_inst/svo_tmds_2/n175_s14/I1
12.020	0.626	tINS	RF	4	R9C31[2][B]	svo_hdmi_inst/svo_tmds_2/n175_s14/F
13.331	1.311	tNET	FF	1	R6C33[3][A]	svo_hdmi_inst/svo_tmds_2/n176_s13/I1
14.153	0.822	tINS	FF	4	R6C33[3][A]	svo_hdmi_inst/svo_tmds_2/n176_s13/F
15.458	1.305	tNET	FF	2	R6C30[0][A]	svo_hdmi_inst/svo_tmds_2/n245_s/I1
16.008	0.550	tINS	FR	1	R6C30[0][A]	svo_hdmi_inst/svo_tmds_2/n245_s/COUT
16.008	0.000	tNET	RR	2	R6C30[0][B]	svo_hdmi_inst/svo_tmds_2/n326_s/CIN
16.571	0.563	tINS	RF	1	R6C30[0][B]	svo_hdmi_inst/svo_tmds_2/n326_s/SUM
18.345	1.773	tNET	FF	2	R7C30[0][B]	svo_hdmi_inst/svo_tmds_2/n326_s0/I0
19.303	0.958	tINS	FF	1	R7C30[0][B]	svo_hdmi_inst/svo_tmds_2/n326_s0/COUT
19.303	0.000	tNET	FF	2	R7C30[1][A]	svo_hdmi_inst/svo_tmds_2/n325_s0/CIN
19.831	0.528	tINS	FR	4	R7C30[1][A]	svo_hdmi_inst/svo_tmds_2/n325_s0/SUM
20.258	0.427	tNET	RR	1	R7C31[1][A]	svo_hdmi_inst/svo_tmds_2/n382_s3/I2
21.319	1.061	tINS	RR	1	R7C31[1][A]	svo_hdmi_inst/svo_tmds_2/n382_s3/F
21.737	0.419	tNET	RR	1	R7C32[3][A]	svo_hdmi_inst/svo_tmds_2/n382_s1/I0
22.769	1.032	tINS	RF	1	R7C32[3][A]	svo_hdmi_inst/svo_tmds_2/n382_s1/F
22.775	0.005	tNET	FF	1	R7C32[0][A]	svo_hdmi_inst/svo_tmds_2/n382_s0/I0
23.597	0.822	tINS	FF	1	R7C32[0][A]	svo_hdmi_inst/svo_tmds_2/n382_s0/F
23.597	0.000	tNET	FF	1	R7C32[0][A]	svo_hdmi_inst/svo_tmds_2/cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
39.682	39.682					active clock edge time
39.682	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
40.255	0.242	tNET	RR	1	R7C32[0][A]	svo_hdmi_inst/svo_tmds_2/cnt_2_s0/CLK
39.855	-0.400	tSu		1	R7C32[0][A]	svo_hdmi_inst/svo_tmds_2/cnt_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	39.682
Logic Level	16
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 12.389, 53.807%; route: 10.177, 44.202%; tC2Q: 0.458, 1.991%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path15

Path Summary:

Slack	16.465
Data Arrival Time	23.390
Data Required Time	39.855
From	svo_hdmi_inst/svo_enc/out_axis_tdata_11_s0
To	svo_hdmi_inst/svo_tmds_1/cnt_3_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R9C15[2][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_11_s0/CLK
1.030	0.458	tC2Q	RF	6	R9C15[2][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_11_s0/Q
4.103	3.073	tNET	FF	1	R16C34[3][A]	svo_hdmi_inst/svo_tmds_1/n407_s3/I2
4.729	0.626	tINS	FF	8	R16C34[3][A]	svo_hdmi_inst/svo_tmds_1/n407_s3/F
5.561	0.832	tNET	FF	1	R15C33[1][A]	svo_hdmi_inst/svo_tmds_1/n404_s3/I3
6.383	0.822	tINS	FF	5	R15C33[1][A]	svo_hdmi_inst/svo_tmds_1/n404_s3/F
6.405	0.022	tNET	FF	1	R15C33[3][A]	svo_hdmi_inst/svo_tmds_1/n88_s7/I3
7.031	0.626	tINS	FF	2	R15C33[3][A]	svo_hdmi_inst/svo_tmds_1/n88_s7/F
7.042	0.011	tNET	FF	1	R15C33[1][B]	svo_hdmi_inst/svo_tmds_1/n88_s3/I1
7.864	0.822	tINS	FF	1	R15C33[1][B]	svo_hdmi_inst/svo_tmds_1/n88_s3/F
7.869	0.005	tNET	FF	1	R15C33[2][A]	svo_hdmi_inst/svo_tmds_1/n88_s0/I3
8.968	1.099	tINS	FF	30	R15C33[2][A]	svo_hdmi_inst/svo_tmds_1/n88_s0/F
9.817	0.848	tNET	FF	1	R14C33[3][B]	svo_hdmi_inst/svo_tmds_1/n146_s13/I2
10.916	1.099	tINS	FF	3	R14C33[3][B]	svo_hdmi_inst/svo_tmds_1/n146_s13/F
11.729	0.813	tNET	FF	1	R13C32[3][B]	svo_hdmi_inst/svo_tmds_1/n146_s10/I2
12.761	1.032	tINS	FF	4	R13C32[3][B]	svo_hdmi_inst/svo_tmds_1/n146_s10/F
13.582	0.821	tNET	FF	1	R14C31[1][B]	svo_hdmi_inst/svo_tmds_1/n147_s18/I0
14.384	0.802	tINS	FR	4	R14C31[1][B]	svo_hdmi_inst/svo_tmds_1/n147_s18/F
14.811	0.427	tNET	RR	2	R14C32[0][A]	svo_hdmi_inst/svo_tmds_1/n223_s/I1
15.512	0.701	tINS	RR	1	R14C32[0][A]	svo_hdmi_inst/svo_tmds_1/n223_s/SUM
17.000	1.488	tNET	RR	2	R15C32[0][A]	svo_hdmi_inst/svo_tmds_1/n223_s0/I0
17.958	0.958	tINS	RF	1	R15C32[0][A]	svo_hdmi_inst/svo_tmds_1/n223_s0/COUT
17.958	0.000	tNET	FF	2	R15C32[0][B]	svo_hdmi_inst/svo_tmds_1/n289_s0/CIN
18.015	0.057	tINS	FF	1	R15C32[0][B]	svo_hdmi_inst/svo_tmds_1/n289_s0/COUT
18.015	0.000	tNET	FF	2	R15C32[1][A]	svo_hdmi_inst/svo_tmds_1/n288_s0/CIN
18.072	0.057	tINS	FF	1	R15C32[1][A]	svo_hdmi_inst/svo_tmds_1/n288_s0/COUT
18.072	0.000	tNET	FF	2	R15C32[1][B]	svo_hdmi_inst/svo_tmds_1/n287_s0/CIN
18.635	0.563	tINS	FF	3	R15C32[1][B]	svo_hdmi_inst/svo_tmds_1/n287_s0/SUM
19.941	1.306	tNET	FF	1	R13C31[2][B]	svo_hdmi_inst/svo_tmds_1/n381_s4/I3
21.040	1.099	tINS	FF	1	R13C31[2][B]	svo_hdmi_inst/svo_tmds_1/n381_s4/F
21.530	0.490	tNET	FF	1	R13C30[2][A]	svo_hdmi_inst/svo_tmds_1/n381_s1/I1
22.562	1.032	tINS	FF	1	R13C30[2][A]	svo_hdmi_inst/svo_tmds_1/n381_s1/F
22.568	0.005	tNET	FF	1	R13C30[0][A]	svo_hdmi_inst/svo_tmds_1/n381_s0/I0
23.390	0.822	tINS	FF	1	R13C30[0][A]	svo_hdmi_inst/svo_tmds_1/n381_s0/F
23.390	0.000	tNET	FF	1	R13C30[0][A]	svo_hdmi_inst/svo_tmds_1/cnt_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
39.682	39.682					active clock edge time
39.682	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
40.255	0.242	tNET	RR	1	R13C30[0][A]	svo_hdmi_inst/svo_tmds_1/cnt_3_s0/CLK
39.855	-0.400	tSu		1	R13C30[0][A]	svo_hdmi_inst/svo_tmds_1/cnt_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	39.682
Logic Level	16
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 12.217, 53.542%; route: 10.142, 44.449%; tC2Q: 0.458, 2.009%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path16

Path Summary:

Slack	16.555
Data Arrival Time	23.299
Data Required Time	39.855
From	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0
To	svo_hdmi_inst/svo_tmds_0/cnt_1_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R9C18[0][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0/CLK
1.030	0.458	tC2Q	RF	8	R9C18[0][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0/Q
3.326	2.296	tNET	FF	1	R15C24[0][B]	svo_hdmi_inst/svo_tmds_0/n404_s4/I3
3.952	0.626	tINS	FF	9	R15C24[0][B]	svo_hdmi_inst/svo_tmds_0/n404_s4/F
4.799	0.847	tNET	FF	1	R16C23[2][B]	svo_hdmi_inst/svo_tmds_0/n406_s2/I1
5.825	1.026	tINS	FR	3	R16C23[2][B]	svo_hdmi_inst/svo_tmds_0/n406_s2/F
6.248	0.423	tNET	RR	1	R16C24[1][B]	svo_hdmi_inst/svo_tmds_0/n88_s7/I3
7.347	1.099	tINS	RF	2	R16C24[1][B]	svo_hdmi_inst/svo_tmds_0/n88_s7/F
7.358	0.011	tNET	FF	1	R16C24[3][A]	svo_hdmi_inst/svo_tmds_0/n88_s3/I1
8.457	1.099	tINS	FF	1	R16C24[3][A]	svo_hdmi_inst/svo_tmds_0/n88_s3/F
8.462	0.005	tNET	FF	1	R16C24[3][B]	svo_hdmi_inst/svo_tmds_0/n88_s0/I3
9.264	0.802	tINS	FR	30	R16C24[3][B]	svo_hdmi_inst/svo_tmds_0/n88_s0/F
9.703	0.438	tNET	RR	1	R16C23[2][A]	svo_hdmi_inst/svo_tmds_0/n146_s13/I2
10.525	0.822	tINS	RF	3	R16C23[2][A]	svo_hdmi_inst/svo_tmds_0/n146_s13/F
11.338	0.813	tNET	FF	1	R15C22[2][A]	svo_hdmi_inst/svo_tmds_0/n146_s10/I2
12.370	1.032	tINS	FF	4	R15C22[2][A]	svo_hdmi_inst/svo_tmds_0/n146_s10/F
13.356	0.986	tNET	FF	1	R16C20[1][B]	svo_hdmi_inst/svo_tmds_0/n147_s18/I0
14.178	0.822	tINS	FF	4	R16C20[1][B]	svo_hdmi_inst/svo_tmds_0/n147_s18/F
15.648	1.470	tNET	FF	2	R15C16[0][A]	svo_hdmi_inst/svo_tmds_0/n223_s/I1
16.349	0.701	tINS	FR	1	R15C16[0][A]	svo_hdmi_inst/svo_tmds_0/n223_s/SUM
17.052	0.704	tNET	RR	2	R15C14[0][A]	svo_hdmi_inst/svo_tmds_0/n223_s0/I0
18.010	0.958	tINS	RF	1	R15C14[0][A]	svo_hdmi_inst/svo_tmds_0/n223_s0/COUT
18.010	0.000	tNET	FF	2	R15C14[0][B]	svo_hdmi_inst/svo_tmds_0/n289_s0/CIN
18.573	0.563	tINS	FF	5	R15C14[0][B]	svo_hdmi_inst/svo_tmds_0/n289_s0/SUM
20.043	1.470	tNET	FF	1	R16C20[3][B]	svo_hdmi_inst/svo_tmds_0/n366_s2/I1
20.865	0.822	tINS	FF	1	R16C20[3][B]	svo_hdmi_inst/svo_tmds_0/n366_s2/F
20.865	0.000	tNET	FF	1	R16C20[3][A]	svo_hdmi_inst/svo_tmds_0/n366_s0/I1
21.014	0.149	tINS	FF	1	R16C20[3][A]	svo_hdmi_inst/svo_tmds_0/n366_s0/O
22.477	1.463	tNET	FF	1	R16C20[0][A]	svo_hdmi_inst/svo_tmds_0/n383_s0/I1
23.299	0.822	tINS	FF	1	R16C20[0][A]	svo_hdmi_inst/svo_tmds_0/n383_s0/F
23.299	0.000	tNET	FF	1	R16C20[0][A]	svo_hdmi_inst/svo_tmds_0/cnt_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
39.682	39.682					active clock edge time
39.682	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
40.255	0.242	tNET	RR	1	R16C20[0][A]	svo_hdmi_inst/svo_tmds_0/cnt_1_s0/CLK
39.855	-0.400	tSu		1	R16C20[0][A]	svo_hdmi_inst/svo_tmds_0/cnt_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	39.682
Logic Level	14
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 11.343, 49.909%; route: 10.926, 48.074%; tC2Q: 0.458, 2.017%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path17

Path Summary:

Slack	16.582
Data Arrival Time	23.273
Data Required Time	39.855
From	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0
To	svo_hdmi_inst/svo_tmds_0/cnt_3_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R9C18[0][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0/CLK
1.030	0.458	tC2Q	RF	8	R9C18[0][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0/Q
3.326	2.296	tNET	FF	1	R15C24[0][B]	svo_hdmi_inst/svo_tmds_0/n404_s4/I3
3.952	0.626	tINS	FF	9	R15C24[0][B]	svo_hdmi_inst/svo_tmds_0/n404_s4/F
4.799	0.847	tNET	FF	1	R16C23[2][B]	svo_hdmi_inst/svo_tmds_0/n406_s2/I1
5.825	1.026	tINS	FR	3	R16C23[2][B]	svo_hdmi_inst/svo_tmds_0/n406_s2/F
6.248	0.423	tNET	RR	1	R16C24[1][B]	svo_hdmi_inst/svo_tmds_0/n88_s7/I3
7.347	1.099	tINS	RF	2	R16C24[1][B]	svo_hdmi_inst/svo_tmds_0/n88_s7/F
7.358	0.011	tNET	FF	1	R16C24[3][A]	svo_hdmi_inst/svo_tmds_0/n88_s3/I1
8.457	1.099	tINS	FF	1	R16C24[3][A]	svo_hdmi_inst/svo_tmds_0/n88_s3/F
8.462	0.005	tNET	FF	1	R16C24[3][B]	svo_hdmi_inst/svo_tmds_0/n88_s0/I3
9.264	0.802	tINS	FR	30	R16C24[3][B]	svo_hdmi_inst/svo_tmds_0/n88_s0/F
9.703	0.438	tNET	RR	1	R16C23[2][A]	svo_hdmi_inst/svo_tmds_0/n146_s13/I2
10.525	0.822	tINS	RF	3	R16C23[2][A]	svo_hdmi_inst/svo_tmds_0/n146_s13/F
11.338	0.813	tNET	FF	1	R15C22[3][B]	svo_hdmi_inst/svo_tmds_0/n145_s12/I2
12.370	1.032	tINS	FF	3	R15C22[3][B]	svo_hdmi_inst/svo_tmds_0/n145_s12/F
14.174	1.804	tNET	FF	1	R16C19[0][B]	svo_hdmi_inst/svo_tmds_0/n145_s11/I1
15.206	1.032	tINS	FF	3	R16C19[0][B]	svo_hdmi_inst/svo_tmds_0/n145_s11/F
16.512	1.306	tNET	FF	2	R15C16[1][A]	svo_hdmi_inst/svo_tmds_0/n288_s/I1
17.213	0.701	tINS	FR	1	R15C16[1][A]	svo_hdmi_inst/svo_tmds_0/n288_s/SUM
17.999	0.786	tNET	RR	2	R15C14[1][A]	svo_hdmi_inst/svo_tmds_0/n288_s0/I0
18.957	0.958	tINS	RF	1	R15C14[1][A]	svo_hdmi_inst/svo_tmds_0/n288_s0/COUT
18.957	0.000	tNET	FF	2	R15C14[1][B]	svo_hdmi_inst/svo_tmds_0/n287_s0/CIN
19.520	0.563	tINS	FF	3	R15C14[1][B]	svo_hdmi_inst/svo_tmds_0/n287_s0/SUM
19.862	0.342	tNET	FF	1	R15C14[3][B]	svo_hdmi_inst/svo_tmds_0/n381_s4/I3
20.684	0.822	tINS	FF	1	R15C14[3][B]	svo_hdmi_inst/svo_tmds_0/n381_s4/F
21.819	1.135	tNET	FF	1	R15C17[1][A]	svo_hdmi_inst/svo_tmds_0/n381_s1/I1
22.641	0.822	tINS	FF	1	R15C17[1][A]	svo_hdmi_inst/svo_tmds_0/n381_s1/F
22.647	0.005	tNET	FF	1	R15C17[1][B]	svo_hdmi_inst/svo_tmds_0/n381_s0/I0
23.273	0.626	tINS	FF	1	R15C17[1][B]	svo_hdmi_inst/svo_tmds_0/n381_s0/F
23.273	0.000	tNET	FF	1	R15C17[1][B]	svo_hdmi_inst/svo_tmds_0/cnt_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
39.682	39.682					active clock edge time
39.682	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
40.255	0.242	tNET	RR	1	R15C17[1][B]	svo_hdmi_inst/svo_tmds_0/cnt_3_s0/CLK
39.855	-0.400	tSu		1	R15C17[1][B]	svo_hdmi_inst/svo_tmds_0/cnt_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	39.682
Logic Level	15
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 12.030, 52.994%; route: 10.212, 44.987%; tC2Q: 0.458, 2.019%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path18

Path Summary:

Slack	16.677
Data Arrival Time	23.178
Data Required Time	39.855
From	svo_hdmi_inst/svo_enc/out_axis_tdata_11_s0
To	svo_hdmi_inst/svo_tmds_1/cnt_2_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R9C15[2][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_11_s0/CLK
1.030	0.458	tC2Q	RF	6	R9C15[2][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_11_s0/Q
4.103	3.073	tNET	FF	1	R16C34[3][A]	svo_hdmi_inst/svo_tmds_1/n407_s3/I2
4.729	0.626	tINS	FF	8	R16C34[3][A]	svo_hdmi_inst/svo_tmds_1/n407_s3/F
5.561	0.832	tNET	FF	1	R15C33[1][A]	svo_hdmi_inst/svo_tmds_1/n404_s3/I3
6.383	0.822	tINS	FF	5	R15C33[1][A]	svo_hdmi_inst/svo_tmds_1/n404_s3/F
6.405	0.022	tNET	FF	1	R15C33[3][A]	svo_hdmi_inst/svo_tmds_1/n88_s7/I3
7.031	0.626	tINS	FF	2	R15C33[3][A]	svo_hdmi_inst/svo_tmds_1/n88_s7/F
7.042	0.011	tNET	FF	1	R15C33[1][B]	svo_hdmi_inst/svo_tmds_1/n88_s3/I1
7.864	0.822	tINS	FF	1	R15C33[1][B]	svo_hdmi_inst/svo_tmds_1/n88_s3/F
7.869	0.005	tNET	FF	1	R15C33[2][A]	svo_hdmi_inst/svo_tmds_1/n88_s0/I3
8.968	1.099	tINS	FF	30	R15C33[2][A]	svo_hdmi_inst/svo_tmds_1/n88_s0/F
9.817	0.848	tNET	FF	1	R14C33[3][B]	svo_hdmi_inst/svo_tmds_1/n146_s13/I2
10.916	1.099	tINS	FF	3	R14C33[3][B]	svo_hdmi_inst/svo_tmds_1/n146_s13/F
11.729	0.813	tNET	FF	1	R13C32[3][B]	svo_hdmi_inst/svo_tmds_1/n146_s10/I2
12.761	1.032	tINS	FF	4	R13C32[3][B]	svo_hdmi_inst/svo_tmds_1/n146_s10/F
13.582	0.821	tNET	FF	1	R14C31[1][B]	svo_hdmi_inst/svo_tmds_1/n147_s18/I0
14.384	0.802	tINS	FR	4	R14C31[1][B]	svo_hdmi_inst/svo_tmds_1/n147_s18/F
14.811	0.427	tNET	RR	2	R14C32[0][A]	svo_hdmi_inst/svo_tmds_1/n223_s/I1
15.512	0.701	tINS	RR	1	R14C32[0][A]	svo_hdmi_inst/svo_tmds_1/n223_s/SUM
17.000	1.488	tNET	RR	2	R15C32[0][A]	svo_hdmi_inst/svo_tmds_1/n223_s0/I0
17.958	0.958	tINS	RF	1	R15C32[0][A]	svo_hdmi_inst/svo_tmds_1/n223_s0/COUT
17.958	0.000	tNET	FF	2	R15C32[0][B]	svo_hdmi_inst/svo_tmds_1/n289_s0/CIN
18.015	0.057	tINS	FF	1	R15C32[0][B]	svo_hdmi_inst/svo_tmds_1/n289_s0/COUT
18.015	0.000	tNET	FF	2	R15C32[1][A]	svo_hdmi_inst/svo_tmds_1/n288_s0/CIN
18.578	0.563	tINS	FF	4	R15C32[1][A]	svo_hdmi_inst/svo_tmds_1/n288_s0/SUM
20.208	1.629	tNET	FF	1	R12C31[0][A]	svo_hdmi_inst/svo_tmds_1/n382_s4/I2
21.307	1.099	tINS	FF	1	R12C31[0][A]	svo_hdmi_inst/svo_tmds_1/n382_s4/F
21.312	0.005	tNET	FF	1	R12C31[0][B]	svo_hdmi_inst/svo_tmds_1/n382_s1/I1
21.937	0.625	tINS	FR	1	R12C31[0][B]	svo_hdmi_inst/svo_tmds_1/n382_s1/F
22.356	0.419	tNET	RR	1	R13C31[0][A]	svo_hdmi_inst/svo_tmds_1/n382_s0/I0
23.178	0.822	tINS	RF	1	R13C31[0][A]	svo_hdmi_inst/svo_tmds_1/n382_s0/F
23.178	0.000	tNET	FF	1	R13C31[0][A]	svo_hdmi_inst/svo_tmds_1/cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
39.682	39.682					active clock edge time
39.682	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
40.255	0.242	tNET	RR	1	R13C31[0][A]	svo_hdmi_inst/svo_tmds_1/cnt_2_s0/CLK
39.855	-0.400	tSu		1	R13C31[0][A]	svo_hdmi_inst/svo_tmds_1/cnt_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	39.682
Logic Level	16
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 11.753, 51.991%; route: 10.395, 45.982%; tC2Q: 0.458, 2.027%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path19

Path Summary:

Slack	16.970
Data Arrival Time	22.884
Data Required Time	39.855
From	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0
To	svo_hdmi_inst/svo_tmds_0/q_out_4_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R9C18[0][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0/CLK
1.030	0.458	tC2Q	RF	8	R9C18[0][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0/Q
3.326	2.296	tNET	FF	1	R15C24[0][B]	svo_hdmi_inst/svo_tmds_0/n404_s4/I3
3.952	0.626	tINS	FF	9	R15C24[0][B]	svo_hdmi_inst/svo_tmds_0/n404_s4/F
4.799	0.847	tNET	FF	1	R16C23[2][B]	svo_hdmi_inst/svo_tmds_0/n406_s2/I1
5.825	1.026	tINS	FR	3	R16C23[2][B]	svo_hdmi_inst/svo_tmds_0/n406_s2/F
6.248	0.423	tNET	RR	1	R16C24[1][B]	svo_hdmi_inst/svo_tmds_0/n88_s7/I3
7.347	1.099	tINS	RF	2	R16C24[1][B]	svo_hdmi_inst/svo_tmds_0/n88_s7/F
7.358	0.011	tNET	FF	1	R16C24[3][A]	svo_hdmi_inst/svo_tmds_0/n88_s3/I1
8.457	1.099	tINS	FF	1	R16C24[3][A]	svo_hdmi_inst/svo_tmds_0/n88_s3/F
8.462	0.005	tNET	FF	1	R16C24[3][B]	svo_hdmi_inst/svo_tmds_0/n88_s0/I3
9.264	0.802	tINS	FR	30	R16C24[3][B]	svo_hdmi_inst/svo_tmds_0/n88_s0/F
9.703	0.438	tNET	RR	1	R16C23[2][A]	svo_hdmi_inst/svo_tmds_0/n146_s13/I2
10.525	0.822	tINS	RF	3	R16C23[2][A]	svo_hdmi_inst/svo_tmds_0/n146_s13/F
11.338	0.813	tNET	FF	1	R15C22[3][B]	svo_hdmi_inst/svo_tmds_0/n145_s12/I2
12.370	1.032	tINS	FF	3	R15C22[3][B]	svo_hdmi_inst/svo_tmds_0/n145_s12/F
14.174	1.804	tNET	FF	1	R16C19[0][B]	svo_hdmi_inst/svo_tmds_0/n145_s11/I1
15.206	1.032	tINS	FF	3	R16C19[0][B]	svo_hdmi_inst/svo_tmds_0/n145_s11/F
15.702	0.496	tNET	FF	2	R16C21[0][B]	svo_hdmi_inst/svo_tmds_0/n180_s0/I1
16.747	1.045	tINS	FF	1	R16C21[0][B]	svo_hdmi_inst/svo_tmds_0/n180_s0/COUT
16.747	0.000	tNET	FF	2	R16C21[1][A]	svo_hdmi_inst/svo_tmds_0/n181_s0/CIN
16.804	0.057	tINS	FF	1	R16C21[1][A]	svo_hdmi_inst/svo_tmds_0/n181_s0/COUT
17.857	1.053	tNET	FF	1	R16C19[0][A]	svo_hdmi_inst/svo_tmds_0/n183_s0/I2
18.956	1.099	tINS	FF	10	R16C19[0][A]	svo_hdmi_inst/svo_tmds_0/n183_s0/F
20.126	1.170	tNET	FF	1	R15C23[2][B]	svo_hdmi_inst/svo_tmds_0/n359_s1/I3
20.948	0.822	tINS	FF	8	R15C23[2][B]	svo_hdmi_inst/svo_tmds_0/n359_s1/F
21.785	0.838	tNET	FF	1	R16C24[0][B]	svo_hdmi_inst/svo_tmds_0/n406_s1/I2
22.884	1.099	tINS	FF	1	R16C24[0][B]	svo_hdmi_inst/svo_tmds_0/n406_s1/F
22.884	0.000	tNET	FF	1	R16C24[0][B]	svo_hdmi_inst/svo_tmds_0/q_out_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
39.682	39.682					active clock edge time
39.682	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
40.255	0.242	tNET	RR	1	R16C24[0][B]	svo_hdmi_inst/svo_tmds_0/q_out_4_s0/CLK
39.855	-0.400	tSu		1	R16C24[0][B]	svo_hdmi_inst/svo_tmds_0/q_out_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	39.682
Logic Level	14
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 11.660, 52.258%; route: 10.194, 45.688%; tC2Q: 0.458, 2.054%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path20

Path Summary:

Slack	16.999
Data Arrival Time	22.856
Data Required Time	39.855
From	svo_hdmi_inst/svo_enc/out_axis_tdata_3_s0
To	svo_hdmi_inst/svo_tmds_2/cnt_1_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R8C16[1][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_3_s0/CLK
1.030	0.458	tC2Q	RF	4	R8C16[1][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_3_s0/Q
2.992	1.962	tNET	FF	1	R8C28[0][A]	svo_hdmi_inst/svo_tmds_2/n146_s15/I2
3.814	0.822	tINS	FF	12	R8C28[0][A]	svo_hdmi_inst/svo_tmds_2/n146_s15/F
3.853	0.038	tNET	FF	1	R8C28[3][A]	svo_hdmi_inst/svo_tmds_2/n406_s2/I1
4.479	0.626	tINS	FF	1	R8C28[3][A]	svo_hdmi_inst/svo_tmds_2/n406_s2/F
4.484	0.005	tNET	FF	1	R8C28[2][A]	svo_hdmi_inst/svo_tmds_2/n88_s4/I3
5.306	0.822	tINS	FF	3	R8C28[2][A]	svo_hdmi_inst/svo_tmds_2/n88_s4/F
6.142	0.836	tNET	FF	1	R8C29[3][B]	svo_hdmi_inst/svo_tmds_2/n88_s2/I2
7.174	1.032	tINS	FF	8	R8C29[3][B]	svo_hdmi_inst/svo_tmds_2/n88_s2/F
8.018	0.843	tNET	FF	1	R8C30[3][A]	svo_hdmi_inst/svo_tmds_2/n407_s3/I0
9.117	1.099	tINS	FF	3	R8C30[3][A]	svo_hdmi_inst/svo_tmds_2/n407_s3/F
9.943	0.826	tNET	FF	1	R9C30[2][A]	svo_hdmi_inst/svo_tmds_2/n175_s16/I3
10.969	1.026	tINS	FR	3	R9C30[2][A]	svo_hdmi_inst/svo_tmds_2/n175_s16/F
11.394	0.425	tNET	RR	1	R9C31[2][B]	svo_hdmi_inst/svo_tmds_2/n175_s14/I1
12.020	0.626	tINS	RF	4	R9C31[2][B]	svo_hdmi_inst/svo_tmds_2/n175_s14/F
13.331	1.311	tNET	FF	1	R6C33[3][A]	svo_hdmi_inst/svo_tmds_2/n176_s13/I1
14.153	0.822	tINS	FF	4	R6C33[3][A]	svo_hdmi_inst/svo_tmds_2/n176_s13/F
15.458	1.305	tNET	FF	2	R6C30[0][A]	svo_hdmi_inst/svo_tmds_2/n245_s/I1
16.008	0.550	tINS	FR	1	R6C30[0][A]	svo_hdmi_inst/svo_tmds_2/n245_s/COUT
16.008	0.000	tNET	RR	2	R6C30[0][B]	svo_hdmi_inst/svo_tmds_2/n326_s/CIN
16.571	0.563	tINS	RF	1	R6C30[0][B]	svo_hdmi_inst/svo_tmds_2/n326_s/SUM
18.345	1.773	tNET	FF	2	R7C30[0][B]	svo_hdmi_inst/svo_tmds_2/n326_s0/I0
19.339	0.994	tINS	FR	5	R7C30[0][B]	svo_hdmi_inst/svo_tmds_2/n326_s0/SUM
19.762	0.423	tNET	RR	1	R8C30[1][A]	svo_hdmi_inst/svo_tmds_2/n366_s1/I3
20.794	1.032	tINS	RF	1	R8C30[1][A]	svo_hdmi_inst/svo_tmds_2/n366_s1/F
20.794	0.000	tNET	FF	1	R8C30[1][A]	svo_hdmi_inst/svo_tmds_2/n366_s0/I0
20.943	0.149	tINS	FF	1	R8C30[1][A]	svo_hdmi_inst/svo_tmds_2/n366_s0/O
21.757	0.814	tNET	FF	1	R7C31[1][B]	svo_hdmi_inst/svo_tmds_2/n383_s0/I1
22.856	1.099	tINS	FF	1	R7C31[1][B]	svo_hdmi_inst/svo_tmds_2/n383_s0/F
22.856	0.000	tNET	FF	1	R7C31[1][B]	svo_hdmi_inst/svo_tmds_2/cnt_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
39.682	39.682					active clock edge time
39.682	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
40.255	0.242	tNET	RR	1	R7C31[1][B]	svo_hdmi_inst/svo_tmds_2/cnt_1_s0/CLK
39.855	-0.400	tSu		1	R7C31[1][B]	svo_hdmi_inst/svo_tmds_2/cnt_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	39.682
Logic Level	14
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 11.262, 50.540%; route: 10.563, 47.403%; tC2Q: 0.458, 2.057%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path21

Path Summary:

Slack	17.147
Data Arrival Time	22.707
Data Required Time	39.855
From	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0
To	svo_hdmi_inst/svo_tmds_0/cnt_2_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R9C18[0][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0/CLK
1.030	0.458	tC2Q	RF	8	R9C18[0][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0/Q
3.326	2.296	tNET	FF	1	R15C24[0][B]	svo_hdmi_inst/svo_tmds_0/n404_s4/I3
3.952	0.626	tINS	FF	9	R15C24[0][B]	svo_hdmi_inst/svo_tmds_0/n404_s4/F
4.799	0.847	tNET	FF	1	R16C23[2][B]	svo_hdmi_inst/svo_tmds_0/n406_s2/I1
5.825	1.026	tINS	FR	3	R16C23[2][B]	svo_hdmi_inst/svo_tmds_0/n406_s2/F
6.248	0.423	tNET	RR	1	R16C24[1][B]	svo_hdmi_inst/svo_tmds_0/n88_s7/I3
7.347	1.099	tINS	RF	2	R16C24[1][B]	svo_hdmi_inst/svo_tmds_0/n88_s7/F
7.358	0.011	tNET	FF	1	R16C24[3][A]	svo_hdmi_inst/svo_tmds_0/n88_s3/I1
8.457	1.099	tINS	FF	1	R16C24[3][A]	svo_hdmi_inst/svo_tmds_0/n88_s3/F
8.462	0.005	tNET	FF	1	R16C24[3][B]	svo_hdmi_inst/svo_tmds_0/n88_s0/I3
9.264	0.802	tINS	FR	30	R16C24[3][B]	svo_hdmi_inst/svo_tmds_0/n88_s0/F
9.703	0.438	tNET	RR	1	R16C23[2][A]	svo_hdmi_inst/svo_tmds_0/n146_s13/I2
10.525	0.822	tINS	RF	3	R16C23[2][A]	svo_hdmi_inst/svo_tmds_0/n146_s13/F
11.338	0.813	tNET	FF	1	R15C22[2][A]	svo_hdmi_inst/svo_tmds_0/n146_s10/I2
12.370	1.032	tINS	FF	4	R15C22[2][A]	svo_hdmi_inst/svo_tmds_0/n146_s10/F
13.356	0.986	tNET	FF	1	R16C20[1][B]	svo_hdmi_inst/svo_tmds_0/n147_s18/I0
14.178	0.822	tINS	FF	4	R16C20[1][B]	svo_hdmi_inst/svo_tmds_0/n147_s18/F
15.648	1.470	tNET	FF	2	R15C16[0][A]	svo_hdmi_inst/svo_tmds_0/n223_s/I1
16.198	0.550	tINS	FR	1	R15C16[0][A]	svo_hdmi_inst/svo_tmds_0/n223_s/COUT
16.198	0.000	tNET	RR	2	R15C16[0][B]	svo_hdmi_inst/svo_tmds_0/n289_s/CIN
16.761	0.563	tINS	RF	1	R15C16[0][B]	svo_hdmi_inst/svo_tmds_0/n289_s/SUM
17.565	0.804	tNET	FF	2	R15C14[0][B]	svo_hdmi_inst/svo_tmds_0/n289_s0/I0
18.523	0.958	tINS	FF	1	R15C14[0][B]	svo_hdmi_inst/svo_tmds_0/n289_s0/COUT
18.523	0.000	tNET	FF	2	R15C14[1][A]	svo_hdmi_inst/svo_tmds_0/n288_s0/CIN
19.051	0.528	tINS	FR	4	R15C14[1][A]	svo_hdmi_inst/svo_tmds_0/n288_s0/SUM
19.480	0.429	tNET	RR	1	R15C13[0][B]	svo_hdmi_inst/svo_tmds_0/n382_s4/I2
20.512	1.032	tINS	RF	1	R15C13[0][B]	svo_hdmi_inst/svo_tmds_0/n382_s4/F
20.848	0.336	tNET	FF	1	R15C13[3][A]	svo_hdmi_inst/svo_tmds_0/n382_s1/I1
21.880	1.032	tINS	FF	1	R15C13[3][A]	svo_hdmi_inst/svo_tmds_0/n382_s1/F
21.885	0.005	tNET	FF	1	R15C13[1][A]	svo_hdmi_inst/svo_tmds_0/n382_s0/I0
22.707	0.822	tINS	FF	1	R15C13[1][A]	svo_hdmi_inst/svo_tmds_0/n382_s0/F
22.707	0.000	tNET	FF	1	R15C13[1][A]	svo_hdmi_inst/svo_tmds_0/cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
39.682	39.682					active clock edge time
39.682	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
40.255	0.242	tNET	RR	1	R15C13[1][A]	svo_hdmi_inst/svo_tmds_0/cnt_2_s0/CLK
39.855	-0.400	tSu		1	R15C13[1][A]	svo_hdmi_inst/svo_tmds_0/cnt_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	39.682
Logic Level	16
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 12.813, 57.885%; route: 8.864, 40.045%; tC2Q: 0.458, 2.071%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path22

Path Summary:

Slack	17.199
Data Arrival Time	22.655
Data Required Time	39.855
From	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0
To	svo_hdmi_inst/svo_tmds_0/q_out_1_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R9C18[0][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0/CLK
1.030	0.458	tC2Q	RF	8	R9C18[0][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0/Q
3.326	2.296	tNET	FF	1	R15C24[0][B]	svo_hdmi_inst/svo_tmds_0/n404_s4/I3
3.952	0.626	tINS	FF	9	R15C24[0][B]	svo_hdmi_inst/svo_tmds_0/n404_s4/F
4.799	0.847	tNET	FF	1	R16C23[2][B]	svo_hdmi_inst/svo_tmds_0/n406_s2/I1
5.825	1.026	tINS	FR	3	R16C23[2][B]	svo_hdmi_inst/svo_tmds_0/n406_s2/F
6.248	0.423	tNET	RR	1	R16C24[1][B]	svo_hdmi_inst/svo_tmds_0/n88_s7/I3
7.347	1.099	tINS	RF	2	R16C24[1][B]	svo_hdmi_inst/svo_tmds_0/n88_s7/F
7.358	0.011	tNET	FF	1	R16C24[3][A]	svo_hdmi_inst/svo_tmds_0/n88_s3/I1
8.457	1.099	tINS	FF	1	R16C24[3][A]	svo_hdmi_inst/svo_tmds_0/n88_s3/F
8.462	0.005	tNET	FF	1	R16C24[3][B]	svo_hdmi_inst/svo_tmds_0/n88_s0/I3
9.264	0.802	tINS	FR	30	R16C24[3][B]	svo_hdmi_inst/svo_tmds_0/n88_s0/F
9.703	0.438	tNET	RR	1	R16C23[2][A]	svo_hdmi_inst/svo_tmds_0/n146_s13/I2
10.525	0.822	tINS	RF	3	R16C23[2][A]	svo_hdmi_inst/svo_tmds_0/n146_s13/F
11.338	0.813	tNET	FF	1	R15C22[3][B]	svo_hdmi_inst/svo_tmds_0/n145_s12/I2
12.370	1.032	tINS	FF	3	R15C22[3][B]	svo_hdmi_inst/svo_tmds_0/n145_s12/F
14.174	1.804	tNET	FF	1	R16C19[0][B]	svo_hdmi_inst/svo_tmds_0/n145_s11/I1
15.206	1.032	tINS	FF	3	R16C19[0][B]	svo_hdmi_inst/svo_tmds_0/n145_s11/F
15.702	0.496	tNET	FF	2	R16C21[0][B]	svo_hdmi_inst/svo_tmds_0/n180_s0/I1
16.747	1.045	tINS	FF	1	R16C21[0][B]	svo_hdmi_inst/svo_tmds_0/n180_s0/COUT
16.747	0.000	tNET	FF	2	R16C21[1][A]	svo_hdmi_inst/svo_tmds_0/n181_s0/CIN
16.804	0.057	tINS	FF	1	R16C21[1][A]	svo_hdmi_inst/svo_tmds_0/n181_s0/COUT
17.857	1.053	tNET	FF	1	R16C19[0][A]	svo_hdmi_inst/svo_tmds_0/n183_s0/I2
18.956	1.099	tINS	FF	10	R16C19[0][A]	svo_hdmi_inst/svo_tmds_0/n183_s0/F
20.126	1.170	tNET	FF	1	R15C23[1][B]	svo_hdmi_inst/svo_tmds_0/n409_s2/I2
20.752	0.626	tINS	FF	1	R15C23[1][B]	svo_hdmi_inst/svo_tmds_0/n409_s2/F
21.556	0.804	tNET	FF	1	R15C26[0][B]	svo_hdmi_inst/svo_tmds_0/n409_s0/I2
22.655	1.099	tINS	FF	1	R15C26[0][B]	svo_hdmi_inst/svo_tmds_0/n409_s0/F
22.655	0.000	tNET	FF	1	R15C26[0][B]	svo_hdmi_inst/svo_tmds_0/q_out_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
39.682	39.682					active clock edge time
39.682	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
40.255	0.242	tNET	RR	1	R15C26[0][B]	svo_hdmi_inst/svo_tmds_0/q_out_1_s0/CLK
39.855	-0.400	tSu		1	R15C26[0][B]	svo_hdmi_inst/svo_tmds_0/q_out_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	39.682
Logic Level	14
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 11.464, 51.913%; route: 10.161, 46.011%; tC2Q: 0.458, 2.076%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path23

Path Summary:

Slack	17.236
Data Arrival Time	22.619
Data Required Time	39.855
From	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0
To	svo_hdmi_inst/svo_tmds_0/q_out_3_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R9C18[0][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0/CLK
1.030	0.458	tC2Q	RF	8	R9C18[0][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0/Q
3.326	2.296	tNET	FF	1	R15C24[0][B]	svo_hdmi_inst/svo_tmds_0/n404_s4/I3
3.952	0.626	tINS	FF	9	R15C24[0][B]	svo_hdmi_inst/svo_tmds_0/n404_s4/F
4.799	0.847	tNET	FF	1	R16C23[2][B]	svo_hdmi_inst/svo_tmds_0/n406_s2/I1
5.825	1.026	tINS	FR	3	R16C23[2][B]	svo_hdmi_inst/svo_tmds_0/n406_s2/F
6.248	0.423	tNET	RR	1	R16C24[1][B]	svo_hdmi_inst/svo_tmds_0/n88_s7/I3
7.347	1.099	tINS	RF	2	R16C24[1][B]	svo_hdmi_inst/svo_tmds_0/n88_s7/F
7.358	0.011	tNET	FF	1	R16C24[3][A]	svo_hdmi_inst/svo_tmds_0/n88_s3/I1
8.457	1.099	tINS	FF	1	R16C24[3][A]	svo_hdmi_inst/svo_tmds_0/n88_s3/F
8.462	0.005	tNET	FF	1	R16C24[3][B]	svo_hdmi_inst/svo_tmds_0/n88_s0/I3
9.264	0.802	tINS	FR	30	R16C24[3][B]	svo_hdmi_inst/svo_tmds_0/n88_s0/F
9.703	0.438	tNET	RR	1	R16C23[2][A]	svo_hdmi_inst/svo_tmds_0/n146_s13/I2
10.525	0.822	tINS	RF	3	R16C23[2][A]	svo_hdmi_inst/svo_tmds_0/n146_s13/F
11.338	0.813	tNET	FF	1	R15C22[3][B]	svo_hdmi_inst/svo_tmds_0/n145_s12/I2
12.370	1.032	tINS	FF	3	R15C22[3][B]	svo_hdmi_inst/svo_tmds_0/n145_s12/F
14.174	1.804	tNET	FF	1	R16C19[0][B]	svo_hdmi_inst/svo_tmds_0/n145_s11/I1
15.206	1.032	tINS	FF	3	R16C19[0][B]	svo_hdmi_inst/svo_tmds_0/n145_s11/F
15.702	0.496	tNET	FF	2	R16C21[0][B]	svo_hdmi_inst/svo_tmds_0/n180_s0/I1
16.747	1.045	tINS	FF	1	R16C21[0][B]	svo_hdmi_inst/svo_tmds_0/n180_s0/COUT
16.747	0.000	tNET	FF	2	R16C21[1][A]	svo_hdmi_inst/svo_tmds_0/n181_s0/CIN
16.804	0.057	tINS	FF	1	R16C21[1][A]	svo_hdmi_inst/svo_tmds_0/n181_s0/COUT
17.857	1.053	tNET	FF	1	R16C19[0][A]	svo_hdmi_inst/svo_tmds_0/n183_s0/I2
18.956	1.099	tINS	FF	10	R16C19[0][A]	svo_hdmi_inst/svo_tmds_0/n183_s0/F
20.126	1.170	tNET	FF	1	R15C23[2][B]	svo_hdmi_inst/svo_tmds_0/n359_s1/I3
20.948	0.822	tINS	FF	8	R15C23[2][B]	svo_hdmi_inst/svo_tmds_0/n359_s1/F
21.797	0.849	tNET	FF	1	R16C25[2][A]	svo_hdmi_inst/svo_tmds_0/n407_s0/I2
22.619	0.822	tINS	FF	1	R16C25[2][A]	svo_hdmi_inst/svo_tmds_0/n407_s0/F
22.619	0.000	tNET	FF	1	R16C25[2][A]	svo_hdmi_inst/svo_tmds_0/q_out_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
39.682	39.682					active clock edge time
39.682	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
40.255	0.242	tNET	RR	1	R16C25[2][A]	svo_hdmi_inst/svo_tmds_0/q_out_3_s0/CLK
39.855	-0.400	tSu		1	R16C25[2][A]	svo_hdmi_inst/svo_tmds_0/q_out_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	39.682
Logic Level	14
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 11.383, 51.632%; route: 10.205, 46.289%; tC2Q: 0.458, 2.079%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path24

Path Summary:

Slack	17.464
Data Arrival Time	22.390
Data Required Time	39.855
From	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0
To	svo_hdmi_inst/svo_tmds_0/q_out_9_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R9C18[0][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0/CLK
1.030	0.458	tC2Q	RF	8	R9C18[0][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_17_s0/Q
3.326	2.296	tNET	FF	1	R15C24[0][B]	svo_hdmi_inst/svo_tmds_0/n404_s4/I3
3.952	0.626	tINS	FF	9	R15C24[0][B]	svo_hdmi_inst/svo_tmds_0/n404_s4/F
4.799	0.847	tNET	FF	1	R16C23[2][B]	svo_hdmi_inst/svo_tmds_0/n406_s2/I1
5.825	1.026	tINS	FR	3	R16C23[2][B]	svo_hdmi_inst/svo_tmds_0/n406_s2/F
6.248	0.423	tNET	RR	1	R16C24[1][B]	svo_hdmi_inst/svo_tmds_0/n88_s7/I3
7.347	1.099	tINS	RF	2	R16C24[1][B]	svo_hdmi_inst/svo_tmds_0/n88_s7/F
7.358	0.011	tNET	FF	1	R16C24[3][A]	svo_hdmi_inst/svo_tmds_0/n88_s3/I1
8.457	1.099	tINS	FF	1	R16C24[3][A]	svo_hdmi_inst/svo_tmds_0/n88_s3/F
8.462	0.005	tNET	FF	1	R16C24[3][B]	svo_hdmi_inst/svo_tmds_0/n88_s0/I3
9.264	0.802	tINS	FR	30	R16C24[3][B]	svo_hdmi_inst/svo_tmds_0/n88_s0/F
9.703	0.438	tNET	RR	1	R16C23[2][A]	svo_hdmi_inst/svo_tmds_0/n146_s13/I2
10.525	0.822	tINS	RF	3	R16C23[2][A]	svo_hdmi_inst/svo_tmds_0/n146_s13/F
11.338	0.813	tNET	FF	1	R15C22[3][B]	svo_hdmi_inst/svo_tmds_0/n145_s12/I2
12.370	1.032	tINS	FF	3	R15C22[3][B]	svo_hdmi_inst/svo_tmds_0/n145_s12/F
14.174	1.804	tNET	FF	1	R16C19[0][B]	svo_hdmi_inst/svo_tmds_0/n145_s11/I1
15.206	1.032	tINS	FF	3	R16C19[0][B]	svo_hdmi_inst/svo_tmds_0/n145_s11/F
15.702	0.496	tNET	FF	2	R16C21[0][B]	svo_hdmi_inst/svo_tmds_0/n180_s0/I1
16.747	1.045	tINS	FF	1	R16C21[0][B]	svo_hdmi_inst/svo_tmds_0/n180_s0/COUT
16.747	0.000	tNET	FF	2	R16C21[1][A]	svo_hdmi_inst/svo_tmds_0/n181_s0/CIN
16.804	0.057	tINS	FF	1	R16C21[1][A]	svo_hdmi_inst/svo_tmds_0/n181_s0/COUT
17.857	1.053	tNET	FF	1	R16C19[0][A]	svo_hdmi_inst/svo_tmds_0/n183_s0/I2
18.956	1.099	tINS	FF	10	R16C19[0][A]	svo_hdmi_inst/svo_tmds_0/n183_s0/F
20.126	1.170	tNET	FF	1	R15C23[2][B]	svo_hdmi_inst/svo_tmds_0/n359_s1/I3
20.928	0.802	tINS	FR	8	R15C23[2][B]	svo_hdmi_inst/svo_tmds_0/n359_s1/F
21.358	0.431	tNET	RR	1	R15C24[1][B]	svo_hdmi_inst/svo_tmds_0/n401_s0/I0
22.390	1.032	tINS	RF	1	R15C24[1][B]	svo_hdmi_inst/svo_tmds_0/n401_s0/F
22.390	0.000	tNET	FF	1	R15C24[1][B]	svo_hdmi_inst/svo_tmds_0/q_out_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
39.682	39.682					active clock edge time
39.682	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
40.255	0.242	tNET	RR	1	R15C24[1][B]	svo_hdmi_inst/svo_tmds_0/q_out_9_s0/CLK
39.855	-0.400	tSu		1	R15C24[1][B]	svo_hdmi_inst/svo_tmds_0/q_out_9_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	39.682
Logic Level	14
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 11.573, 53.043%; route: 9.787, 44.857%; tC2Q: 0.458, 2.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path25

Path Summary:

Slack	17.543
Data Arrival Time	22.312
Data Required Time	39.855
From	svo_hdmi_inst/svo_enc/out_axis_tdata_3_s0
To	svo_hdmi_inst/svo_tmds_2/q_out_4_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R8C16[1][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_3_s0/CLK
1.030	0.458	tC2Q	RF	4	R8C16[1][A]	svo_hdmi_inst/svo_enc/out_axis_tdata_3_s0/Q
2.992	1.962	tNET	FF	1	R8C28[0][A]	svo_hdmi_inst/svo_tmds_2/n146_s15/I2
3.814	0.822	tINS	FF	12	R8C28[0][A]	svo_hdmi_inst/svo_tmds_2/n146_s15/F
3.853	0.038	tNET	FF	1	R8C28[3][A]	svo_hdmi_inst/svo_tmds_2/n406_s2/I1
4.479	0.626	tINS	FF	1	R8C28[3][A]	svo_hdmi_inst/svo_tmds_2/n406_s2/F
4.484	0.005	tNET	FF	1	R8C28[2][A]	svo_hdmi_inst/svo_tmds_2/n88_s4/I3
5.306	0.822	tINS	FF	3	R8C28[2][A]	svo_hdmi_inst/svo_tmds_2/n88_s4/F
6.142	0.836	tNET	FF	1	R8C29[3][B]	svo_hdmi_inst/svo_tmds_2/n88_s2/I2
7.174	1.032	tINS	FF	8	R8C29[3][B]	svo_hdmi_inst/svo_tmds_2/n88_s2/F
8.018	0.843	tNET	FF	1	R8C30[3][A]	svo_hdmi_inst/svo_tmds_2/n407_s3/I0
9.117	1.099	tINS	FF	3	R8C30[3][A]	svo_hdmi_inst/svo_tmds_2/n407_s3/F
9.943	0.826	tNET	FF	1	R9C30[2][A]	svo_hdmi_inst/svo_tmds_2/n175_s16/I3
10.969	1.026	tINS	FR	3	R9C30[2][A]	svo_hdmi_inst/svo_tmds_2/n175_s16/F
11.394	0.425	tNET	RR	1	R9C31[0][A]	svo_hdmi_inst/svo_tmds_2/n174_s16/I1
12.020	0.626	tINS	RF	4	R9C31[0][A]	svo_hdmi_inst/svo_tmds_2/n174_s16/F
13.319	1.299	tNET	FF	1	R6C30[3][A]	svo_hdmi_inst/svo_tmds_2/n174_s15/I0
14.418	1.099	tINS	FF	3	R6C30[3][A]	svo_hdmi_inst/svo_tmds_2/n174_s15/F
15.233	0.815	tNET	FF	2	R8C31[0][B]	svo_hdmi_inst/svo_tmds_2/n180_s0/I0
16.191	0.958	tINS	FF	1	R8C31[0][B]	svo_hdmi_inst/svo_tmds_2/n180_s0/COUT
16.191	0.000	tNET	FF	2	R8C31[1][A]	svo_hdmi_inst/svo_tmds_2/n181_s0/CIN
16.248	0.057	tINS	FF	1	R8C31[1][A]	svo_hdmi_inst/svo_tmds_2/n181_s0/COUT
17.301	1.053	tNET	FF	1	R6C31[1][B]	svo_hdmi_inst/svo_tmds_2/n183_s0/I2
18.400	1.099	tINS	FF	10	R6C31[1][B]	svo_hdmi_inst/svo_tmds_2/n183_s0/F
19.255	0.855	tNET	FF	1	R8C32[3][A]	svo_hdmi_inst/svo_tmds_2/n359_s1/I3
20.354	1.099	tINS	FF	8	R8C32[3][A]	svo_hdmi_inst/svo_tmds_2/n359_s1/F
21.213	0.859	tNET	FF	1	R9C32[0][A]	svo_hdmi_inst/svo_tmds_2/n406_s3/I3
22.312	1.099	tINS	FF	1	R9C32[0][A]	svo_hdmi_inst/svo_tmds_2/n406_s3/F
22.312	0.000	tNET	FF	1	R9C32[0][A]	svo_hdmi_inst/svo_tmds_2/q_out_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
39.682	39.682					active clock edge time
39.682	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
40.255	0.242	tNET	RR	1	R9C32[0][A]	svo_hdmi_inst/svo_tmds_2/q_out_4_s0/CLK
39.855	-0.400	tSu		1	R9C32[0][A]	svo_hdmi_inst/svo_tmds_2/q_out_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	39.682
Logic Level	14
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 11.464, 52.732%; route: 9.818, 45.159%; tC2Q: 0.458, 2.108%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.417
Data Arrival Time	1.084
Data Required Time	0.667
From	svo_hdmi_inst/svo_tcard/xoff_3_s0
To	svo_hdmi_inst/svo_tcard/vdma_tdata_0_s135
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R11C7[2][A]	svo_hdmi_inst/svo_tcard/xoff_3_s0/CLK
0.846	0.333	tC2Q	RF	4	R11C7[2][A]	svo_hdmi_inst/svo_tcard/xoff_3_s0/Q
1.084	0.238	tNET	FF	1	BSRAM_R10[1]	svo_hdmi_inst/svo_tcard/vdma_tdata_0_s135/AD[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	BSRAM_R10[1]	svo_hdmi_inst/svo_tcard/vdma_tdata_0_s135/CLK
0.667	0.154	tHld		1	BSRAM_R10[1]	svo_hdmi_inst/svo_tcard/vdma_tdata_0_s135

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.238, 41.627%; tC2Q: 0.333, 58.373%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path2

Path Summary:

Slack	0.688
Data Arrival Time	1.355
Data Required Time	0.667
From	svo_hdmi_inst/svo_tcard/xoff_1_s0
To	svo_hdmi_inst/svo_tcard/vdma_tdata_0_s135
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R11C7[0][B]	svo_hdmi_inst/svo_tcard/xoff_1_s0/CLK
0.846	0.333	tC2Q	RR	6	R11C7[0][B]	svo_hdmi_inst/svo_tcard/xoff_1_s0/Q
1.355	0.509	tNET	RR	1	BSRAM_R10[1]	svo_hdmi_inst/svo_tcard/vdma_tdata_0_s135/AD[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	BSRAM_R10[1]	svo_hdmi_inst/svo_tcard/vdma_tdata_0_s135/CLK
0.667	0.154	tHld		1	BSRAM_R10[1]	svo_hdmi_inst/svo_tcard/vdma_tdata_0_s135

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.509, 60.409%; tC2Q: 0.333, 39.591%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path3

Path Summary:

Slack	0.708
Data Arrival Time	1.221
Data Required Time	0.513
From	svo_hdmi_inst/svo_enc/vcursor_13_s0
To	svo_hdmi_inst/svo_enc/vcursor_13_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R13C24[0][A]	svo_hdmi_inst/svo_enc/vcursor_13_s0/CLK
0.846	0.333	tC2Q	RR	2	R13C24[0][A]	svo_hdmi_inst/svo_enc/vcursor_13_s0/Q
0.849	0.002	tNET	RR	1	R13C24[0][A]	svo_hdmi_inst/svo_enc/n80_s2/I3
1.221	0.372	tINS	RF	1	R13C24[0][A]	svo_hdmi_inst/svo_enc/n80_s2/F
1.221	0.000	tNET	FF	1	R13C24[0][A]	svo_hdmi_inst/svo_enc/vcursor_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R13C24[0][A]	svo_hdmi_inst/svo_enc/vcursor_13_s0/CLK
0.513	0.000	tHld		1	R13C24[0][A]	svo_hdmi_inst/svo_enc/vcursor_13_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path4

Path Summary:

Slack	0.708
Data Arrival Time	1.221
Data Required Time	0.513
From	svo_hdmi_inst/svo_enc/hcursor_3_s0
To	svo_hdmi_inst/svo_enc/hcursor_3_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R7C22[0][A]	svo_hdmi_inst/svo_enc/hcursor_3_s0/CLK
0.846	0.333	tC2Q	RR	3	R7C22[0][A]	svo_hdmi_inst/svo_enc/hcursor_3_s0/Q
0.849	0.002	tNET	RR	1	R7C22[0][A]	svo_hdmi_inst/svo_enc/n119_s2/I3
1.221	0.372	tINS	RF	1	R7C22[0][A]	svo_hdmi_inst/svo_enc/n119_s2/F
1.221	0.000	tNET	FF	1	R7C22[0][A]	svo_hdmi_inst/svo_enc/hcursor_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R7C22[0][A]	svo_hdmi_inst/svo_enc/hcursor_3_s0/CLK
0.513	0.000	tHld		1	R7C22[0][A]	svo_hdmi_inst/svo_enc/hcursor_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path5

Path Summary:

Slack	0.708
Data Arrival Time	1.221
Data Required Time	0.513
From	svo_hdmi_inst/svo_enc/hcursor_11_s0
To	svo_hdmi_inst/svo_enc/hcursor_11_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R13C22[1][A]	svo_hdmi_inst/svo_enc/hcursor_11_s0/CLK
0.846	0.333	tC2Q	RR	4	R13C22[1][A]	svo_hdmi_inst/svo_enc/hcursor_11_s0/Q
0.849	0.002	tNET	RR	1	R13C22[1][A]	svo_hdmi_inst/svo_enc/n111_s2/I0
1.221	0.372	tINS	RF	1	R13C22[1][A]	svo_hdmi_inst/svo_enc/n111_s2/F
1.221	0.000	tNET	FF	1	R13C22[1][A]	svo_hdmi_inst/svo_enc/hcursor_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R13C22[1][A]	svo_hdmi_inst/svo_enc/hcursor_11_s0/CLK
0.513	0.000	tHld		1	R13C22[1][A]	svo_hdmi_inst/svo_enc/hcursor_11_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path6

Path Summary:

Slack	0.708
Data Arrival Time	1.221
Data Required Time	0.513
From	svo_hdmi_inst/svo_enc/hcursor_13_s0
To	svo_hdmi_inst/svo_enc/hcursor_13_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R13C22[0][A]	svo_hdmi_inst/svo_enc/hcursor_13_s0/CLK
0.846	0.333	tC2Q	RR	2	R13C22[0][A]	svo_hdmi_inst/svo_enc/hcursor_13_s0/Q
0.849	0.002	tNET	RR	1	R13C22[0][A]	svo_hdmi_inst/svo_enc/n109_s2/I3
1.221	0.372	tINS	RF	1	R13C22[0][A]	svo_hdmi_inst/svo_enc/n109_s2/F
1.221	0.000	tNET	FF	1	R13C22[0][A]	svo_hdmi_inst/svo_enc/hcursor_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R13C22[0][A]	svo_hdmi_inst/svo_enc/hcursor_13_s0/CLK
0.513	0.000	tHld		1	R13C22[0][A]	svo_hdmi_inst/svo_enc/hcursor_13_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path7

Path Summary:

Slack	0.708
Data Arrival Time	1.221
Data Required Time	0.513
From	svo_hdmi_inst/svo_tcard/hcursor_13_s0
To	svo_hdmi_inst/svo_tcard/hcursor_13_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R15C9[0][A]	svo_hdmi_inst/svo_tcard/hcursor_13_s0/CLK
0.846	0.333	tC2Q	RR	2	R15C9[0][A]	svo_hdmi_inst/svo_tcard/hcursor_13_s0/Q
0.849	0.002	tNET	RR	1	R15C9[0][A]	svo_hdmi_inst/svo_tcard/n1693_s2/I3
1.221	0.372	tINS	RF	1	R15C9[0][A]	svo_hdmi_inst/svo_tcard/n1693_s2/F
1.221	0.000	tNET	FF	1	R15C9[0][A]	svo_hdmi_inst/svo_tcard/hcursor_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R15C9[0][A]	svo_hdmi_inst/svo_tcard/hcursor_13_s0/CLK
0.513	0.000	tHld		1	R15C9[0][A]	svo_hdmi_inst/svo_tcard/hcursor_13_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path8

Path Summary:

Slack	0.708
Data Arrival Time	1.221
Data Required Time	0.513
From	svo_hdmi_inst/svo_tcard/b_3_s0
To	svo_hdmi_inst/svo_tcard/b_3_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R7C9[0][A]	svo_hdmi_inst/svo_tcard/b_3_s0/CLK
0.846	0.333	tC2Q	RR	2	R7C9[0][A]	svo_hdmi_inst/svo_tcard/b_3_s0/Q
0.849	0.002	tNET	RR	1	R7C9[0][A]	svo_hdmi_inst/svo_tcard/n1393_s2/I0
1.221	0.372	tINS	RF	1	R7C9[0][A]	svo_hdmi_inst/svo_tcard/n1393_s2/F
1.221	0.000	tNET	FF	1	R7C9[0][A]	svo_hdmi_inst/svo_tcard/b_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R7C9[0][A]	svo_hdmi_inst/svo_tcard/b_3_s0/CLK
0.513	0.000	tHld		1	R7C9[0][A]	svo_hdmi_inst/svo_tcard/b_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path9

Path Summary:

Slack	0.708
Data Arrival Time	1.221
Data Required Time	0.513
From	svo_hdmi_inst/svo_tcard/x_8_s0
To	svo_hdmi_inst/svo_tcard/x_8_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R13C8[0][A]	svo_hdmi_inst/svo_tcard/x_8_s0/CLK
0.846	0.333	tC2Q	RR	2	R13C8[0][A]	svo_hdmi_inst/svo_tcard/x_8_s0/Q
0.849	0.002	tNET	RR	1	R13C8[0][A]	svo_hdmi_inst/svo_tcard/n1678_s2/I3
1.221	0.372	tINS	RF	1	R13C8[0][A]	svo_hdmi_inst/svo_tcard/n1678_s2/F
1.221	0.000	tNET	FF	1	R13C8[0][A]	svo_hdmi_inst/svo_tcard/x_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R13C8[0][A]	svo_hdmi_inst/svo_tcard/x_8_s0/CLK
0.513	0.000	tHld		1	R13C8[0][A]	svo_hdmi_inst/svo_tcard/x_8_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path10

Path Summary:

Slack	0.708
Data Arrival Time	1.221
Data Required Time	0.513
From	svo_hdmi_inst/svo_tcard/vcursor_9_s0
To	svo_hdmi_inst/svo_tcard/vcursor_9_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R15C6[0][A]	svo_hdmi_inst/svo_tcard/vcursor_9_s0/CLK
0.846	0.333	tC2Q	RR	6	R15C6[0][A]	svo_hdmi_inst/svo_tcard/vcursor_9_s0/Q
0.849	0.002	tNET	RR	1	R15C6[0][A]	svo_hdmi_inst/svo_tcard/n1628_s2/I0
1.221	0.372	tINS	RF	1	R15C6[0][A]	svo_hdmi_inst/svo_tcard/n1628_s2/F
1.221	0.000	tNET	FF	1	R15C6[0][A]	svo_hdmi_inst/svo_tcard/vcursor_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R15C6[0][A]	svo_hdmi_inst/svo_tcard/vcursor_9_s0/CLK
0.513	0.000	tHld		1	R15C6[0][A]	svo_hdmi_inst/svo_tcard/vcursor_9_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path11

Path Summary:

Slack	0.708
Data Arrival Time	1.221
Data Required Time	0.513
From	svo_hdmi_inst/svo_tcard/vcursor_11_s0
To	svo_hdmi_inst/svo_tcard/vcursor_11_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R15C7[0][A]	svo_hdmi_inst/svo_tcard/vcursor_11_s0/CLK
0.846	0.333	tC2Q	RR	4	R15C7[0][A]	svo_hdmi_inst/svo_tcard/vcursor_11_s0/Q
0.849	0.002	tNET	RR	1	R15C7[0][A]	svo_hdmi_inst/svo_tcard/n1626_s4/I0
1.221	0.372	tINS	RF	1	R15C7[0][A]	svo_hdmi_inst/svo_tcard/n1626_s4/F
1.221	0.000	tNET	FF	1	R15C7[0][A]	svo_hdmi_inst/svo_tcard/vcursor_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R15C7[0][A]	svo_hdmi_inst/svo_tcard/vcursor_11_s0/CLK
0.513	0.000	tHld		1	R15C7[0][A]	svo_hdmi_inst/svo_tcard/vcursor_11_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path12

Path Summary:

Slack	0.708
Data Arrival Time	1.221
Data Required Time	0.513
From	svo_hdmi_inst/svo_tcard/hcursor_6_s0
To	svo_hdmi_inst/svo_tcard/hcursor_6_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R14C9[0][A]	svo_hdmi_inst/svo_tcard/hcursor_6_s0/CLK
0.846	0.333	tC2Q	RR	3	R14C9[0][A]	svo_hdmi_inst/svo_tcard/hcursor_6_s0/Q
0.849	0.002	tNET	RR	1	R14C9[0][A]	svo_hdmi_inst/svo_tcard/n1700_s2/I3
1.221	0.372	tINS	RF	1	R14C9[0][A]	svo_hdmi_inst/svo_tcard/n1700_s2/F
1.221	0.000	tNET	FF	1	R14C9[0][A]	svo_hdmi_inst/svo_tcard/hcursor_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R14C9[0][A]	svo_hdmi_inst/svo_tcard/hcursor_6_s0/CLK
0.513	0.000	tHld		1	R14C9[0][A]	svo_hdmi_inst/svo_tcard/hcursor_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path13

Path Summary:

Slack	0.709
Data Arrival Time	1.222
Data Required Time	0.513
From	svo_hdmi_inst/svo_enc/wait_for_fifos_1_s1
To	svo_hdmi_inst/svo_enc/wait_for_fifos_1_s1
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R8C25[1][A]	svo_hdmi_inst/svo_enc/wait_for_fifos_1_s1/CLK
0.846	0.333	tC2Q	RR	4	R8C25[1][A]	svo_hdmi_inst/svo_enc/wait_for_fifos_1_s1/Q
0.850	0.004	tNET	RR	1	R8C25[1][A]	svo_hdmi_inst/svo_enc/n408_s4/I0
1.222	0.372	tINS	RF	1	R8C25[1][A]	svo_hdmi_inst/svo_enc/n408_s4/F
1.222	0.000	tNET	FF	1	R8C25[1][A]	svo_hdmi_inst/svo_enc/wait_for_fifos_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R8C25[1][A]	svo_hdmi_inst/svo_enc/wait_for_fifos_1_s1/CLK
0.513	0.000	tHld		1	R8C25[1][A]	svo_hdmi_inst/svo_enc/wait_for_fifos_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path14

Path Summary:

Slack	0.709
Data Arrival Time	1.222
Data Required Time	0.513
From	svo_hdmi_inst/svo_enc/out_fifo_rdaddr_0_s0
To	svo_hdmi_inst/svo_enc/out_fifo_rdaddr_0_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R8C25[0][A]	svo_hdmi_inst/svo_enc/out_fifo_rdaddr_0_s0/CLK
0.846	0.333	tC2Q	RR	6	R8C25[0][A]	svo_hdmi_inst/svo_enc/out_fifo_rdaddr_0_s0/Q
0.850	0.004	tNET	RR	1	R8C25[0][A]	svo_hdmi_inst/svo_enc/n413_s5/I0
1.222	0.372	tINS	RF	1	R8C25[0][A]	svo_hdmi_inst/svo_enc/n413_s5/F
1.222	0.000	tNET	FF	1	R8C25[0][A]	svo_hdmi_inst/svo_enc/out_fifo_rdaddr_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R8C25[0][A]	svo_hdmi_inst/svo_enc/out_fifo_rdaddr_0_s0/CLK
0.513	0.000	tHld		1	R8C25[0][A]	svo_hdmi_inst/svo_enc/out_fifo_rdaddr_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path15

Path Summary:

Slack	0.709
Data Arrival Time	1.222
Data Required Time	0.513
From	svo_hdmi_inst/svo_enc/out_fifo_rdaddr_1_s0
To	svo_hdmi_inst/svo_enc/out_fifo_rdaddr_1_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R7C23[1][A]	svo_hdmi_inst/svo_enc/out_fifo_rdaddr_1_s0/CLK
0.846	0.333	tC2Q	RR	4	R7C23[1][A]	svo_hdmi_inst/svo_enc/out_fifo_rdaddr_1_s0/Q
0.850	0.004	tNET	RR	1	R7C23[1][A]	svo_hdmi_inst/svo_enc/n412_s2/I0
1.222	0.372	tINS	RF	1	R7C23[1][A]	svo_hdmi_inst/svo_enc/n412_s2/F
1.222	0.000	tNET	FF	1	R7C23[1][A]	svo_hdmi_inst/svo_enc/out_fifo_rdaddr_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R7C23[1][A]	svo_hdmi_inst/svo_enc/out_fifo_rdaddr_1_s0/CLK
0.513	0.000	tHld		1	R7C23[1][A]	svo_hdmi_inst/svo_enc/out_fifo_rdaddr_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path16

Path Summary:

Slack	0.709
Data Arrival Time	1.222
Data Required Time	0.513
From	svo_hdmi_inst/svo_enc/vcursor_7_s0
To	svo_hdmi_inst/svo_enc/vcursor_7_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R13C23[0][A]	svo_hdmi_inst/svo_enc/vcursor_7_s0/CLK
0.846	0.333	tC2Q	RR	4	R13C23[0][A]	svo_hdmi_inst/svo_enc/vcursor_7_s0/Q
0.850	0.004	tNET	RR	1	R13C23[0][A]	svo_hdmi_inst/svo_enc/n86_s2/I0
1.222	0.372	tINS	RF	1	R13C23[0][A]	svo_hdmi_inst/svo_enc/n86_s2/F
1.222	0.000	tNET	FF	1	R13C23[0][A]	svo_hdmi_inst/svo_enc/vcursor_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R13C23[0][A]	svo_hdmi_inst/svo_enc/vcursor_7_s0/CLK
0.513	0.000	tHld		1	R13C23[0][A]	svo_hdmi_inst/svo_enc/vcursor_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path17

Path Summary:

Slack	0.709
Data Arrival Time	1.222
Data Required Time	0.513
From	svo_hdmi_inst/svo_enc/vcursor_10_s0
To	svo_hdmi_inst/svo_enc/vcursor_10_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R13C25[0][A]	svo_hdmi_inst/svo_enc/vcursor_10_s0/CLK
0.846	0.333	tC2Q	RR	4	R13C25[0][A]	svo_hdmi_inst/svo_enc/vcursor_10_s0/Q
0.850	0.004	tNET	RR	1	R13C25[0][A]	svo_hdmi_inst/svo_enc/n83_s2/I3
1.222	0.372	tINS	RF	1	R13C25[0][A]	svo_hdmi_inst/svo_enc/n83_s2/F
1.222	0.000	tNET	FF	1	R13C25[0][A]	svo_hdmi_inst/svo_enc/vcursor_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R13C25[0][A]	svo_hdmi_inst/svo_enc/vcursor_10_s0/CLK
0.513	0.000	tHld		1	R13C25[0][A]	svo_hdmi_inst/svo_enc/vcursor_10_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path18

Path Summary:

Slack	0.709
Data Arrival Time	1.222
Data Required Time	0.513
From	svo_hdmi_inst/svo_enc/vcursor_11_s0
To	svo_hdmi_inst/svo_enc/vcursor_11_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R13C25[1][A]	svo_hdmi_inst/svo_enc/vcursor_11_s0/CLK
0.846	0.333	tC2Q	RR	5	R13C25[1][A]	svo_hdmi_inst/svo_enc/vcursor_11_s0/Q
0.850	0.004	tNET	RR	1	R13C25[1][A]	svo_hdmi_inst/svo_enc/n82_s2/I0
1.222	0.372	tINS	RF	1	R13C25[1][A]	svo_hdmi_inst/svo_enc/n82_s2/F
1.222	0.000	tNET	FF	1	R13C25[1][A]	svo_hdmi_inst/svo_enc/vcursor_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R13C25[1][A]	svo_hdmi_inst/svo_enc/vcursor_11_s0/CLK
0.513	0.000	tHld		1	R13C25[1][A]	svo_hdmi_inst/svo_enc/vcursor_11_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path19

Path Summary:

Slack	0.709
Data Arrival Time	1.222
Data Required Time	0.513
From	svo_hdmi_inst/svo_enc/hcursor_7_s0
To	svo_hdmi_inst/svo_enc/hcursor_7_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R11C22[0][A]	svo_hdmi_inst/svo_enc/hcursor_7_s0/CLK
0.846	0.333	tC2Q	RR	5	R11C22[0][A]	svo_hdmi_inst/svo_enc/hcursor_7_s0/Q
0.850	0.004	tNET	RR	1	R11C22[0][A]	svo_hdmi_inst/svo_enc/n115_s2/I3
1.222	0.372	tINS	RF	1	R11C22[0][A]	svo_hdmi_inst/svo_enc/n115_s2/F
1.222	0.000	tNET	FF	1	R11C22[0][A]	svo_hdmi_inst/svo_enc/hcursor_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R11C22[0][A]	svo_hdmi_inst/svo_enc/hcursor_7_s0/CLK
0.513	0.000	tHld		1	R11C22[0][A]	svo_hdmi_inst/svo_enc/hcursor_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path20

Path Summary:

Slack	0.709
Data Arrival Time	1.222
Data Required Time	0.513
From	svo_hdmi_inst/svo_tcard/hcursor_0_s1
To	svo_hdmi_inst/svo_tcard/hcursor_0_s1
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R11C10[0][A]	svo_hdmi_inst/svo_tcard/hcursor_0_s1/CLK
0.846	0.333	tC2Q	RR	6	R11C10[0][A]	svo_hdmi_inst/svo_tcard/hcursor_0_s1/Q
0.850	0.004	tNET	RR	1	R11C10[0][A]	svo_hdmi_inst/svo_tcard/n1706_s5/I2
1.222	0.372	tINS	RF	1	R11C10[0][A]	svo_hdmi_inst/svo_tcard/n1706_s5/F
1.222	0.000	tNET	FF	1	R11C10[0][A]	svo_hdmi_inst/svo_tcard/hcursor_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R11C10[0][A]	svo_hdmi_inst/svo_tcard/hcursor_0_s1/CLK
0.513	0.000	tHld		1	R11C10[0][A]	svo_hdmi_inst/svo_tcard/hcursor_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path21

Path Summary:

Slack	0.709
Data Arrival Time	1.222
Data Required Time	0.513
From	svo_hdmi_inst/svo_tcard/rng_26_s0
To	svo_hdmi_inst/svo_tcard/rng_26_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R6C7[1][A]	svo_hdmi_inst/svo_tcard/rng_26_s0/CLK
0.846	0.333	tC2Q	RR	3	R6C7[1][A]	svo_hdmi_inst/svo_tcard/rng_26_s0/Q
0.850	0.004	tNET	RR	1	R6C7[1][A]	svo_hdmi_inst/svo_tcard/n1124_s0/I2
1.222	0.372	tINS	RF	1	R6C7[1][A]	svo_hdmi_inst/svo_tcard/n1124_s0/F
1.222	0.000	tNET	FF	1	R6C7[1][A]	svo_hdmi_inst/svo_tcard/rng_26_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R6C7[1][A]	svo_hdmi_inst/svo_tcard/rng_26_s0/CLK
0.513	0.000	tHld		1	R6C7[1][A]	svo_hdmi_inst/svo_tcard/rng_26_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path22

Path Summary:

Slack	0.709
Data Arrival Time	1.222
Data Required Time	0.513
From	svo_hdmi_inst/svo_tcard/yoff_0_s0
To	svo_hdmi_inst/svo_tcard/yoff_0_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R12C12[0][A]	svo_hdmi_inst/svo_tcard/yoff_0_s0/CLK
0.846	0.333	tC2Q	RR	6	R12C12[0][A]	svo_hdmi_inst/svo_tcard/yoff_0_s0/Q
0.850	0.004	tNET	RR	1	R12C12[0][A]	svo_hdmi_inst/svo_tcard/n1651_s3/I0
1.222	0.372	tINS	RF	1	R12C12[0][A]	svo_hdmi_inst/svo_tcard/n1651_s3/F
1.222	0.000	tNET	FF	1	R12C12[0][A]	svo_hdmi_inst/svo_tcard/yoff_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R12C12[0][A]	svo_hdmi_inst/svo_tcard/yoff_0_s0/CLK
0.513	0.000	tHld		1	R12C12[0][A]	svo_hdmi_inst/svo_tcard/yoff_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path23

Path Summary:

Slack	0.709
Data Arrival Time	1.222
Data Required Time	0.513
From	svo_hdmi_inst/svo_tcard/yoff_3_s0
To	svo_hdmi_inst/svo_tcard/yoff_3_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R11C12[1][A]	svo_hdmi_inst/svo_tcard/yoff_3_s0/CLK
0.846	0.333	tC2Q	RR	3	R11C12[1][A]	svo_hdmi_inst/svo_tcard/yoff_3_s0/Q
0.850	0.004	tNET	RR	1	R11C12[1][A]	svo_hdmi_inst/svo_tcard/n1648_s2/I1
1.222	0.372	tINS	RF	1	R11C12[1][A]	svo_hdmi_inst/svo_tcard/n1648_s2/F
1.222	0.000	tNET	FF	1	R11C12[1][A]	svo_hdmi_inst/svo_tcard/yoff_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R11C12[1][A]	svo_hdmi_inst/svo_tcard/yoff_3_s0/CLK
0.513	0.000	tHld		1	R11C12[1][A]	svo_hdmi_inst/svo_tcard/yoff_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path24

Path Summary:

Slack	0.709
Data Arrival Time	1.222
Data Required Time	0.513
From	svo_hdmi_inst/svo_tcard/x_3_s0
To	svo_hdmi_inst/svo_tcard/x_3_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R14C7[0][A]	svo_hdmi_inst/svo_tcard/x_3_s0/CLK
0.846	0.333	tC2Q	RR	6	R14C7[0][A]	svo_hdmi_inst/svo_tcard/x_3_s0/Q
0.850	0.004	tNET	RR	1	R14C7[0][A]	svo_hdmi_inst/svo_tcard/n1683_s2/I3
1.222	0.372	tINS	RF	1	R14C7[0][A]	svo_hdmi_inst/svo_tcard/n1683_s2/F
1.222	0.000	tNET	FF	1	R14C7[0][A]	svo_hdmi_inst/svo_tcard/x_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R14C7[0][A]	svo_hdmi_inst/svo_tcard/x_3_s0/CLK
0.513	0.000	tHld		1	R14C7[0][A]	svo_hdmi_inst/svo_tcard/x_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path25

Path Summary:

Slack	0.709
Data Arrival Time	1.222
Data Required Time	0.513
From	svo_hdmi_inst/svo_tcard/x_5_s0
To	svo_hdmi_inst/svo_tcard/x_5_s0
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R12C7[1][A]	svo_hdmi_inst/svo_tcard/x_5_s0/CLK
0.846	0.333	tC2Q	RR	4	R12C7[1][A]	svo_hdmi_inst/svo_tcard/x_5_s0/Q
0.850	0.004	tNET	RR	1	R12C7[1][A]	svo_hdmi_inst/svo_tcard/n1681_s2/I3
1.222	0.372	tINS	RF	1	R12C7[1][A]	svo_hdmi_inst/svo_tcard/n1681_s2/F
1.222	0.000	tNET	FF	1	R12C7[1][A]	svo_hdmi_inst/svo_tcard/x_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R12C7[1][A]	svo_hdmi_inst/svo_tcard/x_5_s0/CLK
0.513	0.000	tHld		1	R12C7[1][A]	svo_hdmi_inst/svo_tcard/x_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.384
Data Arrival Time	5.904
Data Required Time	6.288
From	svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To	svo_hdmi_inst/tmds_serdes[2]
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R11C19[2][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
1.030	0.458	tC2Q	RF	4	R11C19[2][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
2.491	1.460	tNET	FF	1	R8C23[3][B]	svo_hdmi_inst/n107_s1/I1
3.590	1.099	tINS	FF	101	R8C23[3][B]	svo_hdmi_inst/n107_s1/F
5.904	2.314	tNET	FF	1	IOR2[A]	svo_hdmi_inst/tmds_serdes[2]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
3.968	3.968					active clock edge time
3.968	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
6.241	2.273	tCL	FF	4	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
6.363	0.121	tNET	FF	1	IOR2[A]	svo_hdmi_inst/tmds_serdes[2]/FCLK
6.333	-0.030	tUnc				svo_hdmi_inst/tmds_serdes[2]
6.288	-0.045	tSu		1	IOR2[A]	svo_hdmi_inst/tmds_serdes[2]

Path Statistics:

Clock Skew	1.823
Setup Relationship	3.968
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 1.099, 20.611%; route: 3.775, 70.793%; tC2Q: 0.458, 8.596%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.121, 100.000%

Path2

Path Summary:

Slack	0.384
Data Arrival Time	5.904
Data Required Time	6.288
From	svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To	svo_hdmi_inst/tmds_serdes[1]
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R11C19[2][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
1.030	0.458	tC2Q	RF	4	R11C19[2][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
2.491	1.460	tNET	FF	1	R8C23[3][B]	svo_hdmi_inst/n107_s1/I1
3.590	1.099	tINS	FF	101	R8C23[3][B]	svo_hdmi_inst/n107_s1/F
5.904	2.314	tNET	FF	1	IOR11[A]	svo_hdmi_inst/tmds_serdes[1]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
3.968	3.968					active clock edge time
3.968	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
6.241	2.273	tCL	FF	4	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
6.363	0.121	tNET	FF	1	IOR11[A]	svo_hdmi_inst/tmds_serdes[1]/FCLK
6.333	-0.030	tUnc				svo_hdmi_inst/tmds_serdes[1]
6.288	-0.045	tSu		1	IOR11[A]	svo_hdmi_inst/tmds_serdes[1]

Path Statistics:

Clock Skew	1.823
Setup Relationship	3.968
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 1.099, 20.611%; route: 3.775, 70.793%; tC2Q: 0.458, 8.596%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.121, 100.000%

Path3

Path Summary:

Slack	0.384
Data Arrival Time	5.904
Data Required Time	6.288
From	svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To	svo_hdmi_inst/tmds_serdes[0]
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R11C19[2][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
1.030	0.458	tC2Q	RF	4	R11C19[2][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
2.491	1.460	tNET	FF	1	R8C23[3][B]	svo_hdmi_inst/n107_s1/I1
3.590	1.099	tINS	FF	101	R8C23[3][B]	svo_hdmi_inst/n107_s1/F
5.904	2.314	tNET	FF	1	IOR15[A]	svo_hdmi_inst/tmds_serdes[0]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
3.968	3.968					active clock edge time
3.968	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
6.241	2.273	tCL	FF	4	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
6.363	0.121	tNET	FF	1	IOR15[A]	svo_hdmi_inst/tmds_serdes[0]/FCLK
6.333	-0.030	tUnc				svo_hdmi_inst/tmds_serdes[0]
6.288	-0.045	tSu		1	IOR15[A]	svo_hdmi_inst/tmds_serdes[0]

Path Statistics:

Clock Skew	1.823
Setup Relationship	3.968
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 1.099, 20.611%; route: 3.775, 70.793%; tC2Q: 0.458, 8.596%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.121, 100.000%

Path4

Path Summary:

Slack	4.345
Data Arrival Time	5.904
Data Required Time	10.250
From	svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To	svo_hdmi_inst/tmds_serdes[0]
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R11C19[2][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
1.030	0.458	tC2Q	RF	4	R11C19[2][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
2.491	1.460	tNET	FF	1	R8C23[3][B]	svo_hdmi_inst/n107_s1/I1
3.590	1.099	tINS	FF	101	R8C23[3][B]	svo_hdmi_inst/n107_s1/F
5.904	2.314	tNET	FF	1	IOR15[A]	svo_hdmi_inst/tmds_serdes[0]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.936	7.936					active clock edge time
7.936	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
10.210	2.273	tCL	RR	4	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
10.325	0.115	tNET	RR	1	IOR15[A]	svo_hdmi_inst/tmds_serdes[0]/FCLK
10.295	-0.030	tUnc				svo_hdmi_inst/tmds_serdes[0]
10.250	-0.045	tSu		1	IOR15[A]	svo_hdmi_inst/tmds_serdes[0]

Path Statistics:

Clock Skew	1.816
Setup Relationship	7.936
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 1.099, 20.611%; route: 3.775, 70.793%; tC2Q: 0.458, 8.596%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.115, 100.000%

Path5

Path Summary:

Slack	4.345
Data Arrival Time	5.904
Data Required Time	10.250
From	svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To	svo_hdmi_inst/tmds_serdes[1]
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R11C19[2][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
1.030	0.458	tC2Q	RF	4	R11C19[2][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
2.491	1.460	tNET	FF	1	R8C23[3][B]	svo_hdmi_inst/n107_s1/I1
3.590	1.099	tINS	FF	101	R8C23[3][B]	svo_hdmi_inst/n107_s1/F
5.904	2.314	tNET	FF	1	IOR11[A]	svo_hdmi_inst/tmds_serdes[1]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.936	7.936					active clock edge time
7.936	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
10.210	2.273	tCL	RR	4	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
10.325	0.115	tNET	RR	1	IOR11[A]	svo_hdmi_inst/tmds_serdes[1]/FCLK
10.295	-0.030	tUnc				svo_hdmi_inst/tmds_serdes[1]
10.250	-0.045	tSu		1	IOR11[A]	svo_hdmi_inst/tmds_serdes[1]

Path Statistics:

Clock Skew	1.816
Setup Relationship	7.936
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 1.099, 20.611%; route: 3.775, 70.793%; tC2Q: 0.458, 8.596%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.115, 100.000%

Path6

Path Summary:

Slack	4.345
Data Arrival Time	5.904
Data Required Time	10.250
From	svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To	svo_hdmi_inst/tmds_serdes[2]
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R11C19[2][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
1.030	0.458	tC2Q	RF	4	R11C19[2][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
2.491	1.460	tNET	FF	1	R8C23[3][B]	svo_hdmi_inst/n107_s1/I1
3.590	1.099	tINS	FF	101	R8C23[3][B]	svo_hdmi_inst/n107_s1/F
5.904	2.314	tNET	FF	1	IOR2[A]	svo_hdmi_inst/tmds_serdes[2]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
7.936	7.936					active clock edge time
7.936	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
10.210	2.273	tCL	RR	4	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
10.325	0.115	tNET	RR	1	IOR2[A]	svo_hdmi_inst/tmds_serdes[2]/FCLK
10.295	-0.030	tUnc				svo_hdmi_inst/tmds_serdes[2]
10.250	-0.045	tSu		1	IOR2[A]	svo_hdmi_inst/tmds_serdes[2]

Path Statistics:

Clock Skew	1.816
Setup Relationship	7.936
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 1.099, 20.611%; route: 3.775, 70.793%; tC2Q: 0.458, 8.596%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.115, 100.000%

Path7

Path Summary:

Slack	34.305
Data Arrival Time	5.904
Data Required Time	40.210
From	svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To	svo_hdmi_inst/tmds_serdes[0]
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R11C19[2][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
1.030	0.458	tC2Q	RF	4	R11C19[2][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
2.491	1.460	tNET	FF	1	R8C23[3][B]	svo_hdmi_inst/n107_s1/I1
3.590	1.099	tINS	FF	101	R8C23[3][B]	svo_hdmi_inst/n107_s1/F
5.904	2.314	tNET	FF	1	IOR15[A]	svo_hdmi_inst/tmds_serdes[0]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
39.682	39.682					active clock edge time
39.682	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
40.255	0.242	tNET	RR	1	IOR15[A]	svo_hdmi_inst/tmds_serdes[0]/PCLK
40.210	-0.045	tSu		1	IOR15[A]	svo_hdmi_inst/tmds_serdes[0]

Path Statistics:

Clock Skew	0.000
Setup Relationship	39.682
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 1.099, 20.611%; route: 3.775, 70.793%; tC2Q: 0.458, 8.596%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path8

Path Summary:

Slack	34.305
Data Arrival Time	5.904
Data Required Time	40.210
From	svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To	svo_hdmi_inst/tmds_serdes[1]
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R11C19[2][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
1.030	0.458	tC2Q	RF	4	R11C19[2][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
2.491	1.460	tNET	FF	1	R8C23[3][B]	svo_hdmi_inst/n107_s1/I1
3.590	1.099	tINS	FF	101	R8C23[3][B]	svo_hdmi_inst/n107_s1/F
5.904	2.314	tNET	FF	1	IOR11[A]	svo_hdmi_inst/tmds_serdes[1]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
39.682	39.682					active clock edge time
39.682	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
40.255	0.242	tNET	RR	1	IOR11[A]	svo_hdmi_inst/tmds_serdes[1]/PCLK
40.210	-0.045	tSu		1	IOR11[A]	svo_hdmi_inst/tmds_serdes[1]

Path Statistics:

Clock Skew	0.000
Setup Relationship	39.682
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 1.099, 20.611%; route: 3.775, 70.793%; tC2Q: 0.458, 8.596%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path9

Path Summary:

Slack	34.305
Data Arrival Time	5.904
Data Required Time	40.210
From	svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To	svo_hdmi_inst/tmds_serdes[2]
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.572	0.242	tNET	RR	1	R11C19[2][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
1.030	0.458	tC2Q	RF	4	R11C19[2][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
2.491	1.460	tNET	FF	1	R8C23[3][B]	svo_hdmi_inst/n107_s1/I1
3.590	1.099	tINS	FF	101	R8C23[3][B]	svo_hdmi_inst/n107_s1/F
5.904	2.314	tNET	FF	1	IOR2[A]	svo_hdmi_inst/tmds_serdes[2]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
39.682	39.682					active clock edge time
39.682	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
40.255	0.242	tNET	RR	1	IOR2[A]	svo_hdmi_inst/tmds_serdes[2]/PCLK
40.210	-0.045	tSu		1	IOR2[A]	svo_hdmi_inst/tmds_serdes[2]

Path Statistics:

Clock Skew	0.000
Setup Relationship	39.682
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 1.099, 20.611%; route: 3.775, 70.793%; tC2Q: 0.458, 8.596%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.500
Data Arrival Time	3.900
Data Required Time	2.400
From	svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To	svo_hdmi_inst/tmds_serdes[0]
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R11C19[2][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
0.846	0.333	tC2Q	RR	4	R11C19[2][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
1.702	0.856	tNET	RR	1	R8C23[3][B]	svo_hdmi_inst/n107_s1/I1
2.426	0.724	tINS	RR	101	R8C23[3][B]	svo_hdmi_inst/n107_s1/F
3.900	1.474	tNET	RR	1	IOR15[A]	svo_hdmi_inst/tmds_serdes[0]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	4	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.358	0.085	tNET	RR	1	IOR15[A]	svo_hdmi_inst/tmds_serdes[0]/FCLK
2.388	0.030	tUnc				svo_hdmi_inst/tmds_serdes[0]
2.400	0.012	tHld		1	IOR15[A]	svo_hdmi_inst/tmds_serdes[0]

Path Statistics:

Clock Skew	1.845
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.724, 21.375%; route: 2.330, 68.784%; tC2Q: 0.333, 9.841%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.085, 100.000%

Path2

Path Summary:

Slack	1.500
Data Arrival Time	3.900
Data Required Time	2.400
From	svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To	svo_hdmi_inst/tmds_serdes[1]
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R11C19[2][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
0.846	0.333	tC2Q	RR	4	R11C19[2][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
1.702	0.856	tNET	RR	1	R8C23[3][B]	svo_hdmi_inst/n107_s1/I1
2.426	0.724	tINS	RR	101	R8C23[3][B]	svo_hdmi_inst/n107_s1/F
3.900	1.474	tNET	RR	1	IOR11[A]	svo_hdmi_inst/tmds_serdes[1]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	4	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.358	0.085	tNET	RR	1	IOR11[A]	svo_hdmi_inst/tmds_serdes[1]/FCLK
2.388	0.030	tUnc				svo_hdmi_inst/tmds_serdes[1]
2.400	0.012	tHld		1	IOR11[A]	svo_hdmi_inst/tmds_serdes[1]

Path Statistics:

Clock Skew	1.845
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.724, 21.375%; route: 2.330, 68.784%; tC2Q: 0.333, 9.841%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.085, 100.000%

Path3

Path Summary:

Slack	1.500
Data Arrival Time	3.900
Data Required Time	2.400
From	svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To	svo_hdmi_inst/tmds_serdes[2]
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R11C19[2][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
0.846	0.333	tC2Q	RR	4	R11C19[2][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
1.702	0.856	tNET	RR	1	R8C23[3][B]	svo_hdmi_inst/n107_s1/I1
2.426	0.724	tINS	RR	101	R8C23[3][B]	svo_hdmi_inst/n107_s1/F
3.900	1.474	tNET	RR	1	IOR2[A]	svo_hdmi_inst/tmds_serdes[2]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	4	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
2.358	0.085	tNET	RR	1	IOR2[A]	svo_hdmi_inst/tmds_serdes[2]/FCLK
2.388	0.030	tUnc				svo_hdmi_inst/tmds_serdes[2]
2.400	0.012	tHld		1	IOR2[A]	svo_hdmi_inst/tmds_serdes[2]

Path Statistics:

Clock Skew	1.845
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.724, 21.375%; route: 2.330, 68.784%; tC2Q: 0.333, 9.841%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.085, 100.000%

Path4

Path Summary:

Slack	3.375
Data Arrival Time	3.900
Data Required Time	0.526
From	svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To	svo_hdmi_inst/tmds_serdes[2]
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R11C19[2][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
0.846	0.333	tC2Q	RR	4	R11C19[2][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
1.702	0.856	tNET	RR	1	R8C23[3][B]	svo_hdmi_inst/n107_s1/I1
2.426	0.724	tINS	RR	101	R8C23[3][B]	svo_hdmi_inst/n107_s1/F
3.900	1.474	tNET	RR	1	IOR2[A]	svo_hdmi_inst/tmds_serdes[2]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	IOR2[A]	svo_hdmi_inst/tmds_serdes[2]/PCLK
0.526	0.012	tHld		1	IOR2[A]	svo_hdmi_inst/tmds_serdes[2]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.724, 21.375%; route: 2.330, 68.784%; tC2Q: 0.333, 9.841%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path5

Path Summary:

Slack	3.375
Data Arrival Time	3.900
Data Required Time	0.526
From	svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To	svo_hdmi_inst/tmds_serdes[1]
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R11C19[2][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
0.846	0.333	tC2Q	RR	4	R11C19[2][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
1.702	0.856	tNET	RR	1	R8C23[3][B]	svo_hdmi_inst/n107_s1/I1
2.426	0.724	tINS	RR	101	R8C23[3][B]	svo_hdmi_inst/n107_s1/F
3.900	1.474	tNET	RR	1	IOR11[A]	svo_hdmi_inst/tmds_serdes[1]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	IOR11[A]	svo_hdmi_inst/tmds_serdes[1]/PCLK
0.526	0.012	tHld		1	IOR11[A]	svo_hdmi_inst/tmds_serdes[1]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.724, 21.375%; route: 2.330, 68.784%; tC2Q: 0.333, 9.841%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path6

Path Summary:

Slack	3.375
Data Arrival Time	3.900
Data Required Time	0.526
From	svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To	svo_hdmi_inst/tmds_serdes[0]
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R11C19[2][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
0.846	0.333	tC2Q	RR	4	R11C19[2][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
1.702	0.856	tNET	RR	1	R8C23[3][B]	svo_hdmi_inst/n107_s1/I1
2.426	0.724	tINS	RR	101	R8C23[3][B]	svo_hdmi_inst/n107_s1/F
3.900	1.474	tNET	RR	1	IOR15[A]	svo_hdmi_inst/tmds_serdes[0]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	IOR15[A]	svo_hdmi_inst/tmds_serdes[0]/PCLK
0.526	0.012	tHld		1	IOR15[A]	svo_hdmi_inst/tmds_serdes[0]

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.724, 21.375%; route: 2.330, 68.784%; tC2Q: 0.333, 9.841%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path7

Path Summary:

Slack	5.463
Data Arrival Time	3.900
Data Required Time	-1.562
From	svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To	svo_hdmi_inst/tmds_serdes[2]
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R11C19[2][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
0.846	0.333	tC2Q	RR	4	R11C19[2][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
1.702	0.856	tNET	RR	1	R8C23[3][B]	svo_hdmi_inst/n107_s1/I1
2.426	0.724	tINS	RR	101	R8C23[3][B]	svo_hdmi_inst/n107_s1/F
3.900	1.474	tNET	RR	1	IOR2[A]	svo_hdmi_inst/tmds_serdes[2]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-3.968	-3.968					active clock edge time
-3.968	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
-1.695	2.273	tCL	FF	4	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
-1.605	0.090	tNET	FF	1	IOR2[A]	svo_hdmi_inst/tmds_serdes[2]/FCLK
-1.575	0.030	tUnc				svo_hdmi_inst/tmds_serdes[2]
-1.562	0.012	tHld		1	IOR2[A]	svo_hdmi_inst/tmds_serdes[2]

Path Statistics:

Clock Skew	1.850
Hold Relationship	-3.968
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.724, 21.375%; route: 2.330, 68.784%; tC2Q: 0.333, 9.841%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.090, 100.000%

Path8

Path Summary:

Slack	5.463
Data Arrival Time	3.900
Data Required Time	-1.562
From	svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To	svo_hdmi_inst/tmds_serdes[1]
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R11C19[2][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
0.846	0.333	tC2Q	RR	4	R11C19[2][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
1.702	0.856	tNET	RR	1	R8C23[3][B]	svo_hdmi_inst/n107_s1/I1
2.426	0.724	tINS	RR	101	R8C23[3][B]	svo_hdmi_inst/n107_s1/F
3.900	1.474	tNET	RR	1	IOR11[A]	svo_hdmi_inst/tmds_serdes[1]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-3.968	-3.968					active clock edge time
-3.968	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
-1.695	2.273	tCL	FF	4	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
-1.605	0.090	tNET	FF	1	IOR11[A]	svo_hdmi_inst/tmds_serdes[1]/FCLK
-1.575	0.030	tUnc				svo_hdmi_inst/tmds_serdes[1]
-1.562	0.012	tHld		1	IOR11[A]	svo_hdmi_inst/tmds_serdes[1]

Path Statistics:

Clock Skew	1.850
Hold Relationship	-3.968
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.724, 21.375%; route: 2.330, 68.784%; tC2Q: 0.333, 9.841%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.090, 100.000%

Path9

Path Summary:

Slack	5.463
Data Arrival Time	3.900
Data Required Time	-1.562
From	svo_hdmi_inst/resetn_clk_pixel_q_3_s0
To	svo_hdmi_inst/tmds_serdes[0]
Launch Clk	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	639	RIGHTSIDE[1]	u_div_5/clkdiv_inst/CLKOUT
0.513	0.183	tNET	RR	1	R11C19[2][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/CLK
0.846	0.333	tC2Q	RR	4	R11C19[2][A]	svo_hdmi_inst/resetn_clk_pixel_q_3_s0/Q
1.702	0.856	tNET	RR	1	R8C23[3][B]	svo_hdmi_inst/n107_s1/I1
2.426	0.724	tINS	RR	101	R8C23[3][B]	svo_hdmi_inst/n107_s1/F
3.900	1.474	tNET	RR	1	IOR15[A]	svo_hdmi_inst/tmds_serdes[0]/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
-3.968	-3.968					active clock edge time
-3.968	0.000					Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
-1.695	2.273	tCL	FF	4	PLL_L	Gowin_PLLVR_inst/pllvr_inst/CLKOUT
-1.605	0.090	tNET	FF	1	IOR15[A]	svo_hdmi_inst/tmds_serdes[0]/FCLK
-1.575	0.030	tUnc				svo_hdmi_inst/tmds_serdes[0]
-1.562	0.012	tHld		1	IOR15[A]	svo_hdmi_inst/tmds_serdes[0]

Path Statistics:

Clock Skew	1.850
Hold Relationship	-3.968
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.724, 21.375%; route: 2.330, 68.784%; tC2Q: 0.333, 9.841%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.090, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	18.517
Actual Width:	19.767
Required Width:	1.250
Type:	Low Pulse Width
Clock:	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
Objects:	u_Reset_Sync/reset_cnt_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
19.841	0.000			active clock edge time
19.841	0.000			u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
20.171	0.330	tCL	FF	u_div_5/clkdiv_inst/CLKOUT
20.428	0.257	tNET	FF	u_Reset_Sync/reset_cnt_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
39.682	0.000			active clock edge time
39.682	0.000			u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	u_div_5/clkdiv_inst/CLKOUT
40.196	0.183	tNET	RR	u_Reset_Sync/reset_cnt_2_s0/CLK

MPW2

MPW Summary:

Slack:	18.517
Actual Width:	19.767
Required Width:	1.250
Type:	Low Pulse Width
Clock:	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
Objects:	u_Reset_Sync/reset_cnt_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
19.841	0.000			active clock edge time
19.841	0.000			u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
20.171	0.330	tCL	FF	u_div_5/clkdiv_inst/CLKOUT
20.428	0.257	tNET	FF	u_Reset_Sync/reset_cnt_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
39.682	0.000			active clock edge time
39.682	0.000			u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	u_div_5/clkdiv_inst/CLKOUT
40.196	0.183	tNET	RR	u_Reset_Sync/reset_cnt_0_s0/CLK

MPW3

MPW Summary:

Slack:	18.517
Actual Width:	19.767
Required Width:	1.250
Type:	Low Pulse Width
Clock:	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
Objects:	svo_hdmi_inst/resetn_clk_pixel_q_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
19.841	0.000			active clock edge time
19.841	0.000			u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
20.171	0.330	tCL	FF	u_div_5/clkdiv_inst/CLKOUT
20.428	0.257	tNET	FF	svo_hdmi_inst/resetn_clk_pixel_q_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
39.682	0.000			active clock edge time
39.682	0.000			u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	u_div_5/clkdiv_inst/CLKOUT
40.196	0.183	tNET	RR	svo_hdmi_inst/resetn_clk_pixel_q_1_s0/CLK

MPW4

MPW Summary:

Slack:	18.517
Actual Width:	19.767
Required Width:	1.250
Type:	Low Pulse Width
Clock:	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
Objects:	svo_hdmi_inst/svo_tcard/hcursor_5_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
19.841	0.000			active clock edge time
19.841	0.000			u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
20.171	0.330	tCL	FF	u_div_5/clkdiv_inst/CLKOUT
20.428	0.257	tNET	FF	svo_hdmi_inst/svo_tcard/hcursor_5_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
39.682	0.000			active clock edge time
39.682	0.000			u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	u_div_5/clkdiv_inst/CLKOUT
40.196	0.183	tNET	RR	svo_hdmi_inst/svo_tcard/hcursor_5_s0/CLK

MPW5

MPW Summary:

Slack:	18.517
Actual Width:	19.767
Required Width:	1.250
Type:	Low Pulse Width
Clock:	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
Objects:	svo_hdmi_inst/svo_tcard/vcursor_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
19.841	0.000			active clock edge time
19.841	0.000			u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
20.171	0.330	tCL	FF	u_div_5/clkdiv_inst/CLKOUT
20.428	0.257	tNET	FF	svo_hdmi_inst/svo_tcard/vcursor_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
39.682	0.000			active clock edge time
39.682	0.000			u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	u_div_5/clkdiv_inst/CLKOUT
40.196	0.183	tNET	RR	svo_hdmi_inst/svo_tcard/vcursor_0_s0/CLK

MPW6

MPW Summary:

Slack:	18.517
Actual Width:	19.767
Required Width:	1.250
Type:	Low Pulse Width
Clock:	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
Objects:	svo_hdmi_inst/svo_tcard/rng_30_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
19.841	0.000			active clock edge time
19.841	0.000			u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
20.171	0.330	tCL	FF	u_div_5/clkdiv_inst/CLKOUT
20.428	0.257	tNET	FF	svo_hdmi_inst/svo_tcard/rng_30_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
39.682	0.000			active clock edge time
39.682	0.000			u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	u_div_5/clkdiv_inst/CLKOUT
40.196	0.183	tNET	RR	svo_hdmi_inst/svo_tcard/rng_30_s0/CLK

MPW7

MPW Summary:

Slack:	18.517
Actual Width:	19.767
Required Width:	1.250
Type:	Low Pulse Width
Clock:	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
Objects:	svo_hdmi_inst/svo_tcard/vdma_tdata_0_s232

Late clock Path:

AT	DELAY	TYPE	RF	NODE
19.841	0.000			active clock edge time
19.841	0.000			u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
20.171	0.330	tCL	FF	u_div_5/clkdiv_inst/CLKOUT
20.428	0.257	tNET	FF	svo_hdmi_inst/svo_tcard/vdma_tdata_0_s232/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
39.682	0.000			active clock edge time
39.682	0.000			u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	u_div_5/clkdiv_inst/CLKOUT
40.196	0.183	tNET	RR	svo_hdmi_inst/svo_tcard/vdma_tdata_0_s232/CLK

MPW8

MPW Summary:

Slack:	18.517
Actual Width:	19.767
Required Width:	1.250
Type:	Low Pulse Width
Clock:	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
Objects:	svo_hdmi_inst/svo_enc/pixel_fifo_pixel_fifo_RAMREG_1_G[2]_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
19.841	0.000			active clock edge time
19.841	0.000			u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
20.171	0.330	tCL	FF	u_div_5/clkdiv_inst/CLKOUT
20.428	0.257	tNET	FF	svo_hdmi_inst/svo_enc/pixel_fifo_pixel_fifo_RAMREG_1_G[2]_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
39.682	0.000			active clock edge time
39.682	0.000			u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	u_div_5/clkdiv_inst/CLKOUT
40.196	0.183	tNET	RR	svo_hdmi_inst/svo_enc/pixel_fifo_pixel_fifo_RAMREG_1_G[2]_s1/CLK

MPW9

MPW Summary:

Slack:	18.517
Actual Width:	19.767
Required Width:	1.250
Type:	Low Pulse Width
Clock:	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
Objects:	svo_hdmi_inst/svo_enc/out_fifo_out_fifo_RAMREG_3_G[22]_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
19.841	0.000			active clock edge time
19.841	0.000			u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
20.171	0.330	tCL	FF	u_div_5/clkdiv_inst/CLKOUT
20.428	0.257	tNET	FF	svo_hdmi_inst/svo_enc/out_fifo_out_fifo_RAMREG_3_G[22]_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
39.682	0.000			active clock edge time
39.682	0.000			u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	u_div_5/clkdiv_inst/CLKOUT
40.196	0.183	tNET	RR	svo_hdmi_inst/svo_enc/out_fifo_out_fifo_RAMREG_3_G[22]_s0/CLK

MPW10

MPW Summary:

Slack:	18.517
Actual Width:	19.767
Required Width:	1.250
Type:	Low Pulse Width
Clock:	u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
Objects:	svo_hdmi_inst/svo_enc/out_fifo_out_fifo_RAMREG_3_G[21]_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
19.841	0.000			active clock edge time
19.841	0.000			u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
20.171	0.330	tCL	FF	u_div_5/clkdiv_inst/CLKOUT
20.428	0.257	tNET	FF	svo_hdmi_inst/svo_enc/out_fifo_out_fifo_RAMREG_3_G[21]_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
39.682	0.000			active clock edge time
39.682	0.000			u_div_5/clkdiv_inst/CLKOUT.default_gen_clk
40.013	0.330	tCL	RR	u_div_5/clkdiv_inst/CLKOUT
40.196	0.183	tNET	RR	svo_hdmi_inst/svo_enc/out_fifo_out_fifo_RAMREG_3_G[21]_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
639	clk_p	0.384	0.659
101	n107_5	0.384	2.799
97	pixel_fifo_rdaddr[2]	27.837	2.836
59	n1888_6	35.015	1.959
52	pixel_fifo_rdaddr[1]	27.810	2.185
51	n414_3	32.319	3.296
47	n2519_5	33.821	2.152
43	vdma_tdata_0_141	32.139	3.270
40	n1088_5	20.970	2.119
31	video_enc_tuser[3]	33.040	2.946

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R13C7	84.72%
R9C24	83.33%
R8C32	83.33%
R9C23	81.94%
R6C17	81.94%
R13C14	81.94%
R6C27	79.17%
R12C8	79.17%
R13C12	79.17%
R8C16	76.39%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name clk_osc -period 37.037 -waveform {0 18.518} [get_ports {clk}]