Pin Messages

Report Title Pin Report
Design File /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/hdmi_720p/impl/gwsynthesis/hdmi.vg
Physical Constraints File /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/hdmi_720p/src/hdmi.cst
Timing Constraints File /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/hdmi_720p/src/hdmi.sdc
Tool Version V1.9.11
Part Number GW1NSR-LV4CQN48PC6/I5
Device GW1NSR-4C
Created Time Tue Apr 8 14:17:08 2025
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Pin Details

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site CFG IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor BankVccio
clk - 45/1 Y in IOT13[A] LPLL_T_in LVCMOS33 NA UP ON NONE NA NA NA NA 1.2
resetn - 14/3 Y in IOB4[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
tmds_clk_p tmds_clk_n 28,27/2 Y out IOR17 - LVCMOS33D 8 NONE NA NA NA NA OFF NA 3.3
tmds_d_p[0] tmds_d_n[0] 30,29/2 Y out IOR15 - LVCMOS33D 8 NONE NA NA NA NA OFF NA 3.3
tmds_d_p[1] tmds_d_n[1] 32,31/2 Y out IOR11 GCLKT_3 LVCMOS33D 8 NONE NA NA NA NA OFF NA 3.3
tmds_d_p[2] tmds_d_n[2] 35,34/2 Y out IOR2 RPLL_T_in LVCMOS33D 8 NONE NA NA NA NA OFF NA 3.3

All Package Pins:

Loc./Bank Signal Dir. Site CFG IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor Bank Vccio
3/0 - in IOT2[A] TDI LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
4/0 - out IOT2[B] TDO LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
6/0 - in IOT3[A] TMS LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
7/0 - in IOT3[B] TCK LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
8/0 - in IOT4[B] JTAGSEL_N LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
9/0 - in IOT5[B] DONE LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
10/0 - in IOT7[A] MODE1 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
1/0 - in IOT10[A] MCLK/D4 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
2/0 - in IOT10[B] MCS_N/D5 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
48/1 - in IOT11[A] MO/D6 LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
47/1 - in IOT11[B] MI/D7 LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
45/1 clk in IOT13[A] LPLL_T_in LVCMOS33 NA UP ON NONE NA NA NA NA 1.2
46/1 - in IOT13[B] LPLL_C_in LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
43/1 - in IOT17[A] GCLKT_0 LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
44/1 - in IOT17[B] GCLKC_0 LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
41/1 - in IOT20[A] GCLKT_1 LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
42/1 - in IOT20[B] GCLKC_1 LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
39/1 - in IOT26[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
40/1 - in IOT26[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
13/3 - in IOB4[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
14/3 resetn in IOB4[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
15/3 - in IOB5[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
p1-22/3 - in IOB5[B] - LVCMOS18 - UP - - - - - - -
16/3 - in IOB6[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
17/3 - in IOB6[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
p1-19/3 - in IOB7[A] - LVCMOS18 - UP - - - - - - -
p1-18/3 - in IOB7[B] - LVCMOS18 - UP - - - - - - -
18/3 - in IOB13[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
19/3 - in IOB13[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
p1-17/3 - in IOB14[A] - LVCMOS18 - UP - - - - - - -
p1-16/3 - in IOB14[B] - LVCMOS18 - UP - - - - - - -
p1-15/3 - in IOB15[A] - LVCMOS18 - UP - - - - - - -
p1-14/3 - in IOB15[B] - LVCMOS18 - UP - - - - - - -
20/3 - in IOB16[A] GCLKT_5 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
21/3 - in IOB16[B] GCLKC_5 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
22/3 - in IOB22[A] GCLKT_4 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
23/3 - in IOB22[B] GCLKC_4 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
p1-13/3 - in IOB23[A] - LVCMOS18 - UP - - - - - - -
p1-10/3 - in IOB24[B] - LVCMOS18 - UP - - - - - - -
p1-9/3 - in IOB25[A] - LVCMOS18 - UP - - - - - - -
p1-8/3 - in IOB25[B] - LVCMOS18 - UP - - - - - - -
p1-7/3 - in IOB29[A] - LVCMOS18 - UP - - - - - - -
p1-6/3 - in IOB29[B] - LVCMOS18 - UP - - - - - - -
35/2 tmds_d_p[2] out IOR2[A] RPLL_T_in LVCMOS33D 8 NONE NA NA NA NA OFF NA 3.3
34/2 tmds_d_n[2] out IOR2[B] RPLL_C_in LVCMOS33D 8 NONE NA NA NA NA OFF NA 3.3
33/2 - in IOR9[B] GCLKC_2 LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
32/2 tmds_d_p[1] out IOR11[A] GCLKT_3 LVCMOS33D 8 NONE NA NA NA NA OFF NA 3.3
31/2 tmds_d_n[1] out IOR11[B] GCLKC_3 LVCMOS33D 8 NONE NA NA NA NA OFF NA 3.3
30/2 tmds_d_p[0] out IOR15[A] - LVCMOS33D 8 NONE NA NA NA NA OFF NA 3.3
29/2 tmds_d_n[0] out IOR15[B] - LVCMOS33D 8 NONE NA NA NA NA OFF NA 3.3
28/2 tmds_clk_p out IOR17[A] - LVCMOS33D 8 NONE NA NA NA NA OFF NA 3.3
27/2 tmds_clk_n out IOR17[B] - LVCMOS33D 8 NONE NA NA NA NA OFF NA 3.3