Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/hdmi_720p/src/gowin_clkdiv/gowin_clkdiv.v /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/hdmi_720p/src/gowin_pllvr/gowin_pllvr.v /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/hdmi_720p/src/hdmi/svo_defines.vh /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/hdmi_720p/src/hdmi/svo_enc.v /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/hdmi_720p/src/hdmi/svo_openldi.v /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/hdmi_720p/src/hdmi/svo_tcard.v /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/hdmi_720p/src/hdmi/svo_term.v /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/hdmi_720p/src/hdmi/svo_tmds.v /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/hdmi_720p/src/hdmi/svo_utils.v /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/hdmi_720p/src/hdmi/svo_vdma.v /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/hdmi_720p/src/svo_hdmi.v /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/hdmi_720p/src/top.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.10.03 Education |
| Part Number | GW1NSR-LV4CQN48PC6/I5 |
| Device | GW1NSR-4C |
| Created Time | Tue Apr 8 10:32:13 2025 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.698s, Elapsed time = 0h 0m 0.434s, Peak memory usage = 320.348MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.043s, Elapsed time = 0h 0m 0.042s, Peak memory usage = 320.348MB Optimizing Phase 1: CPU time = 0h 0m 0.017s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 320.348MB Optimizing Phase 2: CPU time = 0h 0m 0.057s, Elapsed time = 0h 0m 0.054s, Peak memory usage = 320.348MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.034s, Elapsed time = 0h 0m 0.041s, Peak memory usage = 320.348MB Inferring Phase 1: CPU time = 0h 0m 0.012s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 320.348MB Inferring Phase 2: CPU time = 0h 0m 0.005s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 320.348MB Inferring Phase 3: CPU time = 0h 0m 0.008s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 320.348MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.107s, Elapsed time = 0h 0m 0.104s, Peak memory usage = 320.348MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 320.348MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.013s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 320.348MB Tech-Mapping Phase 3: CPU time = 0h 0m 9s, Elapsed time = 0h 0m 9s, Peak memory usage = 320.348MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.137s, Elapsed time = 0h 0m 0.136s, Peak memory usage = 320.348MB Generate output files: CPU time = 0h 0m 0.3s, Elapsed time = 0h 0m 0.334s, Peak memory usage = 320.348MB |
| Total Time and Memory Usage | CPU time = 0h 0m 10s, Elapsed time = 0h 0m 10s, Peak memory usage = 320.348MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 10 |
| I/O Buf | 6 |
| IBUF | 2 |
| ELVDS_OBUF | 4 |
| Register | 634 |
| DFF | 65 |
| DFFE | 232 |
| DFFS | 1 |
| DFFSE | 4 |
| DFFR | 104 |
| DFFRE | 224 |
| DFFC | 4 |
| LUT | 900 |
| LUT2 | 105 |
| LUT3 | 377 |
| LUT4 | 418 |
| ALU | 115 |
| ALU | 115 |
| INV | 5 |
| INV | 5 |
| IOLOGIC | 3 |
| OSER10 | 3 |
| BSRAM | 1 |
| pROM | 1 |
| CLOCK | 2 |
| CLKDIV | 1 |
| PLLVR | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 1020(905 LUT, 115 ALU) / 4608 | 23% |
| Register | 634 / 3573 | 18% |
| --Register as Latch | 0 / 3573 | 0% |
| --Register as FF | 634 / 3573 | 18% |
| BSRAM | 1 / 10 | 10% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk | Base | 37.037 | 27.0 | 0.000 | 18.519 | clk_ibuf/I | ||
| 2 | Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk | Generated | 7.937 | 126.0 | 0.000 | 3.968 | clk_ibuf/I | clk | Gowin_PLLVR_inst/pllvr_inst/CLKOUT |
| 3 | Gowin_PLLVR_inst/pllvr_inst/CLKOUTP.default_gen_clk | Generated | 7.937 | 126.0 | 0.000 | 3.968 | clk_ibuf/I | clk | Gowin_PLLVR_inst/pllvr_inst/CLKOUTP |
| 4 | Gowin_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk | Generated | 15.873 | 63.0 | 0.000 | 7.937 | clk_ibuf/I | clk | Gowin_PLLVR_inst/pllvr_inst/CLKOUTD |
| 5 | Gowin_PLLVR_inst/pllvr_inst/CLKOUTD3.default_gen_clk | Generated | 23.810 | 42.0 | 0.000 | 11.905 | clk_ibuf/I | clk | Gowin_PLLVR_inst/pllvr_inst/CLKOUTD3 |
| 6 | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk | Generated | 39.683 | 25.2 | 0.000 | 19.841 | Gowin_PLLVR_inst/pllvr_inst/CLKOUT | Gowin_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk | u_div_5/clkdiv_inst/CLKOUT |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk | 25.200(MHz) | 32.183(MHz) | 17 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 8.610 |
| Data Arrival Time | 32.125 |
| Data Required Time | 40.736 |
| From | svo_hdmi_inst/svo_enc/out_axis_tdata_2_s0 |
| To | svo_hdmi_inst/svo_tmds_2/cnt_7_s0 |
| Launch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk | |||
| 0.727 | 0.727 | tCL | RR | 639 | u_div_5/clkdiv_inst/CLKOUT |
| 1.453 | 0.726 | tNET | RR | 1 | svo_hdmi_inst/svo_enc/out_axis_tdata_2_s0/CLK |
| 1.911 | 0.458 | tC2Q | RF | 7 | svo_hdmi_inst/svo_enc/out_axis_tdata_2_s0/Q |
| 2.871 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n146_s15/I1 |
| 3.970 | 1.099 | tINS | FF | 12 | svo_hdmi_inst/svo_tmds_2/n146_s15/F |
| 4.930 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n406_s2/I1 |
| 6.029 | 1.099 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_2/n406_s2/F |
| 6.989 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n88_s4/I3 |
| 7.615 | 0.626 | tINS | FF | 3 | svo_hdmi_inst/svo_tmds_2/n88_s4/F |
| 8.575 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n88_s1/I0 |
| 9.607 | 1.032 | tINS | FF | 8 | svo_hdmi_inst/svo_tmds_2/n88_s1/F |
| 10.567 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n175_s19/I0 |
| 11.599 | 1.032 | tINS | FF | 2 | svo_hdmi_inst/svo_tmds_2/n175_s19/F |
| 12.559 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n175_s16/I1 |
| 13.658 | 1.099 | tINS | FF | 3 | svo_hdmi_inst/svo_tmds_2/n175_s16/F |
| 14.618 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n175_s14/I1 |
| 15.717 | 1.099 | tINS | FF | 4 | svo_hdmi_inst/svo_tmds_2/n175_s14/F |
| 16.677 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n176_s13/I1 |
| 17.776 | 1.099 | tINS | FF | 4 | svo_hdmi_inst/svo_tmds_2/n176_s13/F |
| 18.736 | 0.960 | tNET | FF | 2 | svo_hdmi_inst/svo_tmds_2/n223_s/I1 |
| 19.781 | 1.045 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_2/n223_s/COUT |
| 19.781 | 0.000 | tNET | FF | 2 | svo_hdmi_inst/svo_tmds_2/n289_s/CIN |
| 20.344 | 0.563 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_2/n289_s/SUM |
| 21.304 | 0.960 | tNET | FF | 2 | svo_hdmi_inst/svo_tmds_2/n289_s0/I0 |
| 22.262 | 0.958 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_2/n289_s0/COUT |
| 22.262 | 0.000 | tNET | FF | 2 | svo_hdmi_inst/svo_tmds_2/n288_s0/CIN |
| 22.319 | 0.057 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_2/n288_s0/COUT |
| 22.319 | 0.000 | tNET | FF | 2 | svo_hdmi_inst/svo_tmds_2/n287_s0/CIN |
| 22.376 | 0.057 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_2/n287_s0/COUT |
| 22.376 | 0.000 | tNET | FF | 2 | svo_hdmi_inst/svo_tmds_2/n286_s0/CIN |
| 22.433 | 0.057 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_2/n286_s0/COUT |
| 22.433 | 0.000 | tNET | FF | 2 | svo_hdmi_inst/svo_tmds_2/n285_s0/CIN |
| 22.996 | 0.563 | tINS | FF | 4 | svo_hdmi_inst/svo_tmds_2/n285_s0/SUM |
| 23.956 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n377_s8/I1 |
| 25.055 | 1.099 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_2/n377_s8/F |
| 26.015 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n377_s4/I1 |
| 27.114 | 1.099 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_2/n377_s4/F |
| 28.074 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n377_s1/I1 |
| 29.173 | 1.099 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_2/n377_s1/F |
| 30.133 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n377_s0/I0 |
| 31.165 | 1.032 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_2/n377_s0/F |
| 32.125 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/cnt_7_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 39.683 | 0.000 | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk | |||
| 40.410 | 0.727 | tCL | RR | 639 | u_div_5/clkdiv_inst/CLKOUT |
| 41.136 | 0.726 | tNET | RR | 1 | svo_hdmi_inst/svo_tmds_2/cnt_7_s0/CLK |
| 40.736 | -0.400 | tSu | 1 | svo_hdmi_inst/svo_tmds_2/cnt_7_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 39.683 |
| Logic Level: | 17 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 15.814, 51.558%; route: 14.400, 46.948%; tC2Q: 0.458, 1.494% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 2
Path Summary:| Slack | 8.781 |
| Data Arrival Time | 31.954 |
| Data Required Time | 40.736 |
| From | svo_hdmi_inst/svo_enc/out_axis_tdata_2_s0 |
| To | svo_hdmi_inst/svo_tmds_2/cnt_4_s0 |
| Launch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk | |||
| 0.727 | 0.727 | tCL | RR | 639 | u_div_5/clkdiv_inst/CLKOUT |
| 1.453 | 0.726 | tNET | RR | 1 | svo_hdmi_inst/svo_enc/out_axis_tdata_2_s0/CLK |
| 1.911 | 0.458 | tC2Q | RF | 7 | svo_hdmi_inst/svo_enc/out_axis_tdata_2_s0/Q |
| 2.871 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n146_s15/I1 |
| 3.970 | 1.099 | tINS | FF | 12 | svo_hdmi_inst/svo_tmds_2/n146_s15/F |
| 4.930 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n406_s2/I1 |
| 6.029 | 1.099 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_2/n406_s2/F |
| 6.989 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n88_s4/I3 |
| 7.615 | 0.626 | tINS | FF | 3 | svo_hdmi_inst/svo_tmds_2/n88_s4/F |
| 8.575 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n88_s1/I0 |
| 9.607 | 1.032 | tINS | FF | 8 | svo_hdmi_inst/svo_tmds_2/n88_s1/F |
| 10.567 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n175_s19/I0 |
| 11.599 | 1.032 | tINS | FF | 2 | svo_hdmi_inst/svo_tmds_2/n175_s19/F |
| 12.559 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n175_s16/I1 |
| 13.658 | 1.099 | tINS | FF | 3 | svo_hdmi_inst/svo_tmds_2/n175_s16/F |
| 14.618 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n175_s14/I1 |
| 15.717 | 1.099 | tINS | FF | 4 | svo_hdmi_inst/svo_tmds_2/n175_s14/F |
| 16.677 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n176_s13/I1 |
| 17.776 | 1.099 | tINS | FF | 4 | svo_hdmi_inst/svo_tmds_2/n176_s13/F |
| 18.736 | 0.960 | tNET | FF | 2 | svo_hdmi_inst/svo_tmds_2/n223_s/I1 |
| 19.781 | 1.045 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_2/n223_s/COUT |
| 19.781 | 0.000 | tNET | FF | 2 | svo_hdmi_inst/svo_tmds_2/n289_s/CIN |
| 20.344 | 0.563 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_2/n289_s/SUM |
| 21.304 | 0.960 | tNET | FF | 2 | svo_hdmi_inst/svo_tmds_2/n289_s0/I0 |
| 22.262 | 0.958 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_2/n289_s0/COUT |
| 22.262 | 0.000 | tNET | FF | 2 | svo_hdmi_inst/svo_tmds_2/n288_s0/CIN |
| 22.825 | 0.563 | tINS | FF | 4 | svo_hdmi_inst/svo_tmds_2/n288_s0/SUM |
| 23.785 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n377_s7/I1 |
| 24.884 | 1.099 | tINS | FF | 4 | svo_hdmi_inst/svo_tmds_2/n377_s7/F |
| 25.844 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n380_s4/I1 |
| 26.943 | 1.099 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_2/n380_s4/F |
| 27.903 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n380_s1/I1 |
| 29.002 | 1.099 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_2/n380_s1/F |
| 29.962 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n380_s0/I0 |
| 30.994 | 1.032 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_2/n380_s0/F |
| 31.954 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/cnt_4_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 39.683 | 0.000 | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk | |||
| 40.410 | 0.727 | tCL | RR | 639 | u_div_5/clkdiv_inst/CLKOUT |
| 41.136 | 0.726 | tNET | RR | 1 | svo_hdmi_inst/svo_tmds_2/cnt_4_s0/CLK |
| 40.736 | -0.400 | tSu | 1 | svo_hdmi_inst/svo_tmds_2/cnt_4_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 39.683 |
| Logic Level: | 17 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 15.643, 51.286%; route: 14.400, 47.211%; tC2Q: 0.458, 1.503% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 3
Path Summary:| Slack | 8.781 |
| Data Arrival Time | 31.954 |
| Data Required Time | 40.736 |
| From | svo_hdmi_inst/svo_enc/out_axis_tdata_2_s0 |
| To | svo_hdmi_inst/svo_tmds_2/cnt_5_s0 |
| Launch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk | |||
| 0.727 | 0.727 | tCL | RR | 639 | u_div_5/clkdiv_inst/CLKOUT |
| 1.453 | 0.726 | tNET | RR | 1 | svo_hdmi_inst/svo_enc/out_axis_tdata_2_s0/CLK |
| 1.911 | 0.458 | tC2Q | RF | 7 | svo_hdmi_inst/svo_enc/out_axis_tdata_2_s0/Q |
| 2.871 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n146_s15/I1 |
| 3.970 | 1.099 | tINS | FF | 12 | svo_hdmi_inst/svo_tmds_2/n146_s15/F |
| 4.930 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n406_s2/I1 |
| 6.029 | 1.099 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_2/n406_s2/F |
| 6.989 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n88_s4/I3 |
| 7.615 | 0.626 | tINS | FF | 3 | svo_hdmi_inst/svo_tmds_2/n88_s4/F |
| 8.575 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n88_s1/I0 |
| 9.607 | 1.032 | tINS | FF | 8 | svo_hdmi_inst/svo_tmds_2/n88_s1/F |
| 10.567 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n175_s19/I0 |
| 11.599 | 1.032 | tINS | FF | 2 | svo_hdmi_inst/svo_tmds_2/n175_s19/F |
| 12.559 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n175_s16/I1 |
| 13.658 | 1.099 | tINS | FF | 3 | svo_hdmi_inst/svo_tmds_2/n175_s16/F |
| 14.618 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n175_s14/I1 |
| 15.717 | 1.099 | tINS | FF | 4 | svo_hdmi_inst/svo_tmds_2/n175_s14/F |
| 16.677 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n176_s13/I1 |
| 17.776 | 1.099 | tINS | FF | 4 | svo_hdmi_inst/svo_tmds_2/n176_s13/F |
| 18.736 | 0.960 | tNET | FF | 2 | svo_hdmi_inst/svo_tmds_2/n223_s/I1 |
| 19.781 | 1.045 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_2/n223_s/COUT |
| 19.781 | 0.000 | tNET | FF | 2 | svo_hdmi_inst/svo_tmds_2/n289_s/CIN |
| 20.344 | 0.563 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_2/n289_s/SUM |
| 21.304 | 0.960 | tNET | FF | 2 | svo_hdmi_inst/svo_tmds_2/n289_s0/I0 |
| 22.262 | 0.958 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_2/n289_s0/COUT |
| 22.262 | 0.000 | tNET | FF | 2 | svo_hdmi_inst/svo_tmds_2/n288_s0/CIN |
| 22.825 | 0.563 | tINS | FF | 4 | svo_hdmi_inst/svo_tmds_2/n288_s0/SUM |
| 23.785 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n377_s7/I1 |
| 24.884 | 1.099 | tINS | FF | 4 | svo_hdmi_inst/svo_tmds_2/n377_s7/F |
| 25.844 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n379_s4/I1 |
| 26.943 | 1.099 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_2/n379_s4/F |
| 27.903 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n379_s1/I1 |
| 29.002 | 1.099 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_2/n379_s1/F |
| 29.962 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n379_s0/I0 |
| 30.994 | 1.032 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_2/n379_s0/F |
| 31.954 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/cnt_5_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 39.683 | 0.000 | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk | |||
| 40.410 | 0.727 | tCL | RR | 639 | u_div_5/clkdiv_inst/CLKOUT |
| 41.136 | 0.726 | tNET | RR | 1 | svo_hdmi_inst/svo_tmds_2/cnt_5_s0/CLK |
| 40.736 | -0.400 | tSu | 1 | svo_hdmi_inst/svo_tmds_2/cnt_5_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 39.683 |
| Logic Level: | 17 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 15.643, 51.286%; route: 14.400, 47.211%; tC2Q: 0.458, 1.503% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 4
Path Summary:| Slack | 9.016 |
| Data Arrival Time | 31.719 |
| Data Required Time | 40.736 |
| From | svo_hdmi_inst/svo_enc/out_axis_tdata_18_s0 |
| To | svo_hdmi_inst/svo_tmds_0/cnt_7_s0 |
| Launch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk | |||
| 0.727 | 0.727 | tCL | RR | 639 | u_div_5/clkdiv_inst/CLKOUT |
| 1.453 | 0.726 | tNET | RR | 1 | svo_hdmi_inst/svo_enc/out_axis_tdata_18_s0/CLK |
| 1.911 | 0.458 | tC2Q | RF | 8 | svo_hdmi_inst/svo_enc/out_axis_tdata_18_s0/Q |
| 2.871 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_0/n404_s4/I1 |
| 3.970 | 1.099 | tINS | FF | 9 | svo_hdmi_inst/svo_tmds_0/n404_s4/F |
| 4.930 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_0/n406_s2/I1 |
| 6.029 | 1.099 | tINS | FF | 3 | svo_hdmi_inst/svo_tmds_0/n406_s2/F |
| 6.989 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_0/n88_s7/I3 |
| 7.615 | 0.626 | tINS | FF | 2 | svo_hdmi_inst/svo_tmds_0/n88_s7/F |
| 8.575 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_0/n88_s1/I3 |
| 9.201 | 0.626 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_0/n88_s1/F |
| 10.161 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_0/n88_s0/I1 |
| 11.260 | 1.099 | tINS | FF | 30 | svo_hdmi_inst/svo_tmds_0/n88_s0/F |
| 12.220 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_0/n146_s12/I1 |
| 13.319 | 1.099 | tINS | FF | 3 | svo_hdmi_inst/svo_tmds_0/n146_s12/F |
| 14.279 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_0/n146_s10/I1 |
| 15.378 | 1.099 | tINS | FF | 4 | svo_hdmi_inst/svo_tmds_0/n146_s10/F |
| 16.338 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_0/n147_s18/I0 |
| 17.370 | 1.032 | tINS | FF | 4 | svo_hdmi_inst/svo_tmds_0/n147_s18/F |
| 18.330 | 0.960 | tNET | FF | 2 | svo_hdmi_inst/svo_tmds_0/n223_s/I1 |
| 19.375 | 1.045 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_0/n223_s/COUT |
| 19.375 | 0.000 | tNET | FF | 2 | svo_hdmi_inst/svo_tmds_0/n289_s/CIN |
| 19.938 | 0.563 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_0/n289_s/SUM |
| 20.898 | 0.960 | tNET | FF | 2 | svo_hdmi_inst/svo_tmds_0/n289_s0/I0 |
| 21.856 | 0.958 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_0/n289_s0/COUT |
| 21.856 | 0.000 | tNET | FF | 2 | svo_hdmi_inst/svo_tmds_0/n288_s0/CIN |
| 21.913 | 0.057 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_0/n288_s0/COUT |
| 21.913 | 0.000 | tNET | FF | 2 | svo_hdmi_inst/svo_tmds_0/n287_s0/CIN |
| 21.970 | 0.057 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_0/n287_s0/COUT |
| 21.970 | 0.000 | tNET | FF | 2 | svo_hdmi_inst/svo_tmds_0/n286_s0/CIN |
| 22.027 | 0.057 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_0/n286_s0/COUT |
| 22.027 | 0.000 | tNET | FF | 2 | svo_hdmi_inst/svo_tmds_0/n285_s0/CIN |
| 22.590 | 0.563 | tINS | FF | 4 | svo_hdmi_inst/svo_tmds_0/n285_s0/SUM |
| 23.550 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_0/n377_s8/I1 |
| 24.649 | 1.099 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_0/n377_s8/F |
| 25.609 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_0/n377_s4/I1 |
| 26.708 | 1.099 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_0/n377_s4/F |
| 27.668 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_0/n377_s1/I1 |
| 28.767 | 1.099 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_0/n377_s1/F |
| 29.727 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_0/n377_s0/I0 |
| 30.759 | 1.032 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_0/n377_s0/F |
| 31.719 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_0/cnt_7_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 39.683 | 0.000 | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk | |||
| 40.410 | 0.727 | tCL | RR | 639 | u_div_5/clkdiv_inst/CLKOUT |
| 41.136 | 0.726 | tNET | RR | 1 | svo_hdmi_inst/svo_tmds_0/cnt_7_s0/CLK |
| 40.736 | -0.400 | tSu | 1 | svo_hdmi_inst/svo_tmds_0/cnt_7_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 39.683 |
| Logic Level: | 17 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 15.408, 50.908%; route: 14.400, 47.578%; tC2Q: 0.458, 1.514% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 5
Path Summary:| Slack | 9.058 |
| Data Arrival Time | 31.677 |
| Data Required Time | 40.736 |
| From | svo_hdmi_inst/svo_enc/out_axis_tdata_2_s0 |
| To | svo_hdmi_inst/svo_tmds_2/cnt_6_s0 |
| Launch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk | |||
| 0.727 | 0.727 | tCL | RR | 639 | u_div_5/clkdiv_inst/CLKOUT |
| 1.453 | 0.726 | tNET | RR | 1 | svo_hdmi_inst/svo_enc/out_axis_tdata_2_s0/CLK |
| 1.911 | 0.458 | tC2Q | RF | 7 | svo_hdmi_inst/svo_enc/out_axis_tdata_2_s0/Q |
| 2.871 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n146_s15/I1 |
| 3.970 | 1.099 | tINS | FF | 12 | svo_hdmi_inst/svo_tmds_2/n146_s15/F |
| 4.930 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n406_s2/I1 |
| 6.029 | 1.099 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_2/n406_s2/F |
| 6.989 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n88_s4/I3 |
| 7.615 | 0.626 | tINS | FF | 3 | svo_hdmi_inst/svo_tmds_2/n88_s4/F |
| 8.575 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n88_s1/I0 |
| 9.607 | 1.032 | tINS | FF | 8 | svo_hdmi_inst/svo_tmds_2/n88_s1/F |
| 10.567 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n175_s19/I0 |
| 11.599 | 1.032 | tINS | FF | 2 | svo_hdmi_inst/svo_tmds_2/n175_s19/F |
| 12.559 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n175_s16/I1 |
| 13.658 | 1.099 | tINS | FF | 3 | svo_hdmi_inst/svo_tmds_2/n175_s16/F |
| 14.618 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n175_s14/I1 |
| 15.717 | 1.099 | tINS | FF | 4 | svo_hdmi_inst/svo_tmds_2/n175_s14/F |
| 16.677 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n176_s13/I1 |
| 17.776 | 1.099 | tINS | FF | 4 | svo_hdmi_inst/svo_tmds_2/n176_s13/F |
| 18.736 | 0.960 | tNET | FF | 2 | svo_hdmi_inst/svo_tmds_2/n223_s/I1 |
| 19.781 | 1.045 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_2/n223_s/COUT |
| 19.781 | 0.000 | tNET | FF | 2 | svo_hdmi_inst/svo_tmds_2/n289_s/CIN |
| 20.344 | 0.563 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_2/n289_s/SUM |
| 21.304 | 0.960 | tNET | FF | 2 | svo_hdmi_inst/svo_tmds_2/n289_s0/I0 |
| 22.262 | 0.958 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_2/n289_s0/COUT |
| 22.262 | 0.000 | tNET | FF | 2 | svo_hdmi_inst/svo_tmds_2/n288_s0/CIN |
| 22.825 | 0.563 | tINS | FF | 4 | svo_hdmi_inst/svo_tmds_2/n288_s0/SUM |
| 23.785 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n377_s7/I1 |
| 24.884 | 1.099 | tINS | FF | 4 | svo_hdmi_inst/svo_tmds_2/n377_s7/F |
| 25.844 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n378_s4/I2 |
| 26.666 | 0.822 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_2/n378_s4/F |
| 27.626 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n378_s1/I1 |
| 28.725 | 1.099 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_2/n378_s1/F |
| 29.685 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/n378_s0/I0 |
| 30.717 | 1.032 | tINS | FF | 1 | svo_hdmi_inst/svo_tmds_2/n378_s0/F |
| 31.677 | 0.960 | tNET | FF | 1 | svo_hdmi_inst/svo_tmds_2/cnt_6_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 39.683 | 0.000 | u_div_5/clkdiv_inst/CLKOUT.default_gen_clk | |||
| 40.410 | 0.727 | tCL | RR | 639 | u_div_5/clkdiv_inst/CLKOUT |
| 41.136 | 0.726 | tNET | RR | 1 | svo_hdmi_inst/svo_tmds_2/cnt_6_s0/CLK |
| 40.736 | -0.400 | tSu | 1 | svo_hdmi_inst/svo_tmds_2/cnt_6_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 39.683 |
| Logic Level: | 17 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 15.366, 50.840%; route: 14.400, 47.644%; tC2Q: 0.458, 1.516% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |