Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | /home/quang1806/Desktop/GOWIN_IDE_PROGRAMMER/IDE/ipcore/VFB/data/vfb_top.v /home/quang1806/Desktop/GOWIN_IDE_PROGRAMMER/IDE/ipcore/VFB/data/vfb_wrapper.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.9 |
| Part Number | GW1NSR-LV4CQN48PC6/I5 |
| Device | GW1NSR-4C |
| Created Time | Wed Mar 26 07:21:00 2025 |
| Legal Announcement | Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | Video_Frame_Buffer_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.139s, Elapsed time = 0h 0m 0.151s, Peak memory usage = 72.406MB Running netlist conversion: CPU time = 0h 0m 0.009s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 72.406MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.013s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 72.531MB Optimizing Phase 1: CPU time = 0h 0m 0.009s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 72.531MB Optimizing Phase 2: CPU time = 0h 0m 0.017s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 72.656MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.006s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 73.137MB Inferring Phase 1: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 73.137MB Inferring Phase 2: CPU time = 0h 0m 0.002s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 73.137MB Inferring Phase 3: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 73.309MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.017s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 73.309MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.005s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 73.309MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.006s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 73.309MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 105.125MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.075s, Elapsed time = 0h 0m 0.075s, Peak memory usage = 105.125MB Generate output files: CPU time = 0h 0m 0.132s, Elapsed time = 0h 0m 0.133s, Peak memory usage = 105.125MB |
| Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 105.125MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 139 |
| I/O Buf | 139 |
| IBUF | 60 |
| OBUF | 79 |
| Register | 339 |
| DFF | 1 |
| DFFS | 8 |
| DFFR | 2 |
| DFFP | 28 |
| DFFPE | 2 |
| DFFC | 228 |
| DFFCE | 70 |
| LUT | 423 |
| LUT2 | 90 |
| LUT3 | 136 |
| LUT4 | 197 |
| ALU | 38 |
| ALU | 38 |
| INV | 5 |
| INV | 5 |
| BSRAM | 2 |
| SDPB | 2 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 466(428 LUT, 38 ALU) / 4608 | 11% |
| Register | 339 / 3570 | 10% |
| --Register as Latch | 0 / 3570 | 0% |
| --Register as FF | 339 / 3570 | 10% |
| BSRAM | 2 / 10 | 20% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| I_vin0_clk | Base | 20.000 | 50.0 | 0.000 | 10.000 | I_vin0_clk_ibuf/I | ||
| I_dma_clk | Base | 20.000 | 50.0 | 0.000 | 10.000 | I_dma_clk_ibuf/I | ||
| I_vout0_clk | Base | 20.000 | 50.0 | 0.000 | 10.000 | I_vout0_clk_ibuf/I | ||
| vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n32_6 | Base | 20.000 | 50.0 | 0.000 | 10.000 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n32_s2/O | ||
| vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n37_6 | Base | 20.000 | 50.0 | 0.000 | 10.000 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n37_s2/O | ||
| vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n35_6 | Base | 20.000 | 50.0 | 0.000 | 10.000 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n35_s2/O |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | I_vin0_clk | 50.0(MHz) | 111.7(MHz) | 6 | TOP |
| 2 | I_dma_clk | 50.0(MHz) | 90.8(MHz) | 9 | TOP |
| 3 | I_vout0_clk | 50.0(MHz) | 102.5(MHz) | 8 | TOP |
| 4 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n32_6 | 50.0(MHz) | 747.2(MHz) | 1 | TOP |
| 5 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n37_6 | 50.0(MHz) | 747.2(MHz) | 1 | TOP |
| 6 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n35_6 | 50.0(MHz) | 747.2(MHz) | 1 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 8.983 |
| Data Arrival Time | 11.962 |
| Data Required Time | 20.945 |
| From | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_5_s1 |
| To | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0 |
| Launch Clk | I_dma_clk[R] |
| Latch Clk | I_dma_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_dma_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_dma_clk_ibuf/I |
| 0.982 | 0.982 | tINS | RR | 219 | I_dma_clk_ibuf/O |
| 1.345 | 0.363 | tNET | RR | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_5_s1/CLK |
| 1.803 | 0.458 | tC2Q | RF | 16 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_rd_cnt_5_s1/Q |
| 2.283 | 0.480 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_1_s4/I1 |
| 3.382 | 1.099 | tINS | FF | 8 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_1_s4/F |
| 3.862 | 0.480 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_4_s4/I3 |
| 4.488 | 0.626 | tINS | FF | 8 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_4_s4/F |
| 4.968 | 0.480 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_7_s4/I3 |
| 5.594 | 0.626 | tINS | FF | 7 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_7_s4/F |
| 6.074 | 0.480 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_8_s3/I1 |
| 7.173 | 1.099 | tINS | FF | 4 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rbin_num_next_8_s3/F |
| 7.653 | 0.480 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rgraynext_7_s1/I0 |
| 8.685 | 1.032 | tINS | FF | 2 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rgraynext_7_s1/F |
| 9.165 | 0.480 | tNET | FF | 2 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n323_s0/I0 |
| 10.123 | 0.958 | tINS | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n323_s0/COUT |
| 10.123 | 0.000 | tNET | FF | 2 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n324_s0/CIN |
| 10.180 | 0.057 | tINS | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n324_s0/COUT |
| 10.660 | 0.480 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rempty_val_s1/I2 |
| 11.482 | 0.822 | tINS | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/rempty_val_s1/F |
| 11.962 | 0.480 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | I_dma_clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | I_dma_clk_ibuf/I |
| 20.982 | 0.982 | tINS | RR | 219 | I_dma_clk_ibuf/O |
| 21.345 | 0.363 | tNET | RR | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0/CLK |
| 20.945 | -0.400 | tSu | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Empty_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
| Arrival Data Path Delay: | cell: 6.319, 59.516%; route: 3.840, 36.167%; tC2Q: 0.458, 4.317% |
| Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Path 2
Path Summary:| Slack | 10.242 |
| Data Arrival Time | 10.703 |
| Data Required Time | 20.945 |
| From | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_1_s0 |
| To | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0 |
| Launch Clk | I_vout0_clk[R] |
| Latch Clk | I_vout0_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_vout0_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_vout0_clk_ibuf/I |
| 0.982 | 0.982 | tINS | RR | 57 | I_vout0_clk_ibuf/O |
| 1.345 | 0.363 | tNET | RR | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_1_s0/CLK |
| 1.803 | 0.458 | tC2Q | RF | 4 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_1_s0/Q |
| 2.283 | 0.480 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_2_s4/I1 |
| 3.382 | 1.099 | tINS | FF | 7 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_2_s4/F |
| 3.862 | 0.480 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_5_s4/I3 |
| 4.488 | 0.626 | tINS | FF | 7 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_5_s4/F |
| 4.968 | 0.480 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_7_s4/I2 |
| 5.790 | 0.822 | tINS | FF | 3 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rbin_num_next_7_s4/F |
| 6.270 | 0.480 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rgraynext_6_s0/I1 |
| 7.369 | 1.099 | tINS | FF | 2 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rgraynext_6_s0/F |
| 7.849 | 0.480 | tNET | FF | 2 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n322_s0/I0 |
| 8.807 | 0.958 | tINS | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n322_s0/COUT |
| 8.807 | 0.000 | tNET | FF | 2 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n323_s0/CIN |
| 8.864 | 0.057 | tINS | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n323_s0/COUT |
| 8.864 | 0.000 | tNET | FF | 2 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n324_s0/CIN |
| 8.921 | 0.057 | tINS | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n324_s0/COUT |
| 9.401 | 0.480 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rempty_val_s1/I2 |
| 10.223 | 0.822 | tINS | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/rempty_val_s1/F |
| 10.703 | 0.480 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | I_vout0_clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | I_vout0_clk_ibuf/I |
| 20.982 | 0.982 | tINS | RR | 57 | I_vout0_clk_ibuf/O |
| 21.345 | 0.363 | tNET | RR | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0/CLK |
| 20.945 | -0.400 | tSu | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Empty_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
| Arrival Data Path Delay: | cell: 5.540, 59.198%; route: 3.360, 35.904%; tC2Q: 0.458, 4.898% |
| Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Path 3
Path Summary:| Slack | 10.901 |
| Data Arrival Time | 10.044 |
| Data Required Time | 20.945 |
| From | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_req_o_s5 |
| To | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Full_s0 |
| Launch Clk | I_dma_clk[R] |
| Latch Clk | I_dma_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_dma_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_dma_clk_ibuf/I |
| 0.982 | 0.982 | tINS | RR | 219 | I_dma_clk_ibuf/O |
| 1.345 | 0.363 | tNET | RR | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_req_o_s5/CLK |
| 1.803 | 0.458 | tC2Q | RF | 3 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_rd_req_o_s5/Q |
| 2.283 | 0.480 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n60_s2/I1 |
| 3.382 | 1.099 | tINS | FF | 43 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/n60_s2/F |
| 3.862 | 0.480 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wgraynext_3_s1/I0 |
| 4.894 | 1.032 | tINS | FF | 7 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wgraynext_3_s1/F |
| 5.374 | 0.480 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wgraynext_4_s0/I1 |
| 6.473 | 1.099 | tINS | FF | 2 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wgraynext_4_s0/F |
| 6.953 | 0.480 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wfull_val_s1/I1 |
| 8.052 | 1.099 | tINS | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wfull_val_s1/F |
| 8.532 | 0.480 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wfull_val_s0/I0 |
| 9.564 | 1.032 | tINS | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/wfull_val_s0/F |
| 10.044 | 0.480 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Full_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | I_dma_clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | I_dma_clk_ibuf/I |
| 20.982 | 0.982 | tINS | RR | 219 | I_dma_clk_ibuf/O |
| 21.345 | 0.363 | tNET | RR | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Full_s0/CLK |
| 20.945 | -0.400 | tSu | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Full_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
| Arrival Data Path Delay: | cell: 5.361, 61.625%; route: 2.880, 33.106%; tC2Q: 0.458, 5.269% |
| Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Path 4
Path Summary:| Slack | 11.044 |
| Data Arrival Time | 9.901 |
| Data Required Time | 20.945 |
| From | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_den_s0 |
| To | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Full_s0 |
| Launch Clk | I_vin0_clk[R] |
| Latch Clk | I_vin0_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_vin0_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_vin0_clk_ibuf/I |
| 0.982 | 0.982 | tINS | RR | 62 | I_vin0_clk_ibuf/O |
| 1.345 | 0.363 | tNET | RR | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_den_s0/CLK |
| 1.803 | 0.458 | tC2Q | RF | 4 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_den_s0/Q |
| 2.283 | 0.480 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n56_s1/I1 |
| 3.382 | 1.099 | tINS | FF | 2 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/n56_s1/F |
| 3.862 | 0.480 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wgraynext_0_s0/I1 |
| 4.961 | 1.099 | tINS | FF | 2 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wgraynext_0_s0/F |
| 5.441 | 0.480 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/wfull_val_s7/I1 |
| 6.540 | 1.099 | tINS | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/wfull_val_s7/F |
| 7.020 | 0.480 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/wfull_val_s2/I2 |
| 7.842 | 0.822 | tINS | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/wfull_val_s2/F |
| 8.322 | 0.480 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/wfull_val_s0/I1 |
| 9.421 | 1.099 | tINS | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/wfull_val_s0/F |
| 9.901 | 0.480 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Full_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | I_vin0_clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | I_vin0_clk_ibuf/I |
| 20.982 | 0.982 | tINS | RR | 62 | I_vin0_clk_ibuf/O |
| 21.345 | 0.363 | tNET | RR | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Full_s0/CLK |
| 20.945 | -0.400 | tSu | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Full_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
| Arrival Data Path Delay: | cell: 5.218, 60.984%; route: 2.880, 33.659%; tC2Q: 0.458, 5.357% |
| Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Path 5
Path Summary:| Slack | 11.111 |
| Data Arrival Time | 9.834 |
| Data Required Time | 20.945 |
| From | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_den_s0 |
| To | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wptr_8_s1 |
| Launch Clk | I_vin0_clk[R] |
| Latch Clk | I_vin0_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | I_vin0_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | I_vin0_clk_ibuf/I |
| 0.982 | 0.982 | tINS | RR | 62 | I_vin0_clk_ibuf/O |
| 1.345 | 0.363 | tNET | RR | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_den_s0/CLK |
| 1.803 | 0.458 | tC2Q | RF | 4 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_den_s0/Q |
| 2.283 | 0.480 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wgraynext_1_s1/I1 |
| 3.382 | 1.099 | tINS | FF | 7 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wgraynext_1_s1/F |
| 3.862 | 0.480 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wgraynext_5_s1/I2 |
| 4.684 | 0.822 | tINS | FF | 8 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wgraynext_5_s1/F |
| 5.164 | 0.480 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_num_next_9_s5/I1 |
| 6.263 | 1.099 | tINS | FF | 4 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_num_next_9_s5/F |
| 6.743 | 0.480 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_num_next_9_s3/I1 |
| 7.842 | 1.099 | tINS | FF | 2 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wbin_num_next_9_s3/F |
| 8.322 | 0.480 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wgraynext_8_s1/I0 |
| 9.354 | 1.032 | tINS | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wgraynext_8_s1/F |
| 9.834 | 0.480 | tNET | FF | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wptr_8_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | I_vin0_clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | I_vin0_clk_ibuf/I |
| 20.982 | 0.982 | tINS | RR | 62 | I_vin0_clk_ibuf/O |
| 21.345 | 0.363 | tNET | RR | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wptr_8_s1/CLK |
| 20.945 | -0.400 | tSu | 1 | vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wptr_8_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
| Arrival Data Path Delay: | cell: 5.151, 60.676%; route: 2.880, 33.925%; tC2Q: 0.458, 5.399% |
| Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |