Synthesis Messages

Report Title GowinSynthesis Report
Design File /home/quang1806/Desktop/GOWIN_IDE_PROGRAMMER/IDE/ipcore/HYPERRAM_EMB/data/HPRAM_TOP.v
/home/quang1806/Desktop/GOWIN_IDE_PROGRAMMER/IDE/ipcore/HYPERRAM_EMB/data/hpram_code_166.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9
Part Number GW1NSR-LV4CQN48PC6/I5
Device GW1NSR-4C
Created Time Wed Mar 26 07:19:35 2025
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module HyperRAM_Memory_Interface_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.149s, Elapsed time = 0h 0m 0.168s, Peak memory usage = 75.238MB
Running netlist conversion:
    CPU time = 0h 0m 0.008s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 75.238MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.021s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 75.398MB
    Optimizing Phase 1: CPU time = 0h 0m 0.014s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 75.398MB
    Optimizing Phase 2: CPU time = 0h 0m 0.026s, Elapsed time = 0h 0m 0.026s, Peak memory usage = 75.398MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.008s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 75.949MB
    Inferring Phase 1: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 75.949MB
    Inferring Phase 2: CPU time = 0h 0m 0.003s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 75.949MB
    Inferring Phase 3: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 76.117MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.04s, Elapsed time = 0h 0m 0.041s, Peak memory usage = 76.117MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.005s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 76.117MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.003s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 76.117MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 107.516MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.08s, Elapsed time = 0h 0m 0.08s, Peak memory usage = 107.516MB
Generate output files:
    CPU time = 0h 0m 0.126s, Elapsed time = 0h 0m 0.149s, Peak memory usage = 107.516MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 107.516MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 99
Embedded Port 13
I/O Buf 112
    IBUF 64
    OBUF 39
    IOBUF 9
Register 407
    DFF 1
    DFFP 3
    DFFPE 3
    DFFC 243
    DFFCE 157
LUT 565
    LUT2 191
    LUT3 182
    LUT4 192
ALU 31
    ALU 31
INV 6
    INV 6
IOLOGIC 30
    IDES4 8
    OSER4 12
    IODELAY 10
BSRAM 1
    SDPX9B 1
CLOCK 2
    CLKDIV 1
    DHCEN 1

Resource Utilization Summary

Resource Usage Utilization
Logic 602(571 LUT, 31 ALU) / 4608 14%
Register 407 / 3609 12%
  --Register as Latch 0 / 3609 0%
  --Register as FF 407 / 3609 12%
BSRAM 1 / 10 10%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
memory_clk Base 20.000 50.0 0.000 10.000 memory_clk_ibuf/I
clk Base 20.000 50.0 0.000 10.000 clk_ibuf/I
u_hpram_top/clkdiv/CLKOUT.default_gen_clk Generated 40.000 25.0 0.000 20.000 memory_clk_ibuf/I memory_clk u_hpram_top/clkdiv/CLKOUT

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 50.0(MHz) 131.8(MHz) 5 TOP
2 u_hpram_top/clkdiv/CLKOUT.default_gen_clk 25.0(MHz) 140.0(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 8.898
Data Arrival Time 2.283
Data Required Time 11.181
From u_hpram_top/u_hpram_sync/cs_memsync_4_s0
To u_hpram_top/u_dqce_clk_x2p
Launch Clk clk[F]
Latch Clk memory_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.982 0.982 tINS RR 31 clk_ibuf/O
1.345 0.363 tNET RR 1 u_hpram_top/u_hpram_sync/cs_memsync_4_s0/CLK
1.803 0.458 tC2Q RF 8 u_hpram_top/u_hpram_sync/cs_memsync_4_s0/Q
2.283 0.480 tNET FF 1 u_hpram_top/u_dqce_clk_x2p/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 memory_clk
10.000 0.000 tCL FF 1 memory_clk_ibuf/I
10.984 0.984 tINS FF 1 memory_clk_ibuf/O
11.464 0.480 tNET FF 3 u_hpram_top/u_dqce_clk_x2p/CLKIN
11.434 -0.030 tUnc u_hpram_top/u_dqce_clk_x2p
11.181 -0.254 tSu 1 u_hpram_top/u_dqce_clk_x2p
Path Statistics:
Clock Skew: 0.120
Setup Relationship: 10.000
Logic Level: 1
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.480, 51.155%; tC2Q: 0.458, 48.845%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 2

Path Summary:
Slack 12.413
Data Arrival Time 8.532
Data Required Time 20.945
From u_hpram_top/u_hpram_sync/cs_memsync_5_s0
To u_hpram_top/u_hpram_sync/cs_memsync_1_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.982 0.982 tINS RR 31 clk_ibuf/O
1.345 0.363 tNET RR 1 u_hpram_top/u_hpram_sync/cs_memsync_5_s0/CLK
1.803 0.458 tC2Q RF 7 u_hpram_top/u_hpram_sync/cs_memsync_5_s0/Q
2.283 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/n359_s11/I1
3.382 1.099 tINS FF 2 u_hpram_top/u_hpram_sync/n359_s11/F
3.862 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/n359_s8/I1
4.961 1.099 tINS FF 3 u_hpram_top/u_hpram_sync/n359_s8/F
5.441 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/n326_s14/I0
6.473 1.032 tINS FF 1 u_hpram_top/u_hpram_sync/n326_s14/F
6.953 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/n326_s12/I1
8.052 1.099 tINS FF 1 u_hpram_top/u_hpram_sync/n326_s12/F
8.532 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/cs_memsync_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.982 0.982 tINS RR 31 clk_ibuf/O
21.345 0.363 tNET RR 1 u_hpram_top/u_hpram_sync/cs_memsync_1_s0/CLK
20.945 -0.400 tSu 1 u_hpram_top/u_hpram_sync/cs_memsync_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.329, 60.231%; route: 2.400, 33.392%; tC2Q: 0.458, 6.377%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 3

Path Summary:
Slack 12.623
Data Arrival Time 8.322
Data Required Time 20.945
From u_hpram_top/u_hpram_sync/cs_memsync_5_s0
To u_hpram_top/u_hpram_sync/flag_1_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.982 0.982 tINS RR 31 clk_ibuf/O
1.345 0.363 tNET RR 1 u_hpram_top/u_hpram_sync/cs_memsync_5_s0/CLK
1.803 0.458 tC2Q RF 7 u_hpram_top/u_hpram_sync/cs_memsync_5_s0/Q
2.283 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/n359_s11/I1
3.382 1.099 tINS FF 2 u_hpram_top/u_hpram_sync/n359_s11/F
3.862 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/n359_s8/I1
4.961 1.099 tINS FF 3 u_hpram_top/u_hpram_sync/n359_s8/F
5.441 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/n348_s7/I1
6.540 1.099 tINS FF 1 u_hpram_top/u_hpram_sync/n348_s7/F
7.020 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/n348_s5/I2
7.842 0.822 tINS FF 1 u_hpram_top/u_hpram_sync/n348_s5/F
8.322 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/flag_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.982 0.982 tINS RR 31 clk_ibuf/O
21.345 0.363 tNET RR 1 u_hpram_top/u_hpram_sync/flag_1_s0/CLK
20.945 -0.400 tSu 1 u_hpram_top/u_hpram_sync/flag_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 4.119, 59.034%; route: 2.400, 34.397%; tC2Q: 0.458, 6.569%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 4

Path Summary:
Slack 12.886
Data Arrival Time 8.059
Data Required Time 20.945
From u_hpram_top/u_hpram_sync/cs_memsync_0_s0
To u_hpram_top/u_hpram_sync/count_0_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.982 0.982 tINS RR 31 clk_ibuf/O
1.345 0.363 tNET RR 1 u_hpram_top/u_hpram_sync/cs_memsync_0_s0/CLK
1.803 0.458 tC2Q RF 5 u_hpram_top/u_hpram_sync/cs_memsync_0_s0/Q
2.283 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/n359_s10/I1
3.382 1.099 tINS FF 5 u_hpram_top/u_hpram_sync/n359_s10/F
3.862 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/n282_s17/I3
4.488 0.626 tINS FF 6 u_hpram_top/u_hpram_sync/n282_s17/F
4.968 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/n389_s4/I0
6.000 1.032 tINS FF 3 u_hpram_top/u_hpram_sync/n389_s4/F
6.480 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/n389_s3/I1
7.579 1.099 tINS FF 1 u_hpram_top/u_hpram_sync/n389_s3/F
8.059 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/count_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.982 0.982 tINS RR 31 clk_ibuf/O
21.345 0.363 tNET RR 1 u_hpram_top/u_hpram_sync/count_0_s0/CLK
20.945 -0.400 tSu 1 u_hpram_top/u_hpram_sync/count_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 3.856, 57.430%; route: 2.400, 35.744%; tC2Q: 0.458, 6.826%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%

Path 5

Path Summary:
Slack 12.886
Data Arrival Time 8.059
Data Required Time 20.945
From u_hpram_top/u_hpram_sync/cs_memsync_5_s0
To u_hpram_top/u_hpram_sync/cs_memsync_3_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.982 0.982 tINS RR 31 clk_ibuf/O
1.345 0.363 tNET RR 1 u_hpram_top/u_hpram_sync/cs_memsync_5_s0/CLK
1.803 0.458 tC2Q RF 7 u_hpram_top/u_hpram_sync/cs_memsync_5_s0/Q
2.283 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/n359_s11/I1
3.382 1.099 tINS FF 2 u_hpram_top/u_hpram_sync/n359_s11/F
3.862 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/n315_s13/I1
4.961 1.099 tINS FF 4 u_hpram_top/u_hpram_sync/n315_s13/F
5.441 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/n304_s13/I0
6.473 1.032 tINS FF 1 u_hpram_top/u_hpram_sync/n304_s13/F
6.953 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/n304_s12/I3
7.579 0.626 tINS FF 1 u_hpram_top/u_hpram_sync/n304_s12/F
8.059 0.480 tNET FF 1 u_hpram_top/u_hpram_sync/cs_memsync_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.982 0.982 tINS RR 31 clk_ibuf/O
21.345 0.363 tNET RR 1 u_hpram_top/u_hpram_sync/cs_memsync_3_s0/CLK
20.945 -0.400 tSu 1 u_hpram_top/u_hpram_sync/cs_memsync_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%
Arrival Data Path Delay: cell: 3.856, 57.430%; route: 2.400, 35.744%; tC2Q: 0.458, 6.826%
Required Clock Path Delay: cell: 0.982, 73.009%; route: 0.363, 26.991%