Timing Messages

Report Title	Timing Analysis Report
Design File	/home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/camera_hdmi/impl/gwsynthesis/camera_hdmi.vg
Physical Constraints File	/home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/camera_hdmi/src/dk_video.cst
Timing Constraint File	/home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/camera_hdmi/src/dk_video.sdc
Tool Version	V1.9.11
Part Number	GW1NSR-LV4CQN48PC6/I5
Device	GW1NSR-4C
Created Time	Wed Mar 26 11:03:55 2025
Legal Announcement	Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 1.14V 85C C6/I5
Hold Delay Model	Fast 1.26V 0C C6/I5
Numbers of Paths Analyzed	4245
Numbers of Endpoints Analyzed	2805
Numbers of Falling Endpoints	33
Numbers of Setup Violated Endpoints	642
Numbers of Hold Violated Endpoints	8

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	I_clk	Base	37.037	27.000	0.000	18.518			I_clk
2	serial_clk	Base	2.694	371.195	0.000	1.347			serial_clk
3	pix_clk	Base	13.468	74.250	0.000	6.734			pix_clk
4	ch0_vfb_clk_in	Base	20.000	50.000	0.000	10.000			ch0_vfb_clk_in_s0/F
5	GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk	Generated	6.289	159.000	0.000	3.145	I_clk_ibuf/I	I_clk	GW_PLLVR_inst/pllvr_inst/CLKOUT
6	GW_PLLVR_inst/pllvr_inst/CLKOUTP.default_gen_clk	Generated	6.289	159.000	0.000	3.145	I_clk_ibuf/I	I_clk	GW_PLLVR_inst/pllvr_inst/CLKOUTP
7	GW_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk	Generated	12.579	79.500	0.000	6.289	I_clk_ibuf/I	I_clk	GW_PLLVR_inst/pllvr_inst/CLKOUTD
8	GW_PLLVR_inst/pllvr_inst/CLKOUTD3.default_gen_clk	Generated	18.868	53.000	0.000	9.434	I_clk_ibuf/I	I_clk	GW_PLLVR_inst/pllvr_inst/CLKOUTD3
9	TMDS_PLLVR_inst/pllvr_inst/CLKOUTP.default_gen_clk	Generated	2.694	371.250	0.000	1.347	I_clk_ibuf/I	I_clk	TMDS_PLLVR_inst/pllvr_inst/CLKOUTP
10	TMDS_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk	Generated	80.808	12.375	0.000	40.404	I_clk_ibuf/I	I_clk	TMDS_PLLVR_inst/pllvr_inst/CLKOUTD
11	TMDS_PLLVR_inst/pllvr_inst/CLKOUTD3.default_gen_clk	Generated	8.081	123.750	0.000	4.040	I_clk_ibuf/I	I_clk	TMDS_PLLVR_inst/pllvr_inst/CLKOUTD3
12	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk	Generated	12.579	79.500	0.000	6.289	GW_PLLVR_inst/pllvr_inst/CLKOUT	GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	I_clk	27.000(MHz)	115.934(MHz)	5	TOP
2	pix_clk	74.250(MHz)	58.512(MHz)	9	TOP
3	ch0_vfb_clk_in	50.000(MHz)	109.123(MHz)	6	TOP
4	TMDS_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk	12.375(MHz)	83.447(MHz)	4	TOP
5	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk	79.500(MHz)	62.009(MHz)	8	TOP

No timing paths to get frequency of serial_clk!

No timing paths to get frequency of GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk!

No timing paths to get frequency of GW_PLLVR_inst/pllvr_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of GW_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk!

No timing paths to get frequency of GW_PLLVR_inst/pllvr_inst/CLKOUTD3.default_gen_clk!

No timing paths to get frequency of TMDS_PLLVR_inst/pllvr_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of TMDS_PLLVR_inst/pllvr_inst/CLKOUTD3.default_gen_clk!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
I_clk	Setup	0.000	0
I_clk	Hold	0.000	0
serial_clk	Setup	0.000	0
serial_clk	Hold	0.000	0
pix_clk	Setup	-18.973	12
pix_clk	Hold	0.000	0
ch0_vfb_clk_in	Setup	0.000	0
ch0_vfb_clk_in	Hold	0.000	0
GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk	Setup	0.000	0
GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk	Hold	0.000	0
GW_PLLVR_inst/pllvr_inst/CLKOUTP.default_gen_clk	Setup	0.000	0
GW_PLLVR_inst/pllvr_inst/CLKOUTP.default_gen_clk	Hold	0.000	0
GW_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk	Setup	0.000	0
GW_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk	Hold	0.000	0
GW_PLLVR_inst/pllvr_inst/CLKOUTD3.default_gen_clk	Setup	0.000	0
GW_PLLVR_inst/pllvr_inst/CLKOUTD3.default_gen_clk	Hold	0.000	0
TMDS_PLLVR_inst/pllvr_inst/CLKOUTP.default_gen_clk	Setup	0.000	0
TMDS_PLLVR_inst/pllvr_inst/CLKOUTP.default_gen_clk	Hold	0.000	0
TMDS_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk	Setup	0.000	0
TMDS_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk	Hold	0.000	0
TMDS_PLLVR_inst/pllvr_inst/CLKOUTD3.default_gen_clk	Setup	0.000	0
TMDS_PLLVR_inst/pllvr_inst/CLKOUTD3.default_gen_clk	Hold	0.000	0
HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk	Setup	-36.857	16
HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	-8.751	key_flag_inst/key_flag_s1/Q	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vin_vs_n_sync0_s1/D	I_clk:[R]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]	0.699	2.877	6.142
2	-8.318	key_flag_inst/key_flag_s1/Q	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_s0/D	I_clk:[R]	ch0_vfb_clk_in:[R]	0.001	2.503	5.386
3	-8.313	key_flag_inst/key_flag_s1/Q	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_den_s0/D	I_clk:[R]	ch0_vfb_clk_in:[R]	0.001	2.503	5.381
4	-8.278	key_flag_inst/key_flag_s1/Q	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d0_s0/D	I_clk:[R]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]	0.699	2.877	5.670
5	-8.122	key_flag_inst/key_flag_s1/Q	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/video_vs_n_s0/D	I_clk:[R]	ch0_vfb_clk_in:[R]	0.001	2.503	5.190
6	-5.900	key_flag_inst/key_flag_s1/Q	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_13_s0/D	I_clk:[R]	ch0_vfb_clk_in:[R]	0.001	2.503	2.968
7	-5.900	key_flag_inst/key_flag_s1/Q	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_14_s0/D	I_clk:[R]	ch0_vfb_clk_in:[R]	0.001	2.503	2.968
8	-5.895	key_flag_inst/key_flag_s1/Q	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_7_s0/D	I_clk:[R]	ch0_vfb_clk_in:[R]	0.001	2.503	2.963
9	-5.895	key_flag_inst/key_flag_s1/Q	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_8_s0/D	I_clk:[R]	ch0_vfb_clk_in:[R]	0.001	2.503	2.963
10	-5.838	key_flag_inst/key_flag_s1/Q	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_9_s0/D	I_clk:[R]	ch0_vfb_clk_in:[R]	0.001	2.503	2.906
11	-5.838	key_flag_inst/key_flag_s1/Q	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_10_s0/D	I_clk:[R]	ch0_vfb_clk_in:[R]	0.001	2.503	2.906
12	-5.838	key_flag_inst/key_flag_s1/Q	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_11_s0/D	I_clk:[R]	ch0_vfb_clk_in:[R]	0.001	2.503	2.906
13	-5.838	key_flag_inst/key_flag_s1/Q	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_12_s0/D	I_clk:[R]	ch0_vfb_clk_in:[R]	0.001	2.503	2.906
14	-5.818	key_flag_inst/key_flag_s1/Q	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_5_s0/D	I_clk:[R]	ch0_vfb_clk_in:[R]	0.001	2.503	2.886
15	-5.818	key_flag_inst/key_flag_s1/Q	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_6_s0/D	I_clk:[R]	ch0_vfb_clk_in:[R]	0.001	2.503	2.886
16	-5.804	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/cs_memsync_4_s0/Q	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CE	I_clk:[R]	GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[F]	0.349	1.176	4.693
17	-5.771	key_flag_inst/key_flag_s1/Q	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_0_s0/D	I_clk:[R]	ch0_vfb_clk_in:[R]	0.001	2.503	2.839
18	-5.771	key_flag_inst/key_flag_s1/Q	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_2_s0/D	I_clk:[R]	ch0_vfb_clk_in:[R]	0.001	2.503	2.839
19	-5.771	key_flag_inst/key_flag_s1/Q	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_3_s0/D	I_clk:[R]	ch0_vfb_clk_in:[R]	0.001	2.503	2.839
20	-5.771	key_flag_inst/key_flag_s1/Q	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_4_s0/D	I_clk:[R]	ch0_vfb_clk_in:[R]	0.001	2.503	2.839
21	-5.751	key_flag_inst/key_flag_s1/Q	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_1_s0/D	I_clk:[R]	ch0_vfb_clk_in:[R]	0.001	2.503	2.819
22	-5.751	key_flag_inst/key_flag_s1/Q	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_15_s0/D	I_clk:[R]	ch0_vfb_clk_in:[R]	0.001	2.503	2.819
23	-4.457	syn_gen_inst/O_vs_s0/Q	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d0_s0/D	pix_clk:[R]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]	0.127	-0.330	4.484
24	-4.126	syn_gen_inst/O_vs_s0/Q	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vout_vs_n_sync0_s1/D	pix_clk:[R]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]	0.127	-0.330	4.154
25	-3.698	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll/CLKIN	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_6_s0/CE	GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]	6.289	1.949	7.965

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	-1.195	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_0_s0/Q	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[3].u_ides4/CALIB	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]	GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	-2.057	0.892
2	-1.195	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_0_s0/Q	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[2].u_ides4/CALIB	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]	GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	-2.057	0.892
3	-0.608	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_0_s0/Q	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[4].u_ides4/CALIB	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]	GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	-2.057	1.479
4	-0.568	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_0_s0/Q	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[0].u_ides4/CALIB	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]	GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	-2.057	1.520
5	-0.568	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_0_s0/Q	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[1].u_ides4/CALIB	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]	GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	-2.057	1.520
6	-0.304	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_0_s0/Q	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[6].u_ides4/CALIB	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]	GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	-2.057	1.783
7	-0.304	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_0_s0/Q	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[5].u_ides4/CALIB	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]	GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	-2.057	1.783
8	-0.284	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_0_s0/Q	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[7].u_ides4/CALIB	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]	GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]	0.000	-2.057	1.804
9	0.408	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/rd_ptr_4_s1/Q	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_0_0_s/ADB[9]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.568
10	0.558	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/c_state.INIT_CALIB_DONE_s0/Q	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/init_calib_s0/CE	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.571
11	0.558	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vout_vs_n_sync2_s1/Q	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vout_vs_n_falling_r_s0/RESET	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.571
12	0.576	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_0_s1/Q	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_0_s1/D	pix_clk:[R]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]	0.000	-0.330	0.937
13	0.576	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_4_s1/Q	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_4_s1/D	pix_clk:[R]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]	0.000	-0.330	0.937
14	0.576	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_5_s1/Q	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_5_s1/D	pix_clk:[R]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]	0.000	-0.330	0.937
15	0.576	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_6_s1/Q	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_6_s1/D	pix_clk:[R]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]	0.000	-0.330	0.937
16	0.576	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_7_s1/Q	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_7_s1/D	pix_clk:[R]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]	0.000	-0.330	0.937
17	0.589	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_done_0_s0/Q	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_0_s0/CE	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]	0.000	0.000	0.602
18	0.595	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_1_s1/Q	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_1_s1/D	pix_clk:[R]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]	0.000	-0.330	0.955
19	0.595	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_2_s1/Q	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_2_s1/D	pix_clk:[R]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]	0.000	-0.330	0.955
20	0.703	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_0_s1/Q	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_0_s1/D	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]	ch0_vfb_clk_in:[R]	0.002	-0.170	0.904
21	0.708	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_7_s1/Q	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_7_s1/D	I_clk:[R]	I_clk:[R]	0.000	0.000	0.708
22	0.708	key_flag_inst/key_flag_s1/Q	key_flag_inst/key_flag_s1/D	I_clk:[R]	I_clk:[R]	0.000	0.000	0.708
23	0.708	key_flag_inst/count_20ms_reg_3_s0/Q	key_flag_inst/count_20ms_reg_3_s0/D	I_clk:[R]	I_clk:[R]	0.000	0.000	0.708
24	0.708	key_flag_inst/count_20ms_reg_20_s0/Q	key_flag_inst/count_20ms_reg_20_s0/D	I_clk:[R]	I_clk:[R]	0.000	0.000	0.708
25	0.708	testpattern_inst/V_cnt_0_s3/Q	testpattern_inst/V_cnt_0_s3/D	I_clk:[R]	I_clk:[R]	0.000	0.000	0.708

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	-8.805	u_Reset_Sync/reset_cnt_0_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_clk/RESET	I_clk:[R]	pix_clk:[R]	3.367	3.207	8.889
2	-8.805	u_Reset_Sync/reset_cnt_0_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_b/RESET	I_clk:[R]	pix_clk:[R]	3.367	3.207	8.889
3	-8.805	u_Reset_Sync/reset_cnt_0_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_g/RESET	I_clk:[R]	pix_clk:[R]	3.367	3.207	8.889
4	-8.805	u_Reset_Sync/reset_cnt_0_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_r/RESET	I_clk:[R]	pix_clk:[R]	3.367	3.207	8.889
5	-8.803	u_Reset_Sync/reset_cnt_0_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/c0_d_s0/PRESET	I_clk:[R]	pix_clk:[R]	3.367	3.207	8.889
6	-8.803	u_Reset_Sync/reset_cnt_0_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_7_s0/CLEAR	I_clk:[R]	pix_clk:[R]	3.367	3.207	8.889
7	-8.803	u_Reset_Sync/reset_cnt_0_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_0_s0/CLEAR	I_clk:[R]	pix_clk:[R]	3.367	3.207	8.889
8	-8.803	u_Reset_Sync/reset_cnt_0_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_1_s0/CLEAR	I_clk:[R]	pix_clk:[R]	3.367	3.207	8.889
9	-8.803	u_Reset_Sync/reset_cnt_0_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_2_s0/CLEAR	I_clk:[R]	pix_clk:[R]	3.367	3.207	8.889
10	-8.803	u_Reset_Sync/reset_cnt_0_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_3_s0/CLEAR	I_clk:[R]	pix_clk:[R]	3.367	3.207	8.889
11	-8.803	u_Reset_Sync/reset_cnt_0_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_4_s0/CLEAR	I_clk:[R]	pix_clk:[R]	3.367	3.207	8.889
12	-8.803	u_Reset_Sync/reset_cnt_0_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_5_s0/CLEAR	I_clk:[R]	pix_clk:[R]	3.367	3.207	8.889
13	-8.803	u_Reset_Sync/reset_cnt_0_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_6_s0/CLEAR	I_clk:[R]	pix_clk:[R]	3.367	3.207	8.889
14	-8.803	u_Reset_Sync/reset_cnt_0_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_7_s0/CLEAR	I_clk:[R]	pix_clk:[R]	3.367	3.207	8.889
15	-8.803	u_Reset_Sync/reset_cnt_0_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_8_s0/CLEAR	I_clk:[R]	pix_clk:[R]	3.367	3.207	8.889
16	-8.803	u_Reset_Sync/reset_cnt_0_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_9_s0/CLEAR	I_clk:[R]	pix_clk:[R]	3.367	3.207	8.889
17	-8.803	u_Reset_Sync/reset_cnt_0_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_1_s0/CLEAR	I_clk:[R]	pix_clk:[R]	3.367	3.207	8.889
18	-8.803	u_Reset_Sync/reset_cnt_0_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_2_s0/CLEAR	I_clk:[R]	pix_clk:[R]	3.367	3.207	8.889
19	-8.803	u_Reset_Sync/reset_cnt_0_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_3_s0/CLEAR	I_clk:[R]	pix_clk:[R]	3.367	3.207	8.889
20	-8.803	u_Reset_Sync/reset_cnt_0_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0/CLEAR	I_clk:[R]	pix_clk:[R]	3.367	3.207	8.889
21	-8.803	u_Reset_Sync/reset_cnt_0_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0/CLEAR	I_clk:[R]	pix_clk:[R]	3.367	3.207	8.889
22	-8.803	u_Reset_Sync/reset_cnt_0_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/c1_d_s0/PRESET	I_clk:[R]	pix_clk:[R]	3.367	3.207	8.889
23	-8.803	u_Reset_Sync/reset_cnt_0_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_0_s0/CLEAR	I_clk:[R]	pix_clk:[R]	3.367	3.207	8.889
24	-8.803	u_Reset_Sync/reset_cnt_0_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_1_s0/CLEAR	I_clk:[R]	pix_clk:[R]	3.367	3.207	8.889
25	-8.803	u_Reset_Sync/reset_cnt_0_s0/Q	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_2_s0/CLEAR	I_clk:[R]	pix_clk:[R]	3.367	3.207	8.889

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.781	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_rd_rst_s0/Q	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_w_0_s0/PRESET	pix_clk:[R]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[F]	-0.064	-0.338	1.098
2	0.781	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_rd_rst_s0/Q	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_w_1_s0/PRESET	pix_clk:[R]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[F]	-0.064	-0.338	1.098
3	1.293	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_s0/Q	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/PRESET	ch0_vfb_clk_in:[R]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[F]	-0.001	0.162	1.172
4	1.293	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_s0/Q	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_0_s0/PRESET	ch0_vfb_clk_in:[R]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[F]	-0.001	0.162	1.172
5	2.507	u_Reset_Sync/reset_cnt_1_s0/Q	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_0_s3/CLEAR	I_clk:[R]	I_clk:[R]	0.000	0.000	2.520
6	2.507	u_Reset_Sync/reset_cnt_1_s0/Q	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_1_s3/CLEAR	I_clk:[R]	I_clk:[R]	0.000	0.000	2.520
7	2.507	u_Reset_Sync/reset_cnt_1_s0/Q	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_4_s3/CLEAR	I_clk:[R]	I_clk:[R]	0.000	0.000	2.520
8	2.507	u_Reset_Sync/reset_cnt_1_s0/Q	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_6_s3/CLEAR	I_clk:[R]	I_clk:[R]	0.000	0.000	2.520
9	2.507	u_Reset_Sync/reset_cnt_1_s0/Q	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_12_s3/CLEAR	I_clk:[R]	I_clk:[R]	0.000	0.000	2.520
10	2.507	u_Reset_Sync/reset_cnt_1_s0/Q	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_2_s1/CLEAR	I_clk:[R]	I_clk:[R]	0.000	0.000	2.520
11	2.507	u_Reset_Sync/reset_cnt_1_s0/Q	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_3_s1/CLEAR	I_clk:[R]	I_clk:[R]	0.000	0.000	2.520
12	2.507	u_Reset_Sync/reset_cnt_1_s0/Q	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_5_s1/CLEAR	I_clk:[R]	I_clk:[R]	0.000	0.000	2.520
13	2.507	u_Reset_Sync/reset_cnt_1_s0/Q	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_7_s1/CLEAR	I_clk:[R]	I_clk:[R]	0.000	0.000	2.520
14	2.507	u_Reset_Sync/reset_cnt_1_s0/Q	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_8_s1/CLEAR	I_clk:[R]	I_clk:[R]	0.000	0.000	2.520
15	2.507	u_Reset_Sync/reset_cnt_1_s0/Q	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_9_s1/CLEAR	I_clk:[R]	I_clk:[R]	0.000	0.000	2.520
16	2.507	u_Reset_Sync/reset_cnt_1_s0/Q	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_10_s1/CLEAR	I_clk:[R]	I_clk:[R]	0.000	0.000	2.520
17	2.507	u_Reset_Sync/reset_cnt_1_s0/Q	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_11_s1/CLEAR	I_clk:[R]	I_clk:[R]	0.000	0.000	2.520
18	2.507	u_Reset_Sync/reset_cnt_1_s0/Q	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_13_s1/CLEAR	I_clk:[R]	I_clk:[R]	0.000	0.000	2.520
19	2.507	u_Reset_Sync/reset_cnt_1_s0/Q	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_14_s1/CLEAR	I_clk:[R]	I_clk:[R]	0.000	0.000	2.520
20	2.507	u_Reset_Sync/reset_cnt_1_s0/Q	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_15_s1/CLEAR	I_clk:[R]	I_clk:[R]	0.000	0.000	2.520
21	2.507	u_Reset_Sync/reset_cnt_1_s0/Q	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/cs_memsync_1_s0/PRESET	I_clk:[R]	I_clk:[R]	0.000	0.000	2.520
22	2.507	u_Reset_Sync/reset_cnt_1_s0/Q	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_syn_1_s0/CLEAR	I_clk:[R]	I_clk:[R]	0.000	0.000	2.520
23	2.507	u_Reset_Sync/reset_cnt_1_s0/Q	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/count_0_s0/CLEAR	I_clk:[R]	I_clk:[R]	0.000	0.000	2.520
24	2.507	u_Reset_Sync/reset_cnt_1_s0/Q	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/count_1_s0/CLEAR	I_clk:[R]	I_clk:[R]	0.000	0.000	2.520
25	2.507	u_Reset_Sync/reset_cnt_1_s0/Q	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/count_2_s0/CLEAR	I_clk:[R]	I_clk:[R]	0.000	0.000	2.520

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	4.965	6.215	1.250	Low Pulse Width	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_grant_i_d1_s0
2	4.965	6.215	1.250	Low Pulse Width	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_grant_i_d2_s0
3	4.965	6.215	1.250	Low Pulse Width	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_6_s1
4	4.965	6.215	1.250	Low Pulse Width	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_4_s0
5	4.965	6.215	1.250	Low Pulse Width	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/read_dog_cnt_8_s0
6	4.965	6.215	1.250	Low Pulse Width	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/read_dog_cnt_0_s0
7	4.965	6.215	1.250	Low Pulse Width	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d3_s0
8	4.965	6.215	1.250	Low Pulse Width	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d5_s0
9	4.965	6.215	1.250	Low Pulse Width	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d6_s0
10	4.965	6.215	1.250	Low Pulse Width	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d4_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	-8.751
Data Arrival Time	46.629
Data Required Time	37.878
From	key_flag_inst/key_flag_s1
To	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vin_vs_n_sync0_s1
Launch Clk	I_clk:[R]
Latch Clk	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.037	37.037					active clock edge time
37.037	0.000					I_clk
37.037	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
39.125	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
40.486	1.361	tNET	RR	1	R18C29[0][A]	key_flag_inst/key_flag_s1/CLK
40.945	0.458	tC2Q	RF	20	R18C29[0][A]	key_flag_inst/key_flag_s1/Q
43.391	2.446	tNET	FF	1	R11C23[3][B]	ch0_vfb_vs_in_s0/I2
44.213	0.822	tINS	FF	5	R11C23[3][B]	ch0_vfb_vs_in_s0/F
46.629	2.416	tNET	FF	1	R18C25[1][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vin_vs_n_sync0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.736	37.736					active clock edge time
37.736	0.000					HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
38.066	0.330	tCL	RR	620	BOTTOMSIDE[1]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
38.308	0.242	tNET	RR	1	R18C25[1][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vin_vs_n_sync0_s1/CLK
38.278	-0.030	tUnc				Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vin_vs_n_sync0_s1
37.878	-0.400	tSu		1	R18C25[1][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vin_vs_n_sync0_s1

Path Statistics:

Clock Skew	-2.877
Setup Relationship	0.699
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 0.822, 13.382%; route: 4.862, 79.156%; tC2Q: 0.458, 7.462%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path2

Path Summary:

Slack	-8.318
Data Arrival Time	1008.834
Data Required Time	1000.516
From	key_flag_inst/key_flag_s1
To	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_s0
Launch Clk	I_clk:[R]
Latch Clk	ch0_vfb_clk_in:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
999.999	999.999					active clock edge time
999.999	0.000					I_clk
999.999	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1002.087	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
1003.448	1.361	tNET	RR	1	R18C29[0][A]	key_flag_inst/key_flag_s1/CLK
1003.907	0.458	tC2Q	RF	20	R18C29[0][A]	key_flag_inst/key_flag_s1/Q
1006.353	2.446	tNET	FF	1	R11C23[3][B]	ch0_vfb_vs_in_s0/I2
1007.175	0.822	tINS	FF	5	R11C23[3][B]	ch0_vfb_vs_in_s0/F
1008.012	0.837	tNET	FF	1	R14C23[0][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/video_vs_n_rising_s0/I1
1008.834	0.822	tINS	FF	1	R14C23[0][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/video_vs_n_rising_s0/F
1008.834	0.000	tNET	FF	1	R14C23[0][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1000.000	1000.000					active clock edge time
1000.000	0.000					ch0_vfb_clk_in
1000.000	0.000	tCL	RR	63	R2C20[0][A]	ch0_vfb_clk_in_s0/F
1000.946	0.946	tNET	RR	1	R14C23[0][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_s0/CLK
1000.916	-0.030	tUnc				Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_s0
1000.516	-0.400	tSu		1	R14C23[0][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_s0

Path Statistics:

Clock Skew	-2.503
Setup Relationship	0.001
Logic Level	3
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 1.644, 30.526%; route: 3.283, 60.964%; tC2Q: 0.458, 8.510%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.946, 100.000%

Path3

Path Summary:

Slack	-8.313
Data Arrival Time	1008.829
Data Required Time	1000.516
From	key_flag_inst/key_flag_s1
To	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_den_s0
Launch Clk	I_clk:[R]
Latch Clk	ch0_vfb_clk_in:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
999.999	999.999					active clock edge time
999.999	0.000					I_clk
999.999	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1002.087	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
1003.448	1.361	tNET	RR	1	R18C29[0][A]	key_flag_inst/key_flag_s1/CLK
1003.907	0.458	tC2Q	RF	20	R18C29[0][A]	key_flag_inst/key_flag_s1/Q
1006.353	2.446	tNET	FF	1	R11C23[3][B]	ch0_vfb_vs_in_s0/I2
1007.175	0.822	tINS	FF	5	R11C23[3][B]	ch0_vfb_vs_in_s0/F
1008.007	0.832	tNET	FF	1	R12C25[2][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n16_s1/I0
1008.829	0.822	tINS	FF	1	R12C25[2][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/n16_s1/F
1008.829	0.000	tNET	FF	1	R12C25[2][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_den_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1000.000	1000.000					active clock edge time
1000.000	0.000					ch0_vfb_clk_in
1000.000	0.000	tCL	RR	63	R2C20[0][A]	ch0_vfb_clk_in_s0/F
1000.946	0.946	tNET	RR	1	R12C25[2][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_den_s0/CLK
1000.916	-0.030	tUnc				Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_den_s0
1000.516	-0.400	tSu		1	R12C25[2][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_den_s0

Path Statistics:

Clock Skew	-2.503
Setup Relationship	0.001
Logic Level	3
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 1.644, 30.552%; route: 3.279, 60.931%; tC2Q: 0.458, 8.518%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.946, 100.000%

Path4

Path Summary:

Slack	-8.278
Data Arrival Time	46.156
Data Required Time	37.878
From	key_flag_inst/key_flag_s1
To	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d0_s0
Launch Clk	I_clk:[R]
Latch Clk	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.037	37.037					active clock edge time
37.037	0.000					I_clk
37.037	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
39.125	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
40.486	1.361	tNET	RR	1	R18C29[0][A]	key_flag_inst/key_flag_s1/CLK
40.945	0.458	tC2Q	RF	20	R18C29[0][A]	key_flag_inst/key_flag_s1/Q
43.391	2.446	tNET	FF	1	R11C23[3][B]	ch0_vfb_vs_in_s0/I2
44.213	0.822	tINS	FF	5	R11C23[3][B]	ch0_vfb_vs_in_s0/F
46.156	1.943	tNET	FF	1	R14C24[1][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.736	37.736					active clock edge time
37.736	0.000					HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
38.066	0.330	tCL	RR	620	BOTTOMSIDE[1]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
38.308	0.242	tNET	RR	1	R14C24[1][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d0_s0/CLK
38.278	-0.030	tUnc				Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d0_s0
37.878	-0.400	tSu		1	R14C24[1][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_vs_n_d0_s0

Path Statistics:

Clock Skew	-2.877
Setup Relationship	0.699
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 0.822, 14.498%; route: 4.389, 77.418%; tC2Q: 0.458, 8.084%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path5

Path Summary:

Slack	-8.122
Data Arrival Time	1008.638
Data Required Time	1000.516
From	key_flag_inst/key_flag_s1
To	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/video_vs_n_s0
Launch Clk	I_clk:[R]
Latch Clk	ch0_vfb_clk_in:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
999.999	999.999					active clock edge time
999.999	0.000					I_clk
999.999	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1002.087	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
1003.448	1.361	tNET	RR	1	R18C29[0][A]	key_flag_inst/key_flag_s1/CLK
1003.907	0.458	tC2Q	RF	20	R18C29[0][A]	key_flag_inst/key_flag_s1/Q
1006.353	2.446	tNET	FF	1	R11C23[3][B]	ch0_vfb_vs_in_s0/I2
1007.175	0.822	tINS	FF	5	R11C23[3][B]	ch0_vfb_vs_in_s0/F
1008.638	1.463	tNET	FF	1	R14C23[2][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/video_vs_n_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1000.000	1000.000					active clock edge time
1000.000	0.000					ch0_vfb_clk_in
1000.000	0.000	tCL	RR	63	R2C20[0][A]	ch0_vfb_clk_in_s0/F
1000.946	0.946	tNET	RR	1	R14C23[2][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/video_vs_n_s0/CLK
1000.916	-0.030	tUnc				Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/video_vs_n_s0
1000.516	-0.400	tSu		1	R14C23[2][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/video_vs_n_s0

Path Statistics:

Clock Skew	-2.503
Setup Relationship	0.001
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 0.822, 15.839%; route: 3.909, 75.329%; tC2Q: 0.458, 8.832%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.946, 100.000%

Path6

Path Summary:

Slack	-5.900
Data Arrival Time	1006.416
Data Required Time	1000.516
From	key_flag_inst/key_flag_s1
To	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_13_s0
Launch Clk	I_clk:[R]
Latch Clk	ch0_vfb_clk_in:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
999.999	999.999					active clock edge time
999.999	0.000					I_clk
999.999	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1002.087	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
1003.448	1.361	tNET	RR	1	R18C29[0][A]	key_flag_inst/key_flag_s1/CLK
1003.907	0.458	tC2Q	RF	20	R18C29[0][A]	key_flag_inst/key_flag_s1/Q
1005.384	1.477	tNET	FF	1	R6C31[1][A]	ch0_vfb_data_in_13_s0/I2
1006.416	1.032	tINS	FF	1	R6C31[1][A]	ch0_vfb_data_in_13_s0/F
1006.416	0.000	tNET	FF	1	R6C31[1][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1000.000	1000.000					active clock edge time
1000.000	0.000					ch0_vfb_clk_in
1000.000	0.000	tCL	RR	63	R2C20[0][A]	ch0_vfb_clk_in_s0/F
1000.946	0.946	tNET	RR	1	R6C31[1][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_13_s0/CLK
1000.916	-0.030	tUnc				Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_13_s0
1000.516	-0.400	tSu		1	R6C31[1][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_13_s0

Path Statistics:

Clock Skew	-2.503
Setup Relationship	0.001
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 1.032, 34.777%; route: 1.477, 49.778%; tC2Q: 0.458, 15.445%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.946, 100.000%

Path7

Path Summary:

Slack	-5.900
Data Arrival Time	1006.416
Data Required Time	1000.516
From	key_flag_inst/key_flag_s1
To	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_14_s0
Launch Clk	I_clk:[R]
Latch Clk	ch0_vfb_clk_in:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
999.999	999.999					active clock edge time
999.999	0.000					I_clk
999.999	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1002.087	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
1003.448	1.361	tNET	RR	1	R18C29[0][A]	key_flag_inst/key_flag_s1/CLK
1003.907	0.458	tC2Q	RF	20	R18C29[0][A]	key_flag_inst/key_flag_s1/Q
1005.384	1.477	tNET	FF	1	R6C31[0][A]	ch0_vfb_data_in_14_s0/I2
1006.416	1.032	tINS	FF	1	R6C31[0][A]	ch0_vfb_data_in_14_s0/F
1006.416	0.000	tNET	FF	1	R6C31[0][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1000.000	1000.000					active clock edge time
1000.000	0.000					ch0_vfb_clk_in
1000.000	0.000	tCL	RR	63	R2C20[0][A]	ch0_vfb_clk_in_s0/F
1000.946	0.946	tNET	RR	1	R6C31[0][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_14_s0/CLK
1000.916	-0.030	tUnc				Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_14_s0
1000.516	-0.400	tSu		1	R6C31[0][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_14_s0

Path Statistics:

Clock Skew	-2.503
Setup Relationship	0.001
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 1.032, 34.777%; route: 1.477, 49.778%; tC2Q: 0.458, 15.445%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.946, 100.000%

Path8

Path Summary:

Slack	-5.895
Data Arrival Time	1006.411
Data Required Time	1000.516
From	key_flag_inst/key_flag_s1
To	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_7_s0
Launch Clk	I_clk:[R]
Latch Clk	ch0_vfb_clk_in:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
999.999	999.999					active clock edge time
999.999	0.000					I_clk
999.999	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1002.087	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
1003.448	1.361	tNET	RR	1	R18C29[0][A]	key_flag_inst/key_flag_s1/CLK
1003.907	0.458	tC2Q	RF	20	R18C29[0][A]	key_flag_inst/key_flag_s1/Q
1005.379	1.473	tNET	FF	1	R6C26[0][A]	ch0_vfb_data_in_7_s0/I2
1006.411	1.032	tINS	FF	1	R6C26[0][A]	ch0_vfb_data_in_7_s0/F
1006.411	0.000	tNET	FF	1	R6C26[0][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1000.000	1000.000					active clock edge time
1000.000	0.000					ch0_vfb_clk_in
1000.000	0.000	tCL	RR	63	R2C20[0][A]	ch0_vfb_clk_in_s0/F
1000.946	0.946	tNET	RR	1	R6C26[0][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_7_s0/CLK
1000.916	-0.030	tUnc				Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_7_s0
1000.516	-0.400	tSu		1	R6C26[0][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_7_s0

Path Statistics:

Clock Skew	-2.503
Setup Relationship	0.001
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 1.032, 34.830%; route: 1.473, 49.701%; tC2Q: 0.458, 15.469%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.946, 100.000%

Path9

Path Summary:

Slack	-5.895
Data Arrival Time	1006.411
Data Required Time	1000.516
From	key_flag_inst/key_flag_s1
To	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_8_s0
Launch Clk	I_clk:[R]
Latch Clk	ch0_vfb_clk_in:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
999.999	999.999					active clock edge time
999.999	0.000					I_clk
999.999	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1002.087	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
1003.448	1.361	tNET	RR	1	R18C29[0][A]	key_flag_inst/key_flag_s1/CLK
1003.907	0.458	tC2Q	RF	20	R18C29[0][A]	key_flag_inst/key_flag_s1/Q
1005.379	1.473	tNET	FF	1	R7C31[0][A]	ch0_vfb_data_in_8_s0/I2
1006.411	1.032	tINS	FF	1	R7C31[0][A]	ch0_vfb_data_in_8_s0/F
1006.411	0.000	tNET	FF	1	R7C31[0][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1000.000	1000.000					active clock edge time
1000.000	0.000					ch0_vfb_clk_in
1000.000	0.000	tCL	RR	63	R2C20[0][A]	ch0_vfb_clk_in_s0/F
1000.946	0.946	tNET	RR	1	R7C31[0][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_8_s0/CLK
1000.916	-0.030	tUnc				Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_8_s0
1000.516	-0.400	tSu		1	R7C31[0][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_8_s0

Path Statistics:

Clock Skew	-2.503
Setup Relationship	0.001
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 1.032, 34.830%; route: 1.473, 49.701%; tC2Q: 0.458, 15.469%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.946, 100.000%

Path10

Path Summary:

Slack	-5.838
Data Arrival Time	1006.354
Data Required Time	1000.516
From	key_flag_inst/key_flag_s1
To	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_9_s0
Launch Clk	I_clk:[R]
Latch Clk	ch0_vfb_clk_in:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
999.999	999.999					active clock edge time
999.999	0.000					I_clk
999.999	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1002.087	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
1003.448	1.361	tNET	RR	1	R18C29[0][A]	key_flag_inst/key_flag_s1/CLK
1003.907	0.458	tC2Q	RF	20	R18C29[0][A]	key_flag_inst/key_flag_s1/Q
1005.255	1.348	tNET	FF	1	R6C28[1][A]	ch0_vfb_data_in_9_s0/I2
1006.354	1.099	tINS	FF	1	R6C28[1][A]	ch0_vfb_data_in_9_s0/F
1006.354	0.000	tNET	FF	1	R6C28[1][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1000.000	1000.000					active clock edge time
1000.000	0.000					ch0_vfb_clk_in
1000.000	0.000	tCL	RR	63	R2C20[0][A]	ch0_vfb_clk_in_s0/F
1000.946	0.946	tNET	RR	1	R6C28[1][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_9_s0/CLK
1000.916	-0.030	tUnc				Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_9_s0
1000.516	-0.400	tSu		1	R6C28[1][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_9_s0

Path Statistics:

Clock Skew	-2.503
Setup Relationship	0.001
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 1.099, 37.823%; route: 1.348, 46.403%; tC2Q: 0.458, 15.774%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.946, 100.000%

Path11

Path Summary:

Slack	-5.838
Data Arrival Time	1006.354
Data Required Time	1000.516
From	key_flag_inst/key_flag_s1
To	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_10_s0
Launch Clk	I_clk:[R]
Latch Clk	ch0_vfb_clk_in:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
999.999	999.999					active clock edge time
999.999	0.000					I_clk
999.999	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1002.087	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
1003.448	1.361	tNET	RR	1	R18C29[0][A]	key_flag_inst/key_flag_s1/CLK
1003.907	0.458	tC2Q	RF	20	R18C29[0][A]	key_flag_inst/key_flag_s1/Q
1005.255	1.348	tNET	FF	1	R6C28[1][B]	ch0_vfb_data_in_10_s0/I2
1006.354	1.099	tINS	FF	1	R6C28[1][B]	ch0_vfb_data_in_10_s0/F
1006.354	0.000	tNET	FF	1	R6C28[1][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1000.000	1000.000					active clock edge time
1000.000	0.000					ch0_vfb_clk_in
1000.000	0.000	tCL	RR	63	R2C20[0][A]	ch0_vfb_clk_in_s0/F
1000.946	0.946	tNET	RR	1	R6C28[1][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_10_s0/CLK
1000.916	-0.030	tUnc				Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_10_s0
1000.516	-0.400	tSu		1	R6C28[1][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_10_s0

Path Statistics:

Clock Skew	-2.503
Setup Relationship	0.001
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 1.099, 37.823%; route: 1.348, 46.403%; tC2Q: 0.458, 15.774%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.946, 100.000%

Path12

Path Summary:

Slack	-5.838
Data Arrival Time	1006.354
Data Required Time	1000.516
From	key_flag_inst/key_flag_s1
To	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_11_s0
Launch Clk	I_clk:[R]
Latch Clk	ch0_vfb_clk_in:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
999.999	999.999					active clock edge time
999.999	0.000					I_clk
999.999	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1002.087	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
1003.448	1.361	tNET	RR	1	R18C29[0][A]	key_flag_inst/key_flag_s1/CLK
1003.907	0.458	tC2Q	RF	20	R18C29[0][A]	key_flag_inst/key_flag_s1/Q
1005.255	1.348	tNET	FF	1	R6C29[2][A]	ch0_vfb_data_in_11_s0/I2
1006.354	1.099	tINS	FF	1	R6C29[2][A]	ch0_vfb_data_in_11_s0/F
1006.354	0.000	tNET	FF	1	R6C29[2][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1000.000	1000.000					active clock edge time
1000.000	0.000					ch0_vfb_clk_in
1000.000	0.000	tCL	RR	63	R2C20[0][A]	ch0_vfb_clk_in_s0/F
1000.946	0.946	tNET	RR	1	R6C29[2][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_11_s0/CLK
1000.916	-0.030	tUnc				Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_11_s0
1000.516	-0.400	tSu		1	R6C29[2][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_11_s0

Path Statistics:

Clock Skew	-2.503
Setup Relationship	0.001
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 1.099, 37.823%; route: 1.348, 46.403%; tC2Q: 0.458, 15.774%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.946, 100.000%

Path13

Path Summary:

Slack	-5.838
Data Arrival Time	1006.354
Data Required Time	1000.516
From	key_flag_inst/key_flag_s1
To	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_12_s0
Launch Clk	I_clk:[R]
Latch Clk	ch0_vfb_clk_in:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
999.999	999.999					active clock edge time
999.999	0.000					I_clk
999.999	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1002.087	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
1003.448	1.361	tNET	RR	1	R18C29[0][A]	key_flag_inst/key_flag_s1/CLK
1003.907	0.458	tC2Q	RF	20	R18C29[0][A]	key_flag_inst/key_flag_s1/Q
1005.255	1.348	tNET	FF	1	R6C29[2][B]	ch0_vfb_data_in_12_s0/I2
1006.354	1.099	tINS	FF	1	R6C29[2][B]	ch0_vfb_data_in_12_s0/F
1006.354	0.000	tNET	FF	1	R6C29[2][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1000.000	1000.000					active clock edge time
1000.000	0.000					ch0_vfb_clk_in
1000.000	0.000	tCL	RR	63	R2C20[0][A]	ch0_vfb_clk_in_s0/F
1000.946	0.946	tNET	RR	1	R6C29[2][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_12_s0/CLK
1000.916	-0.030	tUnc				Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_12_s0
1000.516	-0.400	tSu		1	R6C29[2][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_12_s0

Path Statistics:

Clock Skew	-2.503
Setup Relationship	0.001
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 1.099, 37.823%; route: 1.348, 46.403%; tC2Q: 0.458, 15.774%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.946, 100.000%

Path14

Path Summary:

Slack	-5.818
Data Arrival Time	1006.334
Data Required Time	1000.516
From	key_flag_inst/key_flag_s1
To	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_5_s0
Launch Clk	I_clk:[R]
Latch Clk	ch0_vfb_clk_in:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
999.999	999.999					active clock edge time
999.999	0.000					I_clk
999.999	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1002.087	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
1003.448	1.361	tNET	RR	1	R18C29[0][A]	key_flag_inst/key_flag_s1/CLK
1003.907	0.458	tC2Q	RF	20	R18C29[0][A]	key_flag_inst/key_flag_s1/Q
1005.235	1.329	tNET	FF	1	R7C28[2][B]	ch0_vfb_data_in_5_s0/I2
1006.334	1.099	tINS	FF	1	R7C28[2][B]	ch0_vfb_data_in_5_s0/F
1006.334	0.000	tNET	FF	1	R7C28[2][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1000.000	1000.000					active clock edge time
1000.000	0.000					ch0_vfb_clk_in
1000.000	0.000	tCL	RR	63	R2C20[0][A]	ch0_vfb_clk_in_s0/F
1000.946	0.946	tNET	RR	1	R7C28[2][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_5_s0/CLK
1000.916	-0.030	tUnc				Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_5_s0
1000.516	-0.400	tSu		1	R7C28[2][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_5_s0

Path Statistics:

Clock Skew	-2.503
Setup Relationship	0.001
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 1.099, 38.080%; route: 1.329, 46.039%; tC2Q: 0.458, 15.881%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.946, 100.000%

Path15

Path Summary:

Slack	-5.818
Data Arrival Time	1006.334
Data Required Time	1000.516
From	key_flag_inst/key_flag_s1
To	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_6_s0
Launch Clk	I_clk:[R]
Latch Clk	ch0_vfb_clk_in:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
999.999	999.999					active clock edge time
999.999	0.000					I_clk
999.999	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1002.087	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
1003.448	1.361	tNET	RR	1	R18C29[0][A]	key_flag_inst/key_flag_s1/CLK
1003.907	0.458	tC2Q	RF	20	R18C29[0][A]	key_flag_inst/key_flag_s1/Q
1005.235	1.329	tNET	FF	1	R6C30[2][A]	ch0_vfb_data_in_6_s0/I2
1006.334	1.099	tINS	FF	1	R6C30[2][A]	ch0_vfb_data_in_6_s0/F
1006.334	0.000	tNET	FF	1	R6C30[2][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1000.000	1000.000					active clock edge time
1000.000	0.000					ch0_vfb_clk_in
1000.000	0.000	tCL	RR	63	R2C20[0][A]	ch0_vfb_clk_in_s0/F
1000.946	0.946	tNET	RR	1	R6C30[2][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_6_s0/CLK
1000.916	-0.030	tUnc				Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_6_s0
1000.516	-0.400	tSu		1	R6C30[2][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_6_s0

Path Statistics:

Clock Skew	-2.503
Setup Relationship	0.001
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 1.099, 38.080%; route: 1.329, 46.039%; tC2Q: 0.458, 15.881%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.946, 100.000%

Path16

Path Summary:

Slack	-5.804
Data Arrival Time	193.328
Data Required Time	187.524
From	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/cs_memsync_4_s0
To	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p
Launch Clk	I_clk:[R]
Latch Clk	GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
185.185	185.185					active clock edge time
185.185	0.000					I_clk
185.185	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
187.273	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
188.634	1.361	tNET	RR	1	R4C10[0][B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/cs_memsync_4_s0/CLK
189.093	0.458	tC2Q	RF	8	R4C10[0][B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/cs_memsync_4_s0/Q
193.328	4.235	tNET	FF	1	R21C0	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
185.534	185.534					active clock edge time
185.534	0.000					GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
187.808	2.273	tCL	FF	1	PLL_L	GW_PLLVR_inst/pllvr_inst/CLKOUT
187.808	0.000	tNET	FF	3	R21C0	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKIN
187.778	-0.030	tUnc				HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p
187.524	-0.254	tSu		1	R21C0	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p

Path Statistics:

Clock Skew	-1.176
Setup Relationship	0.349
Logic Level	1
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 4.235, 90.235%; tC2Q: 0.458, 9.765%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%

Path17

Path Summary:

Slack	-5.771
Data Arrival Time	1006.287
Data Required Time	1000.516
From	key_flag_inst/key_flag_s1
To	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_0_s0
Launch Clk	I_clk:[R]
Latch Clk	ch0_vfb_clk_in:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
999.999	999.999					active clock edge time
999.999	0.000					I_clk
999.999	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1002.087	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
1003.448	1.361	tNET	RR	1	R18C29[0][A]	key_flag_inst/key_flag_s1/CLK
1003.907	0.458	tC2Q	RF	20	R18C29[0][A]	key_flag_inst/key_flag_s1/Q
1005.255	1.348	tNET	FF	1	R6C29[0][A]	ch0_vfb_data_in_0_s0/I2
1006.287	1.032	tINS	FF	1	R6C29[0][A]	ch0_vfb_data_in_0_s0/F
1006.287	0.000	tNET	FF	1	R6C29[0][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1000.000	1000.000					active clock edge time
1000.000	0.000					ch0_vfb_clk_in
1000.000	0.000	tCL	RR	63	R2C20[0][A]	ch0_vfb_clk_in_s0/F
1000.946	0.946	tNET	RR	1	R6C29[0][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_0_s0/CLK
1000.916	-0.030	tUnc				Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_0_s0
1000.516	-0.400	tSu		1	R6C29[0][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_0_s0

Path Statistics:

Clock Skew	-2.503
Setup Relationship	0.001
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 1.032, 36.355%; route: 1.348, 47.498%; tC2Q: 0.458, 16.146%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.946, 100.000%

Path18

Path Summary:

Slack	-5.771
Data Arrival Time	1006.287
Data Required Time	1000.516
From	key_flag_inst/key_flag_s1
To	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_2_s0
Launch Clk	I_clk:[R]
Latch Clk	ch0_vfb_clk_in:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
999.999	999.999					active clock edge time
999.999	0.000					I_clk
999.999	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1002.087	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
1003.448	1.361	tNET	RR	1	R18C29[0][A]	key_flag_inst/key_flag_s1/CLK
1003.907	0.458	tC2Q	RF	20	R18C29[0][A]	key_flag_inst/key_flag_s1/Q
1005.255	1.348	tNET	FF	1	R6C29[0][B]	ch0_vfb_data_in_2_s0/I2
1006.287	1.032	tINS	FF	1	R6C29[0][B]	ch0_vfb_data_in_2_s0/F
1006.287	0.000	tNET	FF	1	R6C29[0][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1000.000	1000.000					active clock edge time
1000.000	0.000					ch0_vfb_clk_in
1000.000	0.000	tCL	RR	63	R2C20[0][A]	ch0_vfb_clk_in_s0/F
1000.946	0.946	tNET	RR	1	R6C29[0][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_2_s0/CLK
1000.916	-0.030	tUnc				Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_2_s0
1000.516	-0.400	tSu		1	R6C29[0][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_2_s0

Path Statistics:

Clock Skew	-2.503
Setup Relationship	0.001
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 1.032, 36.355%; route: 1.348, 47.498%; tC2Q: 0.458, 16.146%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.946, 100.000%

Path19

Path Summary:

Slack	-5.771
Data Arrival Time	1006.287
Data Required Time	1000.516
From	key_flag_inst/key_flag_s1
To	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_3_s0
Launch Clk	I_clk:[R]
Latch Clk	ch0_vfb_clk_in:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
999.999	999.999					active clock edge time
999.999	0.000					I_clk
999.999	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1002.087	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
1003.448	1.361	tNET	RR	1	R18C29[0][A]	key_flag_inst/key_flag_s1/CLK
1003.907	0.458	tC2Q	RF	20	R18C29[0][A]	key_flag_inst/key_flag_s1/Q
1005.255	1.348	tNET	FF	1	R6C28[0][A]	ch0_vfb_data_in_3_s0/I2
1006.287	1.032	tINS	FF	1	R6C28[0][A]	ch0_vfb_data_in_3_s0/F
1006.287	0.000	tNET	FF	1	R6C28[0][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1000.000	1000.000					active clock edge time
1000.000	0.000					ch0_vfb_clk_in
1000.000	0.000	tCL	RR	63	R2C20[0][A]	ch0_vfb_clk_in_s0/F
1000.946	0.946	tNET	RR	1	R6C28[0][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_3_s0/CLK
1000.916	-0.030	tUnc				Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_3_s0
1000.516	-0.400	tSu		1	R6C28[0][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_3_s0

Path Statistics:

Clock Skew	-2.503
Setup Relationship	0.001
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 1.032, 36.355%; route: 1.348, 47.498%; tC2Q: 0.458, 16.146%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.946, 100.000%

Path20

Path Summary:

Slack	-5.771
Data Arrival Time	1006.287
Data Required Time	1000.516
From	key_flag_inst/key_flag_s1
To	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_4_s0
Launch Clk	I_clk:[R]
Latch Clk	ch0_vfb_clk_in:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
999.999	999.999					active clock edge time
999.999	0.000					I_clk
999.999	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1002.087	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
1003.448	1.361	tNET	RR	1	R18C29[0][A]	key_flag_inst/key_flag_s1/CLK
1003.907	0.458	tC2Q	RF	20	R18C29[0][A]	key_flag_inst/key_flag_s1/Q
1005.255	1.348	tNET	FF	1	R6C28[0][B]	ch0_vfb_data_in_4_s0/I2
1006.287	1.032	tINS	FF	1	R6C28[0][B]	ch0_vfb_data_in_4_s0/F
1006.287	0.000	tNET	FF	1	R6C28[0][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1000.000	1000.000					active clock edge time
1000.000	0.000					ch0_vfb_clk_in
1000.000	0.000	tCL	RR	63	R2C20[0][A]	ch0_vfb_clk_in_s0/F
1000.946	0.946	tNET	RR	1	R6C28[0][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_4_s0/CLK
1000.916	-0.030	tUnc				Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_4_s0
1000.516	-0.400	tSu		1	R6C28[0][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_4_s0

Path Statistics:

Clock Skew	-2.503
Setup Relationship	0.001
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 1.032, 36.355%; route: 1.348, 47.498%; tC2Q: 0.458, 16.146%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.946, 100.000%

Path21

Path Summary:

Slack	-5.751
Data Arrival Time	1006.267
Data Required Time	1000.516
From	key_flag_inst/key_flag_s1
To	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_1_s0
Launch Clk	I_clk:[R]
Latch Clk	ch0_vfb_clk_in:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
999.999	999.999					active clock edge time
999.999	0.000					I_clk
999.999	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1002.087	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
1003.448	1.361	tNET	RR	1	R18C29[0][A]	key_flag_inst/key_flag_s1/CLK
1003.907	0.458	tC2Q	RF	20	R18C29[0][A]	key_flag_inst/key_flag_s1/Q
1005.235	1.329	tNET	FF	1	R7C28[0][A]	ch0_vfb_data_in_1_s0/I2
1006.267	1.032	tINS	FF	1	R7C28[0][A]	ch0_vfb_data_in_1_s0/F
1006.267	0.000	tNET	FF	1	R7C28[0][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1000.000	1000.000					active clock edge time
1000.000	0.000					ch0_vfb_clk_in
1000.000	0.000	tCL	RR	63	R2C20[0][A]	ch0_vfb_clk_in_s0/F
1000.946	0.946	tNET	RR	1	R7C28[0][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_1_s0/CLK
1000.916	-0.030	tUnc				Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_1_s0
1000.516	-0.400	tSu		1	R7C28[0][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_1_s0

Path Statistics:

Clock Skew	-2.503
Setup Relationship	0.001
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 1.032, 36.609%; route: 1.329, 47.133%; tC2Q: 0.458, 16.259%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.946, 100.000%

Path22

Path Summary:

Slack	-5.751
Data Arrival Time	1006.267
Data Required Time	1000.516
From	key_flag_inst/key_flag_s1
To	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_15_s0
Launch Clk	I_clk:[R]
Latch Clk	ch0_vfb_clk_in:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
999.999	999.999					active clock edge time
999.999	0.000					I_clk
999.999	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1002.087	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
1003.448	1.361	tNET	RR	1	R18C29[0][A]	key_flag_inst/key_flag_s1/CLK
1003.907	0.458	tC2Q	RF	20	R18C29[0][A]	key_flag_inst/key_flag_s1/Q
1005.235	1.329	tNET	FF	1	R6C30[0][A]	ch0_vfb_data_in_15_s0/I2
1006.267	1.032	tINS	FF	1	R6C30[0][A]	ch0_vfb_data_in_15_s0/F
1006.267	0.000	tNET	FF	1	R6C30[0][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_15_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1000.000	1000.000					active clock edge time
1000.000	0.000					ch0_vfb_clk_in
1000.000	0.000	tCL	RR	63	R2C20[0][A]	ch0_vfb_clk_in_s0/F
1000.946	0.946	tNET	RR	1	R6C30[0][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_15_s0/CLK
1000.916	-0.030	tUnc				Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_15_s0
1000.516	-0.400	tSu		1	R6C30[0][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_data_15_s0

Path Statistics:

Clock Skew	-2.503
Setup Relationship	0.001
Logic Level	2
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 1.032, 36.609%; route: 1.329, 47.133%; tC2Q: 0.458, 16.259%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.946, 100.000%

Path23

Path Summary:

Slack	-4.457
Data Arrival Time	193.278
Data Required Time	188.821
From	syn_gen_inst/O_vs_s0
To	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d0_s0
Launch Clk	pix_clk:[R]
Latch Clk	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
188.552	188.552					active clock edge time
188.552	0.000					pix_clk
188.552	0.000	tCL	RR	176	RIGHTSIDE[1]	u_clkdiv/CLKOUT
188.794	0.242	tNET	RR	1	R18C35[0][A]	syn_gen_inst/O_vs_s0/CLK
189.252	0.458	tC2Q	RF	2	R18C35[0][A]	syn_gen_inst/O_vs_s0/Q
191.195	1.942	tNET	FF	1	R17C20[1][A]	n259_s2/I0
191.821	0.626	tINS	FF	4	R17C20[1][A]	n259_s2/F
193.278	1.458	tNET	FF	1	R15C20[2][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
188.679	188.679					active clock edge time
188.679	0.000					HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
189.009	0.330	tCL	RR	620	BOTTOMSIDE[1]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
189.251	0.242	tNET	RR	1	R15C20[2][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d0_s0/CLK
189.221	-0.030	tUnc				Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d0_s0
188.821	-0.400	tSu		1	R15C20[2][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d0_s0

Path Statistics:

Clock Skew	0.330
Setup Relationship	0.127
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 0.626, 13.960%; route: 3.400, 75.820%; tC2Q: 0.458, 10.221%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path24

Path Summary:

Slack	-4.126
Data Arrival Time	192.948
Data Required Time	188.821
From	syn_gen_inst/O_vs_s0
To	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vout_vs_n_sync0_s1
Launch Clk	pix_clk:[R]
Latch Clk	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
188.552	188.552					active clock edge time
188.552	0.000					pix_clk
188.552	0.000	tCL	RR	176	RIGHTSIDE[1]	u_clkdiv/CLKOUT
188.794	0.242	tNET	RR	1	R18C35[0][A]	syn_gen_inst/O_vs_s0/CLK
189.252	0.458	tC2Q	RF	2	R18C35[0][A]	syn_gen_inst/O_vs_s0/Q
191.195	1.942	tNET	FF	1	R17C20[1][A]	n259_s2/I0
191.821	0.626	tINS	FF	4	R17C20[1][A]	n259_s2/F
192.948	1.127	tNET	FF	1	R17C19[2][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vout_vs_n_sync0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
188.679	188.679					active clock edge time
188.679	0.000					HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
189.009	0.330	tCL	RR	620	BOTTOMSIDE[1]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
189.251	0.242	tNET	RR	1	R17C19[2][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vout_vs_n_sync0_s1/CLK
189.221	-0.030	tUnc				Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vout_vs_n_sync0_s1
188.821	-0.400	tSu		1	R17C19[2][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vout_vs_n_sync0_s1

Path Statistics:

Clock Skew	0.330
Setup Relationship	0.127
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%
Arrival Data Path Delay	cell: 0.626, 15.071%; route: 3.069, 73.894%; tC2Q: 0.458, 11.035%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path25

Path Summary:

Slack	-3.698
Data Arrival Time	16.775
Data Required Time	13.077
From	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll
To	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_6_s0
Launch Clk	GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]
Latch Clk	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
6.289	6.289					active clock edge time
6.289	0.000					GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
8.562	2.273	tCL	RR	1	PLL_L	GW_PLLVR_inst/pllvr_inst/CLKOUT
8.562	0.000	tNET	RR	3	R21C0	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKIN
8.811	0.248	tINS	RR	22	R21C0	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKOUT
8.926	0.115	tNET	RR	8	DLL_BL	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll/CLKIN
9.492	0.566	tINS	RF	1	DLL_BL	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dll/STEP[0]
13.394	3.902	tNET	FF	2	R18C5[0][B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/n193_s19/I1
13.944	0.550	tINS	FR	1	R18C5[0][B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/n193_s19/COUT
13.944	0.000	tNET	RR	2	R18C5[1][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/n193_s20/CIN
14.001	0.057	tINS	RF	1	R18C5[1][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/n193_s20/COUT
14.001	0.000	tNET	FF	2	R18C5[1][B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/n193_s21/CIN
14.058	0.057	tINS	FF	1	R18C5[1][B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/n193_s21/COUT
14.058	0.000	tNET	FF	2	R18C5[2][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/n193_s22/CIN
14.115	0.057	tINS	FF	1	R18C5[2][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/n193_s22/COUT
14.115	0.000	tNET	FF	2	R18C5[2][B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/n193_s23/CIN
14.172	0.057	tINS	FF	1	R18C5[2][B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/n193_s23/COUT
14.172	0.000	tNET	FF	2	R18C6[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/n193_s24/CIN
14.229	0.057	tINS	FF	1	R18C6[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/n193_s24/COUT
14.229	0.000	tNET	FF	2	R18C6[0][B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/n193_s25/CIN
14.286	0.057	tINS	FF	1	R18C6[0][B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/n193_s25/COUT
14.286	0.000	tNET	FF	2	R18C6[1][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/n193_s26/CIN
14.343	0.057	tINS	FF	2	R18C6[1][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/n193_s26/COUT
14.917	0.574	tNET	FF	1	R18C6[3][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/n259_s1/I0
15.978	1.061	tINS	FR	8	R18C6[3][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/n259_s1/F
16.775	0.798	tNET	RR	1	R18C7[2][B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_6_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.579	12.579					active clock edge time
12.579	0.000					HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
12.909	0.330	tCL	RR	620	BOTTOMSIDE[1]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
13.151	0.242	tNET	RR	1	R18C7[2][B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_6_s0/CLK
13.121	-0.030	tUnc				HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_6_s0
13.077	-0.043	tSu		1	R18C7[2][B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/step_6_s0

Path Statistics:

Clock Skew	-1.949
Setup Relationship	6.289
Logic Level	6
Arrival Clock Path Delay	cell: 0.248, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay	cell: 2.576, 32.346%; route: 5.273, 66.211%; tC2Q: 0.115, 1.443%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	-1.195
Data Arrival Time	1.405
Data Required Time	2.600
From	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_0_s0
To	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[3].u_ides4
Launch Clk	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	620	BOTTOMSIDE[1]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513	0.183	tNET	RR	1	R11C14[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_0_s0/CLK
0.846	0.333	tC2Q	RR	11	R11C14[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_0_s0/Q
1.405	0.559	tNET	RR	1	IOB14[B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[3].u_ides4/CALIB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	1	PLL_L	GW_PLLVR_inst/pllvr_inst/CLKOUT
2.273	0.000	tNET	RR	3	R21C0	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKIN
2.486	0.213	tINS	RR	22	R21C0	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKOUT
2.570	0.085	tNET	RR	1	IOB14[B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[3].u_ides4/FCLK
2.600	0.030	tUnc				HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[3].u_ides4
2.600	0.000	tHld		1	IOB14[B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[3].u_ides4

Path Statistics:

Clock Skew	2.057
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.559, 62.627%; tC2Q: 0.333, 37.373%
Required Clock Path Delay	cell: 0.213, 71.550%; route: 0.085, 28.450%

Path2

Path Summary:

Slack	-1.195
Data Arrival Time	1.405
Data Required Time	2.600
From	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_0_s0
To	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[2].u_ides4
Launch Clk	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	620	BOTTOMSIDE[1]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513	0.183	tNET	RR	1	R11C14[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_0_s0/CLK
0.846	0.333	tC2Q	RR	11	R11C14[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_0_s0/Q
1.405	0.559	tNET	RR	1	IOB14[A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[2].u_ides4/CALIB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	1	PLL_L	GW_PLLVR_inst/pllvr_inst/CLKOUT
2.273	0.000	tNET	RR	3	R21C0	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKIN
2.486	0.213	tINS	RR	22	R21C0	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKOUT
2.570	0.085	tNET	RR	1	IOB14[A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[2].u_ides4/FCLK
2.600	0.030	tUnc				HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[2].u_ides4
2.600	0.000	tHld		1	IOB14[A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[2].u_ides4

Path Statistics:

Clock Skew	2.057
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.559, 62.627%; tC2Q: 0.333, 37.373%
Required Clock Path Delay	cell: 0.213, 71.550%; route: 0.085, 28.450%

Path3

Path Summary:

Slack	-0.608
Data Arrival Time	1.992
Data Required Time	2.600
From	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_0_s0
To	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[4].u_ides4
Launch Clk	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	620	BOTTOMSIDE[1]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513	0.183	tNET	RR	1	R11C14[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_0_s0/CLK
0.846	0.333	tC2Q	RR	11	R11C14[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_0_s0/Q
1.992	1.146	tNET	RR	1	IOB24[B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[4].u_ides4/CALIB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	1	PLL_L	GW_PLLVR_inst/pllvr_inst/CLKOUT
2.273	0.000	tNET	RR	3	R21C0	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKIN
2.486	0.213	tINS	RR	22	R21C0	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKOUT
2.570	0.085	tNET	RR	1	IOB24[B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[4].u_ides4/FCLK
2.600	0.030	tUnc				HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[4].u_ides4
2.600	0.000	tHld		1	IOB24[B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[4].u_ides4

Path Statistics:

Clock Skew	2.057
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.146, 77.466%; tC2Q: 0.333, 22.534%
Required Clock Path Delay	cell: 0.213, 71.550%; route: 0.085, 28.450%

Path4

Path Summary:

Slack	-0.568
Data Arrival Time	2.033
Data Required Time	2.600
From	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_0_s0
To	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[0].u_ides4
Launch Clk	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	620	BOTTOMSIDE[1]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513	0.183	tNET	RR	1	R11C14[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_0_s0/CLK
0.846	0.333	tC2Q	RR	11	R11C14[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_0_s0/Q
2.033	1.186	tNET	RR	1	IOB7[A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[0].u_ides4/CALIB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	1	PLL_L	GW_PLLVR_inst/pllvr_inst/CLKOUT
2.273	0.000	tNET	RR	3	R21C0	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKIN
2.486	0.213	tINS	RR	22	R21C0	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKOUT
2.570	0.085	tNET	RR	1	IOB7[A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[0].u_ides4/FCLK
2.600	0.030	tUnc				HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[0].u_ides4
2.600	0.000	tHld		1	IOB7[A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[0].u_ides4

Path Statistics:

Clock Skew	2.057
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.186, 78.065%; tC2Q: 0.333, 21.935%
Required Clock Path Delay	cell: 0.213, 71.550%; route: 0.085, 28.450%

Path5

Path Summary:

Slack	-0.568
Data Arrival Time	2.033
Data Required Time	2.600
From	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_0_s0
To	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[1].u_ides4
Launch Clk	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	620	BOTTOMSIDE[1]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513	0.183	tNET	RR	1	R11C14[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_0_s0/CLK
0.846	0.333	tC2Q	RR	11	R11C14[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_0_s0/Q
2.033	1.186	tNET	RR	1	IOB7[B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[1].u_ides4/CALIB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	1	PLL_L	GW_PLLVR_inst/pllvr_inst/CLKOUT
2.273	0.000	tNET	RR	3	R21C0	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKIN
2.486	0.213	tINS	RR	22	R21C0	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKOUT
2.570	0.085	tNET	RR	1	IOB7[B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[1].u_ides4/FCLK
2.600	0.030	tUnc				HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[1].u_ides4
2.600	0.000	tHld		1	IOB7[B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[1].u_ides4

Path Statistics:

Clock Skew	2.057
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.186, 78.065%; tC2Q: 0.333, 21.935%
Required Clock Path Delay	cell: 0.213, 71.550%; route: 0.085, 28.450%

Path6

Path Summary:

Slack	-0.304
Data Arrival Time	2.296
Data Required Time	2.600
From	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_0_s0
To	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[6].u_ides4
Launch Clk	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	620	BOTTOMSIDE[1]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513	0.183	tNET	RR	1	R11C14[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_0_s0/CLK
0.846	0.333	tC2Q	RR	11	R11C14[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_0_s0/Q
2.296	1.450	tNET	RR	1	IOB25[B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[6].u_ides4/CALIB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	1	PLL_L	GW_PLLVR_inst/pllvr_inst/CLKOUT
2.273	0.000	tNET	RR	3	R21C0	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKIN
2.486	0.213	tINS	RR	22	R21C0	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKOUT
2.570	0.085	tNET	RR	1	IOB25[B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[6].u_ides4/FCLK
2.600	0.030	tUnc				HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[6].u_ides4
2.600	0.000	tHld		1	IOB25[B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[6].u_ides4

Path Statistics:

Clock Skew	2.057
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.450, 81.309%; tC2Q: 0.333, 18.691%
Required Clock Path Delay	cell: 0.213, 71.550%; route: 0.085, 28.450%

Path7

Path Summary:

Slack	-0.304
Data Arrival Time	2.296
Data Required Time	2.600
From	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_0_s0
To	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[5].u_ides4
Launch Clk	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	620	BOTTOMSIDE[1]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513	0.183	tNET	RR	1	R11C14[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_0_s0/CLK
0.846	0.333	tC2Q	RR	11	R11C14[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_0_s0/Q
2.296	1.450	tNET	RR	1	IOB25[A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[5].u_ides4/CALIB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	1	PLL_L	GW_PLLVR_inst/pllvr_inst/CLKOUT
2.273	0.000	tNET	RR	3	R21C0	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKIN
2.486	0.213	tINS	RR	22	R21C0	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKOUT
2.570	0.085	tNET	RR	1	IOB25[A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[5].u_ides4/FCLK
2.600	0.030	tUnc				HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[5].u_ides4
2.600	0.000	tHld		1	IOB25[A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[5].u_ides4

Path Statistics:

Clock Skew	2.057
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.450, 81.309%; tC2Q: 0.333, 18.691%
Required Clock Path Delay	cell: 0.213, 71.550%; route: 0.085, 28.450%

Path8

Path Summary:

Slack	-0.284
Data Arrival Time	2.317
Data Required Time	2.600
From	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_0_s0
To	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[7].u_ides4
Launch Clk	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	620	BOTTOMSIDE[1]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513	0.183	tNET	RR	1	R11C14[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_0_s0/CLK
0.846	0.333	tC2Q	RR	11	R11C14[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_0_s0/Q
2.317	1.470	tNET	RR	1	IOB29[A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[7].u_ides4/CALIB

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk
2.273	2.273	tCL	RR	1	PLL_L	GW_PLLVR_inst/pllvr_inst/CLKOUT
2.273	0.000	tNET	RR	3	R21C0	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKIN
2.486	0.213	tINS	RR	22	R21C0	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_dqce_clk_x2p/CLKOUT
2.570	0.085	tNET	RR	1	IOB29[A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[7].u_ides4/FCLK
2.600	0.030	tUnc				HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[7].u_ides4
2.600	0.000	tHld		1	IOB29[A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/iserdes_gen[7].u_ides4

Path Statistics:

Clock Skew	2.057
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.470, 81.520%; tC2Q: 0.333, 18.480%
Required Clock Path Delay	cell: 0.213, 71.550%; route: 0.085, 28.450%

Path9

Path Summary:

Slack	0.408
Data Arrival Time	1.081
Data Required Time	0.673
From	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/rd_ptr_4_s1
To	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_0_0_s
Launch Clk	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	620	BOTTOMSIDE[1]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513	0.183	tNET	RR	1	R9C8[2][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/rd_ptr_4_s1/CLK
0.846	0.333	tC2Q	RF	2	R9C8[2][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/rd_ptr_4_s1/Q
1.081	0.234	tNET	FF	1	BSRAM_R10[2]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_0_0_s/ADB[9]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	620	BOTTOMSIDE[1]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513	0.183	tNET	RR	1	BSRAM_R10[2]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_0_0_s/CLKB
0.673	0.160	tHld		1	BSRAM_R10[2]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_wd/data_lane_gen[0].u_hpram_lane/mem_data_mem_data_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.234, 41.295%; tC2Q: 0.333, 58.705%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path10

Path Summary:

Slack	0.558
Data Arrival Time	1.084
Data Required Time	0.526
From	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/c_state.INIT_CALIB_DONE_s0
To	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/init_calib_s0
Launch Clk	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	620	BOTTOMSIDE[1]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513	0.183	tNET	RR	1	R9C14[1][B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/c_state.INIT_CALIB_DONE_s0/CLK
0.846	0.333	tC2Q	RR	2	R9C14[1][B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/c_state.INIT_CALIB_DONE_s0/Q
1.084	0.238	tNET	RR	1	R9C14[2][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/init_calib_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	620	BOTTOMSIDE[1]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513	0.183	tNET	RR	1	R9C14[2][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/init_calib_s0/CLK
0.526	0.012	tHld		1	R9C14[2][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/init_calib_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.238, 41.613%; tC2Q: 0.333, 58.387%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path11

Path Summary:

Slack	0.558
Data Arrival Time	1.084
Data Required Time	0.526
From	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vout_vs_n_sync2_s1
To	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vout_vs_n_falling_r_s0
Launch Clk	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	620	BOTTOMSIDE[1]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513	0.183	tNET	RR	1	R18C19[0][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vout_vs_n_sync2_s1/CLK
0.846	0.333	tC2Q	RR	2	R18C19[0][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vout_vs_n_sync2_s1/Q
1.084	0.238	tNET	RR	1	R18C19[2][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vout_vs_n_falling_r_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	620	BOTTOMSIDE[1]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513	0.183	tNET	RR	1	R18C19[2][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vout_vs_n_falling_r_s0/CLK
0.526	0.012	tHld		1	R18C19[2][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/vout_vs_n_falling_r_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.238, 41.613%; tC2Q: 0.333, 58.387%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path12

Path Summary:

Slack	0.576
Data Arrival Time	1.120
Data Required Time	0.543
From	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_0_s1
To	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_0_s1
Launch Clk	pix_clk:[R]
Latch Clk	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pix_clk
0.000	0.000	tCL	RR	176	RIGHTSIDE[1]	u_clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R4C18[1][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_0_s1/CLK
0.516	0.333	tC2Q	RF	1	R4C18[1][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_0_s1/Q
1.120	0.603	tNET	FF	1	R4C18[0][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	620	BOTTOMSIDE[1]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513	0.183	tNET	RR	1	R4C18[0][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_0_s1/CLK
0.543	0.030	tUnc				Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_0_s1
0.543	0.000	tHld		1	R4C18[0][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_0_s1

Path Statistics:

Clock Skew	0.330
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.603, 64.410%; tC2Q: 0.333, 35.590%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path13

Path Summary:

Slack	0.576
Data Arrival Time	1.120
Data Required Time	0.543
From	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_4_s1
To	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_4_s1
Launch Clk	pix_clk:[R]
Latch Clk	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pix_clk
0.000	0.000	tCL	RR	176	RIGHTSIDE[1]	u_clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R12C19[1][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_4_s1/CLK
0.516	0.333	tC2Q	RF	1	R12C19[1][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_4_s1/Q
1.120	0.603	tNET	FF	1	R12C19[2][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_4_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	620	BOTTOMSIDE[1]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513	0.183	tNET	RR	1	R12C19[2][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_4_s1/CLK
0.543	0.030	tUnc				Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_4_s1
0.543	0.000	tHld		1	R12C19[2][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_4_s1

Path Statistics:

Clock Skew	0.330
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.603, 64.410%; tC2Q: 0.333, 35.590%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path14

Path Summary:

Slack	0.576
Data Arrival Time	1.120
Data Required Time	0.543
From	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_5_s1
To	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_5_s1
Launch Clk	pix_clk:[R]
Latch Clk	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pix_clk
0.000	0.000	tCL	RR	176	RIGHTSIDE[1]	u_clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R5C18[1][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_5_s1/CLK
0.516	0.333	tC2Q	RF	1	R5C18[1][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_5_s1/Q
1.120	0.603	tNET	FF	1	R5C18[0][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	620	BOTTOMSIDE[1]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513	0.183	tNET	RR	1	R5C18[0][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_5_s1/CLK
0.543	0.030	tUnc				Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_5_s1
0.543	0.000	tHld		1	R5C18[0][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_5_s1

Path Statistics:

Clock Skew	0.330
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.603, 64.410%; tC2Q: 0.333, 35.590%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path15

Path Summary:

Slack	0.576
Data Arrival Time	1.120
Data Required Time	0.543
From	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_6_s1
To	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_6_s1
Launch Clk	pix_clk:[R]
Latch Clk	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pix_clk
0.000	0.000	tCL	RR	176	RIGHTSIDE[1]	u_clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R7C17[1][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_6_s1/CLK
0.516	0.333	tC2Q	RF	1	R7C17[1][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_6_s1/Q
1.120	0.603	tNET	FF	1	R7C17[0][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	620	BOTTOMSIDE[1]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513	0.183	tNET	RR	1	R7C17[0][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_6_s1/CLK
0.543	0.030	tUnc				Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_6_s1
0.543	0.000	tHld		1	R7C17[0][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_6_s1

Path Statistics:

Clock Skew	0.330
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.603, 64.410%; tC2Q: 0.333, 35.590%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path16

Path Summary:

Slack	0.576
Data Arrival Time	1.120
Data Required Time	0.543
From	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_7_s1
To	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_7_s1
Launch Clk	pix_clk:[R]
Latch Clk	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pix_clk
0.000	0.000	tCL	RR	176	RIGHTSIDE[1]	u_clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R7C19[1][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_7_s1/CLK
0.516	0.333	tC2Q	RF	1	R7C19[1][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_7_s1/Q
1.120	0.603	tNET	FF	1	R7C19[0][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	620	BOTTOMSIDE[1]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513	0.183	tNET	RR	1	R7C19[0][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_7_s1/CLK
0.543	0.030	tUnc				Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_7_s1
0.543	0.000	tHld		1	R7C19[0][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_7_s1

Path Statistics:

Clock Skew	0.330
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.603, 64.410%; tC2Q: 0.333, 35.590%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path17

Path Summary:

Slack	0.589
Data Arrival Time	1.115
Data Required Time	0.526
From	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_done_0_s0
To	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_0_s0
Launch Clk	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	620	BOTTOMSIDE[1]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513	0.183	tNET	RR	1	R13C14[0][B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_done_0_s0/CLK
0.846	0.333	tC2Q	RR	4	R13C14[0][B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_done_0_s0/Q
1.115	0.268	tNET	RR	1	R11C14[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_0_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	620	BOTTOMSIDE[1]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513	0.183	tNET	RR	1	R11C14[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_0_s0/CLK
0.526	0.012	tHld		1	R11C14[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_init/calib_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.268, 44.611%; tC2Q: 0.333, 55.389%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path18

Path Summary:

Slack	0.595
Data Arrival Time	1.138
Data Required Time	0.543
From	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_1_s1
To	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_1_s1
Launch Clk	pix_clk:[R]
Latch Clk	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pix_clk
0.000	0.000	tCL	RR	176	RIGHTSIDE[1]	u_clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R12C19[1][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_1_s1/CLK
0.516	0.333	tC2Q	RR	1	R12C19[1][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_1_s1/Q
1.138	0.621	tNET	RR	1	R12C19[2][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	620	BOTTOMSIDE[1]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513	0.183	tNET	RR	1	R12C19[2][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_1_s1/CLK
0.543	0.030	tUnc				Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_1_s1
0.543	0.000	tHld		1	R12C19[2][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_1_s1

Path Statistics:

Clock Skew	0.330
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.621, 65.086%; tC2Q: 0.333, 34.914%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path19

Path Summary:

Slack	0.595
Data Arrival Time	1.138
Data Required Time	0.543
From	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_2_s1
To	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_2_s1
Launch Clk	pix_clk:[R]
Latch Clk	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					pix_clk
0.000	0.000	tCL	RR	176	RIGHTSIDE[1]	u_clkdiv/CLKOUT
0.183	0.183	tNET	RR	1	R7C19[1][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_2_s1/CLK
0.516	0.333	tC2Q	RR	1	R7C19[1][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.rptr_2_s1/Q
1.138	0.621	tNET	RR	1	R7C19[2][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
0.330	0.330	tCL	RR	620	BOTTOMSIDE[1]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
0.513	0.183	tNET	RR	1	R7C19[2][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_2_s1/CLK
0.543	0.030	tUnc				Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_2_s1
0.543	0.000	tHld		1	R7C19[2][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.wq1_rptr_2_s1

Path Statistics:

Clock Skew	0.330
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.621, 65.086%; tC2Q: 0.333, 34.914%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%

Path20

Path Summary:

Slack	0.703
Data Arrival Time	2001.415
Data Required Time	2000.712
From	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_0_s1
To	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_0_s1
Launch Clk	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[R]
Latch Clk	ch0_vfb_clk_in:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1999.998	1999.998					active clock edge time
1999.998	0.000					HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
2000.328	0.330	tCL	RR	620	BOTTOMSIDE[1]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
2000.511	0.183	tNET	RR	1	R4C25[2][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_0_s1/CLK
2000.844	0.333	tC2Q	RR	1	R4C25[2][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rptr_0_s1/Q
2001.415	0.570	tNET	RR	1	R3C27[0][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
2000.000	2000.000					active clock edge time
2000.000	0.000					ch0_vfb_clk_in
2000.000	0.000	tCL	RR	63	R2C20[0][A]	ch0_vfb_clk_in_s0/F
2000.684	0.684	tNET	RR	1	R3C27[0][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_0_s1/CLK
2000.714	0.030	tUnc				Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_0_s1
2000.714	0.000	tHld		1	R3C27[0][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.wq1_rptr_0_s1

Path Statistics:

Clock Skew	0.170
Hold Relationship	0.002
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.570, 63.116%; tC2Q: 0.333, 36.884%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.684, 100.000%

Path21

Path Summary:

Slack	0.708
Data Arrival Time	3.066
Data Required Time	2.358
From	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_7_s1
To	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_7_s1
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R5C7[1][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_7_s1/CLK
2.692	0.333	tC2Q	RR	3	R5C7[1][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_7_s1/Q
2.694	0.002	tNET	RR	1	R5C7[1][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/n44_s1/I2
3.066	0.372	tINS	RF	1	R5C7[1][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/n44_s1/F
3.066	0.000	tNET	FF	1	R5C7[1][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R5C7[1][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_7_s1/CLK
2.358	0.000	tHld		1	R5C7[1][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_7_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%

Path22

Path Summary:

Slack	0.708
Data Arrival Time	3.066
Data Required Time	2.358
From	key_flag_inst/key_flag_s1
To	key_flag_inst/key_flag_s1
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R18C29[0][A]	key_flag_inst/key_flag_s1/CLK
2.692	0.333	tC2Q	RR	20	R18C29[0][A]	key_flag_inst/key_flag_s1/Q
2.694	0.002	tNET	RR	1	R18C29[0][A]	key_flag_inst/n106_s2/I0
3.066	0.372	tINS	RF	1	R18C29[0][A]	key_flag_inst/n106_s2/F
3.066	0.000	tNET	FF	1	R18C29[0][A]	key_flag_inst/key_flag_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R18C29[0][A]	key_flag_inst/key_flag_s1/CLK
2.358	0.000	tHld		1	R18C29[0][A]	key_flag_inst/key_flag_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%

Path23

Path Summary:

Slack	0.708
Data Arrival Time	3.066
Data Required Time	2.358
From	key_flag_inst/count_20ms_reg_3_s0
To	key_flag_inst/count_20ms_reg_3_s0
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R17C27[1][A]	key_flag_inst/count_20ms_reg_3_s0/CLK
2.692	0.333	tC2Q	RR	2	R17C27[1][A]	key_flag_inst/count_20ms_reg_3_s0/Q
2.694	0.002	tNET	RR	1	R17C27[1][A]	key_flag_inst/n70_s1/I2
3.066	0.372	tINS	RF	1	R17C27[1][A]	key_flag_inst/n70_s1/F
3.066	0.000	tNET	FF	1	R17C27[1][A]	key_flag_inst/count_20ms_reg_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R17C27[1][A]	key_flag_inst/count_20ms_reg_3_s0/CLK
2.358	0.000	tHld		1	R17C27[1][A]	key_flag_inst/count_20ms_reg_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%

Path24

Path Summary:

Slack	0.708
Data Arrival Time	3.066
Data Required Time	2.358
From	key_flag_inst/count_20ms_reg_20_s0
To	key_flag_inst/count_20ms_reg_20_s0
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R16C29[1][A]	key_flag_inst/count_20ms_reg_20_s0/CLK
2.692	0.333	tC2Q	RR	4	R16C29[1][A]	key_flag_inst/count_20ms_reg_20_s0/Q
2.694	0.002	tNET	RR	1	R16C29[1][A]	key_flag_inst/n53_s1/I0
3.066	0.372	tINS	RF	1	R16C29[1][A]	key_flag_inst/n53_s1/F
3.066	0.000	tNET	FF	1	R16C29[1][A]	key_flag_inst/count_20ms_reg_20_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R16C29[1][A]	key_flag_inst/count_20ms_reg_20_s0/CLK
2.358	0.000	tHld		1	R16C29[1][A]	key_flag_inst/count_20ms_reg_20_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%

Path25

Path Summary:

Slack	0.708
Data Arrival Time	3.066
Data Required Time	2.358
From	testpattern_inst/V_cnt_0_s3
To	testpattern_inst/V_cnt_0_s3
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R13C27[0][A]	testpattern_inst/V_cnt_0_s3/CLK
2.692	0.333	tC2Q	RR	6	R13C27[0][A]	testpattern_inst/V_cnt_0_s3/Q
2.694	0.002	tNET	RR	1	R13C27[0][A]	testpattern_inst/n74_s9/I2
3.066	0.372	tINS	RF	1	R13C27[0][A]	testpattern_inst/n74_s9/F
3.066	0.000	tNET	FF	1	R13C27[0][A]	testpattern_inst/V_cnt_0_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R13C27[0][A]	testpattern_inst/V_cnt_0_s3/CLK
2.358	0.000	tHld		1	R13C27[0][A]	testpattern_inst/V_cnt_0_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	-8.805
Data Arrival Time	49.376
Data Required Time	40.571
From	u_Reset_Sync/reset_cnt_0_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_clk
Launch Clk	I_clk:[R]
Latch Clk	pix_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.037	37.037					active clock edge time
37.037	0.000					I_clk
37.037	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
39.125	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
40.486	1.361	tNET	RR	1	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/CLK
40.945	0.458	tC2Q	RF	2	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/Q
41.752	0.807	tNET	FF	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I0
42.851	1.099	tINS	FF	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
45.798	2.947	tNET	FF	1	R3C31[0][A]	hdmi_rst_n_s0/I1
46.897	1.099	tINS	FF	119	R3C31[0][A]	hdmi_rst_n_s0/F
49.376	2.479	tNET	FF	1	IOR17[A]	DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_clk/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.404	40.404					active clock edge time
40.404	0.000					pix_clk
40.404	0.000	tCL	RR	176	RIGHTSIDE[1]	u_clkdiv/CLKOUT
40.646	0.242	tNET	RR	1	IOR17[A]	DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_clk/PCLK
40.616	-0.030	tUnc				DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_clk
40.571	-0.045	tSu		1	IOR17[A]	DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_clk

Path Statistics:

Clock Skew	-3.207
Setup Relationship	3.367
Logic Level	3
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 2.198, 24.726%; route: 6.233, 70.118%; tC2Q: 0.458, 5.156%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path2

Path Summary:

Slack	-8.805
Data Arrival Time	49.376
Data Required Time	40.571
From	u_Reset_Sync/reset_cnt_0_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_b
Launch Clk	I_clk:[R]
Latch Clk	pix_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.037	37.037					active clock edge time
37.037	0.000					I_clk
37.037	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
39.125	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
40.486	1.361	tNET	RR	1	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/CLK
40.945	0.458	tC2Q	RF	2	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/Q
41.752	0.807	tNET	FF	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I0
42.851	1.099	tINS	FF	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
45.798	2.947	tNET	FF	1	R3C31[0][A]	hdmi_rst_n_s0/I1
46.897	1.099	tINS	FF	119	R3C31[0][A]	hdmi_rst_n_s0/F
49.376	2.479	tNET	FF	1	IOR15[A]	DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_b/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.404	40.404					active clock edge time
40.404	0.000					pix_clk
40.404	0.000	tCL	RR	176	RIGHTSIDE[1]	u_clkdiv/CLKOUT
40.646	0.242	tNET	RR	1	IOR15[A]	DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_b/PCLK
40.616	-0.030	tUnc				DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_b
40.571	-0.045	tSu		1	IOR15[A]	DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_b

Path Statistics:

Clock Skew	-3.207
Setup Relationship	3.367
Logic Level	3
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 2.198, 24.726%; route: 6.233, 70.118%; tC2Q: 0.458, 5.156%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path3

Path Summary:

Slack	-8.805
Data Arrival Time	49.376
Data Required Time	40.571
From	u_Reset_Sync/reset_cnt_0_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_g
Launch Clk	I_clk:[R]
Latch Clk	pix_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.037	37.037					active clock edge time
37.037	0.000					I_clk
37.037	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
39.125	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
40.486	1.361	tNET	RR	1	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/CLK
40.945	0.458	tC2Q	RF	2	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/Q
41.752	0.807	tNET	FF	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I0
42.851	1.099	tINS	FF	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
45.798	2.947	tNET	FF	1	R3C31[0][A]	hdmi_rst_n_s0/I1
46.897	1.099	tINS	FF	119	R3C31[0][A]	hdmi_rst_n_s0/F
49.376	2.479	tNET	FF	1	IOR11[A]	DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_g/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.404	40.404					active clock edge time
40.404	0.000					pix_clk
40.404	0.000	tCL	RR	176	RIGHTSIDE[1]	u_clkdiv/CLKOUT
40.646	0.242	tNET	RR	1	IOR11[A]	DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_g/PCLK
40.616	-0.030	tUnc				DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_g
40.571	-0.045	tSu		1	IOR11[A]	DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_g

Path Statistics:

Clock Skew	-3.207
Setup Relationship	3.367
Logic Level	3
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 2.198, 24.726%; route: 6.233, 70.118%; tC2Q: 0.458, 5.156%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path4

Path Summary:

Slack	-8.805
Data Arrival Time	49.376
Data Required Time	40.571
From	u_Reset_Sync/reset_cnt_0_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_r
Launch Clk	I_clk:[R]
Latch Clk	pix_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.037	37.037					active clock edge time
37.037	0.000					I_clk
37.037	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
39.125	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
40.486	1.361	tNET	RR	1	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/CLK
40.945	0.458	tC2Q	RF	2	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/Q
41.752	0.807	tNET	FF	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I0
42.851	1.099	tINS	FF	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
45.798	2.947	tNET	FF	1	R3C31[0][A]	hdmi_rst_n_s0/I1
46.897	1.099	tINS	FF	119	R3C31[0][A]	hdmi_rst_n_s0/F
49.376	2.479	tNET	FF	1	IOR2[A]	DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_r/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.404	40.404					active clock edge time
40.404	0.000					pix_clk
40.404	0.000	tCL	RR	176	RIGHTSIDE[1]	u_clkdiv/CLKOUT
40.646	0.242	tNET	RR	1	IOR2[A]	DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_r/PCLK
40.616	-0.030	tUnc				DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_r
40.571	-0.045	tSu		1	IOR2[A]	DVI_TX_Top_inst/rgb2dvi_inst/u_OSER10_r

Path Statistics:

Clock Skew	-3.207
Setup Relationship	3.367
Logic Level	3
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 2.198, 24.726%; route: 6.233, 70.118%; tC2Q: 0.458, 5.156%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path5

Path Summary:

Slack	-8.803
Data Arrival Time	49.376
Data Required Time	40.573
From	u_Reset_Sync/reset_cnt_0_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/c0_d_s0
Launch Clk	I_clk:[R]
Latch Clk	pix_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.037	37.037					active clock edge time
37.037	0.000					I_clk
37.037	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
39.125	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
40.486	1.361	tNET	RR	1	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/CLK
40.945	0.458	tC2Q	RF	2	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/Q
41.752	0.807	tNET	FF	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I0
42.851	1.099	tINS	FF	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
45.798	2.947	tNET	FF	1	R3C31[0][A]	hdmi_rst_n_s0/I1
46.897	1.099	tINS	FF	119	R3C31[0][A]	hdmi_rst_n_s0/F
49.376	2.479	tNET	FF	1	R16C32[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/c0_d_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.404	40.404					active clock edge time
40.404	0.000					pix_clk
40.404	0.000	tCL	RR	176	RIGHTSIDE[1]	u_clkdiv/CLKOUT
40.646	0.242	tNET	RR	1	R16C32[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/c0_d_s0/CLK
40.616	-0.030	tUnc				DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/c0_d_s0
40.573	-0.043	tSu		1	R16C32[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/c0_d_s0

Path Statistics:

Clock Skew	-3.207
Setup Relationship	3.367
Logic Level	3
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 2.198, 24.726%; route: 6.233, 70.118%; tC2Q: 0.458, 5.156%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path6

Path Summary:

Slack	-8.803
Data Arrival Time	49.376
Data Required Time	40.573
From	u_Reset_Sync/reset_cnt_0_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_7_s0
Launch Clk	I_clk:[R]
Latch Clk	pix_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.037	37.037					active clock edge time
37.037	0.000					I_clk
37.037	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
39.125	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
40.486	1.361	tNET	RR	1	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/CLK
40.945	0.458	tC2Q	RF	2	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/Q
41.752	0.807	tNET	FF	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I0
42.851	1.099	tINS	FF	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
45.798	2.947	tNET	FF	1	R3C31[0][A]	hdmi_rst_n_s0/I1
46.897	1.099	tINS	FF	119	R3C31[0][A]	hdmi_rst_n_s0/F
49.376	2.479	tNET	FF	1	R14C32[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_7_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.404	40.404					active clock edge time
40.404	0.000					pix_clk
40.404	0.000	tCL	RR	176	RIGHTSIDE[1]	u_clkdiv/CLKOUT
40.646	0.242	tNET	RR	1	R14C32[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_7_s0/CLK
40.616	-0.030	tUnc				DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_7_s0
40.573	-0.043	tSu		1	R14C32[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_7_s0

Path Statistics:

Clock Skew	-3.207
Setup Relationship	3.367
Logic Level	3
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 2.198, 24.726%; route: 6.233, 70.118%; tC2Q: 0.458, 5.156%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path7

Path Summary:

Slack	-8.803
Data Arrival Time	49.376
Data Required Time	40.573
From	u_Reset_Sync/reset_cnt_0_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_0_s0
Launch Clk	I_clk:[R]
Latch Clk	pix_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.037	37.037					active clock edge time
37.037	0.000					I_clk
37.037	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
39.125	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
40.486	1.361	tNET	RR	1	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/CLK
40.945	0.458	tC2Q	RF	2	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/Q
41.752	0.807	tNET	FF	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I0
42.851	1.099	tINS	FF	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
45.798	2.947	tNET	FF	1	R3C31[0][A]	hdmi_rst_n_s0/I1
46.897	1.099	tINS	FF	119	R3C31[0][A]	hdmi_rst_n_s0/F
49.376	2.479	tNET	FF	1	R15C32[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.404	40.404					active clock edge time
40.404	0.000					pix_clk
40.404	0.000	tCL	RR	176	RIGHTSIDE[1]	u_clkdiv/CLKOUT
40.646	0.242	tNET	RR	1	R15C32[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_0_s0/CLK
40.616	-0.030	tUnc				DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_0_s0
40.573	-0.043	tSu		1	R15C32[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_0_s0

Path Statistics:

Clock Skew	-3.207
Setup Relationship	3.367
Logic Level	3
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 2.198, 24.726%; route: 6.233, 70.118%; tC2Q: 0.458, 5.156%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path8

Path Summary:

Slack	-8.803
Data Arrival Time	49.376
Data Required Time	40.573
From	u_Reset_Sync/reset_cnt_0_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_1_s0
Launch Clk	I_clk:[R]
Latch Clk	pix_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.037	37.037					active clock edge time
37.037	0.000					I_clk
37.037	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
39.125	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
40.486	1.361	tNET	RR	1	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/CLK
40.945	0.458	tC2Q	RF	2	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/Q
41.752	0.807	tNET	FF	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I0
42.851	1.099	tINS	FF	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
45.798	2.947	tNET	FF	1	R3C31[0][A]	hdmi_rst_n_s0/I1
46.897	1.099	tINS	FF	119	R3C31[0][A]	hdmi_rst_n_s0/F
49.376	2.479	tNET	FF	1	R15C35[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.404	40.404					active clock edge time
40.404	0.000					pix_clk
40.404	0.000	tCL	RR	176	RIGHTSIDE[1]	u_clkdiv/CLKOUT
40.646	0.242	tNET	RR	1	R15C35[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_1_s0/CLK
40.616	-0.030	tUnc				DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_1_s0
40.573	-0.043	tSu		1	R15C35[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_1_s0

Path Statistics:

Clock Skew	-3.207
Setup Relationship	3.367
Logic Level	3
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 2.198, 24.726%; route: 6.233, 70.118%; tC2Q: 0.458, 5.156%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path9

Path Summary:

Slack	-8.803
Data Arrival Time	49.376
Data Required Time	40.573
From	u_Reset_Sync/reset_cnt_0_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_2_s0
Launch Clk	I_clk:[R]
Latch Clk	pix_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.037	37.037					active clock edge time
37.037	0.000					I_clk
37.037	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
39.125	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
40.486	1.361	tNET	RR	1	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/CLK
40.945	0.458	tC2Q	RF	2	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/Q
41.752	0.807	tNET	FF	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I0
42.851	1.099	tINS	FF	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
45.798	2.947	tNET	FF	1	R3C31[0][A]	hdmi_rst_n_s0/I1
46.897	1.099	tINS	FF	119	R3C31[0][A]	hdmi_rst_n_s0/F
49.376	2.479	tNET	FF	1	R14C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.404	40.404					active clock edge time
40.404	0.000					pix_clk
40.404	0.000	tCL	RR	176	RIGHTSIDE[1]	u_clkdiv/CLKOUT
40.646	0.242	tNET	RR	1	R14C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_2_s0/CLK
40.616	-0.030	tUnc				DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_2_s0
40.573	-0.043	tSu		1	R14C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_2_s0

Path Statistics:

Clock Skew	-3.207
Setup Relationship	3.367
Logic Level	3
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 2.198, 24.726%; route: 6.233, 70.118%; tC2Q: 0.458, 5.156%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path10

Path Summary:

Slack	-8.803
Data Arrival Time	49.376
Data Required Time	40.573
From	u_Reset_Sync/reset_cnt_0_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_3_s0
Launch Clk	I_clk:[R]
Latch Clk	pix_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.037	37.037					active clock edge time
37.037	0.000					I_clk
37.037	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
39.125	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
40.486	1.361	tNET	RR	1	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/CLK
40.945	0.458	tC2Q	RF	2	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/Q
41.752	0.807	tNET	FF	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I0
42.851	1.099	tINS	FF	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
45.798	2.947	tNET	FF	1	R3C31[0][A]	hdmi_rst_n_s0/I1
46.897	1.099	tINS	FF	119	R3C31[0][A]	hdmi_rst_n_s0/F
49.376	2.479	tNET	FF	1	R15C35[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.404	40.404					active clock edge time
40.404	0.000					pix_clk
40.404	0.000	tCL	RR	176	RIGHTSIDE[1]	u_clkdiv/CLKOUT
40.646	0.242	tNET	RR	1	R15C35[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_3_s0/CLK
40.616	-0.030	tUnc				DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_3_s0
40.573	-0.043	tSu		1	R15C35[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_3_s0

Path Statistics:

Clock Skew	-3.207
Setup Relationship	3.367
Logic Level	3
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 2.198, 24.726%; route: 6.233, 70.118%; tC2Q: 0.458, 5.156%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path11

Path Summary:

Slack	-8.803
Data Arrival Time	49.376
Data Required Time	40.573
From	u_Reset_Sync/reset_cnt_0_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_4_s0
Launch Clk	I_clk:[R]
Latch Clk	pix_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.037	37.037					active clock edge time
37.037	0.000					I_clk
37.037	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
39.125	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
40.486	1.361	tNET	RR	1	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/CLK
40.945	0.458	tC2Q	RF	2	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/Q
41.752	0.807	tNET	FF	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I0
42.851	1.099	tINS	FF	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
45.798	2.947	tNET	FF	1	R3C31[0][A]	hdmi_rst_n_s0/I1
46.897	1.099	tINS	FF	119	R3C31[0][A]	hdmi_rst_n_s0/F
49.376	2.479	tNET	FF	1	R15C32[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.404	40.404					active clock edge time
40.404	0.000					pix_clk
40.404	0.000	tCL	RR	176	RIGHTSIDE[1]	u_clkdiv/CLKOUT
40.646	0.242	tNET	RR	1	R15C32[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_4_s0/CLK
40.616	-0.030	tUnc				DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_4_s0
40.573	-0.043	tSu		1	R15C32[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_4_s0

Path Statistics:

Clock Skew	-3.207
Setup Relationship	3.367
Logic Level	3
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 2.198, 24.726%; route: 6.233, 70.118%; tC2Q: 0.458, 5.156%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path12

Path Summary:

Slack	-8.803
Data Arrival Time	49.376
Data Required Time	40.573
From	u_Reset_Sync/reset_cnt_0_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_5_s0
Launch Clk	I_clk:[R]
Latch Clk	pix_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.037	37.037					active clock edge time
37.037	0.000					I_clk
37.037	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
39.125	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
40.486	1.361	tNET	RR	1	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/CLK
40.945	0.458	tC2Q	RF	2	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/Q
41.752	0.807	tNET	FF	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I0
42.851	1.099	tINS	FF	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
45.798	2.947	tNET	FF	1	R3C31[0][A]	hdmi_rst_n_s0/I1
46.897	1.099	tINS	FF	119	R3C31[0][A]	hdmi_rst_n_s0/F
49.376	2.479	tNET	FF	1	R14C35[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.404	40.404					active clock edge time
40.404	0.000					pix_clk
40.404	0.000	tCL	RR	176	RIGHTSIDE[1]	u_clkdiv/CLKOUT
40.646	0.242	tNET	RR	1	R14C35[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_5_s0/CLK
40.616	-0.030	tUnc				DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_5_s0
40.573	-0.043	tSu		1	R14C35[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_5_s0

Path Statistics:

Clock Skew	-3.207
Setup Relationship	3.367
Logic Level	3
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 2.198, 24.726%; route: 6.233, 70.118%; tC2Q: 0.458, 5.156%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path13

Path Summary:

Slack	-8.803
Data Arrival Time	49.376
Data Required Time	40.573
From	u_Reset_Sync/reset_cnt_0_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_6_s0
Launch Clk	I_clk:[R]
Latch Clk	pix_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.037	37.037					active clock edge time
37.037	0.000					I_clk
37.037	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
39.125	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
40.486	1.361	tNET	RR	1	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/CLK
40.945	0.458	tC2Q	RF	2	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/Q
41.752	0.807	tNET	FF	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I0
42.851	1.099	tINS	FF	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
45.798	2.947	tNET	FF	1	R3C31[0][A]	hdmi_rst_n_s0/I1
46.897	1.099	tINS	FF	119	R3C31[0][A]	hdmi_rst_n_s0/F
49.376	2.479	tNET	FF	1	R14C33[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_6_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.404	40.404					active clock edge time
40.404	0.000					pix_clk
40.404	0.000	tCL	RR	176	RIGHTSIDE[1]	u_clkdiv/CLKOUT
40.646	0.242	tNET	RR	1	R14C33[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_6_s0/CLK
40.616	-0.030	tUnc				DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_6_s0
40.573	-0.043	tSu		1	R14C33[1][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_6_s0

Path Statistics:

Clock Skew	-3.207
Setup Relationship	3.367
Logic Level	3
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 2.198, 24.726%; route: 6.233, 70.118%; tC2Q: 0.458, 5.156%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path14

Path Summary:

Slack	-8.803
Data Arrival Time	49.376
Data Required Time	40.573
From	u_Reset_Sync/reset_cnt_0_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_7_s0
Launch Clk	I_clk:[R]
Latch Clk	pix_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.037	37.037					active clock edge time
37.037	0.000					I_clk
37.037	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
39.125	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
40.486	1.361	tNET	RR	1	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/CLK
40.945	0.458	tC2Q	RF	2	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/Q
41.752	0.807	tNET	FF	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I0
42.851	1.099	tINS	FF	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
45.798	2.947	tNET	FF	1	R3C31[0][A]	hdmi_rst_n_s0/I1
46.897	1.099	tINS	FF	119	R3C31[0][A]	hdmi_rst_n_s0/F
49.376	2.479	tNET	FF	1	R15C32[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_7_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.404	40.404					active clock edge time
40.404	0.000					pix_clk
40.404	0.000	tCL	RR	176	RIGHTSIDE[1]	u_clkdiv/CLKOUT
40.646	0.242	tNET	RR	1	R15C32[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_7_s0/CLK
40.616	-0.030	tUnc				DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_7_s0
40.573	-0.043	tSu		1	R15C32[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_7_s0

Path Statistics:

Clock Skew	-3.207
Setup Relationship	3.367
Logic Level	3
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 2.198, 24.726%; route: 6.233, 70.118%; tC2Q: 0.458, 5.156%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path15

Path Summary:

Slack	-8.803
Data Arrival Time	49.376
Data Required Time	40.573
From	u_Reset_Sync/reset_cnt_0_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_8_s0
Launch Clk	I_clk:[R]
Latch Clk	pix_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.037	37.037					active clock edge time
37.037	0.000					I_clk
37.037	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
39.125	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
40.486	1.361	tNET	RR	1	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/CLK
40.945	0.458	tC2Q	RF	2	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/Q
41.752	0.807	tNET	FF	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I0
42.851	1.099	tINS	FF	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
45.798	2.947	tNET	FF	1	R3C31[0][A]	hdmi_rst_n_s0/I1
46.897	1.099	tINS	FF	119	R3C31[0][A]	hdmi_rst_n_s0/F
49.376	2.479	tNET	FF	1	R14C36[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_8_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.404	40.404					active clock edge time
40.404	0.000					pix_clk
40.404	0.000	tCL	RR	176	RIGHTSIDE[1]	u_clkdiv/CLKOUT
40.646	0.242	tNET	RR	1	R14C36[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_8_s0/CLK
40.616	-0.030	tUnc				DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_8_s0
40.573	-0.043	tSu		1	R14C36[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_8_s0

Path Statistics:

Clock Skew	-3.207
Setup Relationship	3.367
Logic Level	3
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 2.198, 24.726%; route: 6.233, 70.118%; tC2Q: 0.458, 5.156%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path16

Path Summary:

Slack	-8.803
Data Arrival Time	49.376
Data Required Time	40.573
From	u_Reset_Sync/reset_cnt_0_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_9_s0
Launch Clk	I_clk:[R]
Latch Clk	pix_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.037	37.037					active clock edge time
37.037	0.000					I_clk
37.037	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
39.125	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
40.486	1.361	tNET	RR	1	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/CLK
40.945	0.458	tC2Q	RF	2	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/Q
41.752	0.807	tNET	FF	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I0
42.851	1.099	tINS	FF	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
45.798	2.947	tNET	FF	1	R3C31[0][A]	hdmi_rst_n_s0/I1
46.897	1.099	tINS	FF	119	R3C31[0][A]	hdmi_rst_n_s0/F
49.376	2.479	tNET	FF	1	R15C35[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_9_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.404	40.404					active clock edge time
40.404	0.000					pix_clk
40.404	0.000	tCL	RR	176	RIGHTSIDE[1]	u_clkdiv/CLKOUT
40.646	0.242	tNET	RR	1	R15C35[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_9_s0/CLK
40.616	-0.030	tUnc				DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_9_s0
40.573	-0.043	tSu		1	R15C35[2][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/dout_9_s0

Path Statistics:

Clock Skew	-3.207
Setup Relationship	3.367
Logic Level	3
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 2.198, 24.726%; route: 6.233, 70.118%; tC2Q: 0.458, 5.156%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path17

Path Summary:

Slack	-8.803
Data Arrival Time	49.376
Data Required Time	40.573
From	u_Reset_Sync/reset_cnt_0_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_1_s0
Launch Clk	I_clk:[R]
Latch Clk	pix_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.037	37.037					active clock edge time
37.037	0.000					I_clk
37.037	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
39.125	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
40.486	1.361	tNET	RR	1	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/CLK
40.945	0.458	tC2Q	RF	2	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/Q
41.752	0.807	tNET	FF	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I0
42.851	1.099	tINS	FF	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
45.798	2.947	tNET	FF	1	R3C31[0][A]	hdmi_rst_n_s0/I1
46.897	1.099	tINS	FF	119	R3C31[0][A]	hdmi_rst_n_s0/F
49.376	2.479	tNET	FF	1	R12C33[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.404	40.404					active clock edge time
40.404	0.000					pix_clk
40.404	0.000	tCL	RR	176	RIGHTSIDE[1]	u_clkdiv/CLKOUT
40.646	0.242	tNET	RR	1	R12C33[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_1_s0/CLK
40.616	-0.030	tUnc				DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_1_s0
40.573	-0.043	tSu		1	R12C33[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_1_s0

Path Statistics:

Clock Skew	-3.207
Setup Relationship	3.367
Logic Level	3
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 2.198, 24.726%; route: 6.233, 70.118%; tC2Q: 0.458, 5.156%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path18

Path Summary:

Slack	-8.803
Data Arrival Time	49.376
Data Required Time	40.573
From	u_Reset_Sync/reset_cnt_0_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_2_s0
Launch Clk	I_clk:[R]
Latch Clk	pix_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.037	37.037					active clock edge time
37.037	0.000					I_clk
37.037	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
39.125	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
40.486	1.361	tNET	RR	1	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/CLK
40.945	0.458	tC2Q	RF	2	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/Q
41.752	0.807	tNET	FF	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I0
42.851	1.099	tINS	FF	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
45.798	2.947	tNET	FF	1	R3C31[0][A]	hdmi_rst_n_s0/I1
46.897	1.099	tINS	FF	119	R3C31[0][A]	hdmi_rst_n_s0/F
49.376	2.479	tNET	FF	1	R12C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.404	40.404					active clock edge time
40.404	0.000					pix_clk
40.404	0.000	tCL	RR	176	RIGHTSIDE[1]	u_clkdiv/CLKOUT
40.646	0.242	tNET	RR	1	R12C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_2_s0/CLK
40.616	-0.030	tUnc				DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_2_s0
40.573	-0.043	tSu		1	R12C33[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_2_s0

Path Statistics:

Clock Skew	-3.207
Setup Relationship	3.367
Logic Level	3
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 2.198, 24.726%; route: 6.233, 70.118%; tC2Q: 0.458, 5.156%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path19

Path Summary:

Slack	-8.803
Data Arrival Time	49.376
Data Required Time	40.573
From	u_Reset_Sync/reset_cnt_0_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_3_s0
Launch Clk	I_clk:[R]
Latch Clk	pix_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.037	37.037					active clock edge time
37.037	0.000					I_clk
37.037	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
39.125	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
40.486	1.361	tNET	RR	1	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/CLK
40.945	0.458	tC2Q	RF	2	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/Q
41.752	0.807	tNET	FF	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I0
42.851	1.099	tINS	FF	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
45.798	2.947	tNET	FF	1	R3C31[0][A]	hdmi_rst_n_s0/I1
46.897	1.099	tINS	FF	119	R3C31[0][A]	hdmi_rst_n_s0/F
49.376	2.479	tNET	FF	1	R14C34[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.404	40.404					active clock edge time
40.404	0.000					pix_clk
40.404	0.000	tCL	RR	176	RIGHTSIDE[1]	u_clkdiv/CLKOUT
40.646	0.242	tNET	RR	1	R14C34[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_3_s0/CLK
40.616	-0.030	tUnc				DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_3_s0
40.573	-0.043	tSu		1	R14C34[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_3_s0

Path Statistics:

Clock Skew	-3.207
Setup Relationship	3.367
Logic Level	3
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 2.198, 24.726%; route: 6.233, 70.118%; tC2Q: 0.458, 5.156%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path20

Path Summary:

Slack	-8.803
Data Arrival Time	49.376
Data Required Time	40.573
From	u_Reset_Sync/reset_cnt_0_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0
Launch Clk	I_clk:[R]
Latch Clk	pix_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.037	37.037					active clock edge time
37.037	0.000					I_clk
37.037	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
39.125	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
40.486	1.361	tNET	RR	1	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/CLK
40.945	0.458	tC2Q	RF	2	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/Q
41.752	0.807	tNET	FF	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I0
42.851	1.099	tINS	FF	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
45.798	2.947	tNET	FF	1	R3C31[0][A]	hdmi_rst_n_s0/I1
46.897	1.099	tINS	FF	119	R3C31[0][A]	hdmi_rst_n_s0/F
49.376	2.479	tNET	FF	1	R12C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.404	40.404					active clock edge time
40.404	0.000					pix_clk
40.404	0.000	tCL	RR	176	RIGHTSIDE[1]	u_clkdiv/CLKOUT
40.646	0.242	tNET	RR	1	R12C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0/CLK
40.616	-0.030	tUnc				DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0
40.573	-0.043	tSu		1	R12C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/cnt_4_s0

Path Statistics:

Clock Skew	-3.207
Setup Relationship	3.367
Logic Level	3
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 2.198, 24.726%; route: 6.233, 70.118%; tC2Q: 0.458, 5.156%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path21

Path Summary:

Slack	-8.803
Data Arrival Time	49.376
Data Required Time	40.573
From	u_Reset_Sync/reset_cnt_0_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0
Launch Clk	I_clk:[R]
Latch Clk	pix_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.037	37.037					active clock edge time
37.037	0.000					I_clk
37.037	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
39.125	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
40.486	1.361	tNET	RR	1	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/CLK
40.945	0.458	tC2Q	RF	2	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/Q
41.752	0.807	tNET	FF	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I0
42.851	1.099	tINS	FF	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
45.798	2.947	tNET	FF	1	R3C31[0][A]	hdmi_rst_n_s0/I1
46.897	1.099	tINS	FF	119	R3C31[0][A]	hdmi_rst_n_s0/F
49.376	2.479	tNET	FF	1	R14C32[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.404	40.404					active clock edge time
40.404	0.000					pix_clk
40.404	0.000	tCL	RR	176	RIGHTSIDE[1]	u_clkdiv/CLKOUT
40.646	0.242	tNET	RR	1	R14C32[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0/CLK
40.616	-0.030	tUnc				DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0
40.573	-0.043	tSu		1	R14C32[1][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0

Path Statistics:

Clock Skew	-3.207
Setup Relationship	3.367
Logic Level	3
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 2.198, 24.726%; route: 6.233, 70.118%; tC2Q: 0.458, 5.156%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path22

Path Summary:

Slack	-8.803
Data Arrival Time	49.376
Data Required Time	40.573
From	u_Reset_Sync/reset_cnt_0_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/c1_d_s0
Launch Clk	I_clk:[R]
Latch Clk	pix_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.037	37.037					active clock edge time
37.037	0.000					I_clk
37.037	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
39.125	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
40.486	1.361	tNET	RR	1	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/CLK
40.945	0.458	tC2Q	RF	2	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/Q
41.752	0.807	tNET	FF	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I0
42.851	1.099	tINS	FF	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
45.798	2.947	tNET	FF	1	R3C31[0][A]	hdmi_rst_n_s0/I1
46.897	1.099	tINS	FF	119	R3C31[0][A]	hdmi_rst_n_s0/F
49.376	2.479	tNET	FF	1	R15C35[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/c1_d_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.404	40.404					active clock edge time
40.404	0.000					pix_clk
40.404	0.000	tCL	RR	176	RIGHTSIDE[1]	u_clkdiv/CLKOUT
40.646	0.242	tNET	RR	1	R15C35[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/c1_d_s0/CLK
40.616	-0.030	tUnc				DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/c1_d_s0
40.573	-0.043	tSu		1	R15C35[2][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/c1_d_s0

Path Statistics:

Clock Skew	-3.207
Setup Relationship	3.367
Logic Level	3
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 2.198, 24.726%; route: 6.233, 70.118%; tC2Q: 0.458, 5.156%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path23

Path Summary:

Slack	-8.803
Data Arrival Time	49.376
Data Required Time	40.573
From	u_Reset_Sync/reset_cnt_0_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_0_s0
Launch Clk	I_clk:[R]
Latch Clk	pix_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.037	37.037					active clock edge time
37.037	0.000					I_clk
37.037	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
39.125	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
40.486	1.361	tNET	RR	1	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/CLK
40.945	0.458	tC2Q	RF	2	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/Q
41.752	0.807	tNET	FF	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I0
42.851	1.099	tINS	FF	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
45.798	2.947	tNET	FF	1	R3C31[0][A]	hdmi_rst_n_s0/I1
46.897	1.099	tINS	FF	119	R3C31[0][A]	hdmi_rst_n_s0/F
49.376	2.479	tNET	FF	1	R15C33[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.404	40.404					active clock edge time
40.404	0.000					pix_clk
40.404	0.000	tCL	RR	176	RIGHTSIDE[1]	u_clkdiv/CLKOUT
40.646	0.242	tNET	RR	1	R15C33[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_0_s0/CLK
40.616	-0.030	tUnc				DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_0_s0
40.573	-0.043	tSu		1	R15C33[0][B]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_0_s0

Path Statistics:

Clock Skew	-3.207
Setup Relationship	3.367
Logic Level	3
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 2.198, 24.726%; route: 6.233, 70.118%; tC2Q: 0.458, 5.156%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path24

Path Summary:

Slack	-8.803
Data Arrival Time	49.376
Data Required Time	40.573
From	u_Reset_Sync/reset_cnt_0_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_1_s0
Launch Clk	I_clk:[R]
Latch Clk	pix_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.037	37.037					active clock edge time
37.037	0.000					I_clk
37.037	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
39.125	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
40.486	1.361	tNET	RR	1	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/CLK
40.945	0.458	tC2Q	RF	2	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/Q
41.752	0.807	tNET	FF	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I0
42.851	1.099	tINS	FF	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
45.798	2.947	tNET	FF	1	R3C31[0][A]	hdmi_rst_n_s0/I1
46.897	1.099	tINS	FF	119	R3C31[0][A]	hdmi_rst_n_s0/F
49.376	2.479	tNET	FF	1	R14C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.404	40.404					active clock edge time
40.404	0.000					pix_clk
40.404	0.000	tCL	RR	176	RIGHTSIDE[1]	u_clkdiv/CLKOUT
40.646	0.242	tNET	RR	1	R14C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_1_s0/CLK
40.616	-0.030	tUnc				DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_1_s0
40.573	-0.043	tSu		1	R14C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_1_s0

Path Statistics:

Clock Skew	-3.207
Setup Relationship	3.367
Logic Level	3
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 2.198, 24.726%; route: 6.233, 70.118%; tC2Q: 0.458, 5.156%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Path25

Path Summary:

Slack	-8.803
Data Arrival Time	49.376
Data Required Time	40.573
From	u_Reset_Sync/reset_cnt_0_s0
To	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_2_s0
Launch Clk	I_clk:[R]
Latch Clk	pix_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
37.037	37.037					active clock edge time
37.037	0.000					I_clk
37.037	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
39.125	2.088	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
40.486	1.361	tNET	RR	1	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/CLK
40.945	0.458	tC2Q	RF	2	R11C28[0][A]	u_Reset_Sync/reset_cnt_0_s0/Q
41.752	0.807	tNET	FF	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I0
42.851	1.099	tINS	FF	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
45.798	2.947	tNET	FF	1	R3C31[0][A]	hdmi_rst_n_s0/I1
46.897	1.099	tINS	FF	119	R3C31[0][A]	hdmi_rst_n_s0/F
49.376	2.479	tNET	FF	1	R15C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.404	40.404					active clock edge time
40.404	0.000					pix_clk
40.404	0.000	tCL	RR	176	RIGHTSIDE[1]	u_clkdiv/CLKOUT
40.646	0.242	tNET	RR	1	R15C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_2_s0/CLK
40.616	-0.030	tUnc				DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_2_s0
40.573	-0.043	tSu		1	R15C33[0][A]	DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/din_d_2_s0

Path Statistics:

Clock Skew	-3.207
Setup Relationship	3.367
Logic Level	3
Arrival Clock Path Delay	cell: 2.088, 60.534%; route: 1.361, 39.466%
Arrival Data Path Delay	cell: 2.198, 24.726%; route: 6.233, 70.118%; tC2Q: 0.458, 5.156%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.242, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.781
Data Arrival Time	1240.337
Data Required Time	1239.556
From	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_rd_rst_s0
To	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_w_0_s0
Launch Clk	pix_clk:[R]
Latch Clk	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1239.056	1239.056					active clock edge time
1239.056	0.000					pix_clk
1239.056	0.000	tCL	RR	176	RIGHTSIDE[1]	u_clkdiv/CLKOUT
1239.239	0.183	tNET	RR	1	R8C18[0][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_rd_rst_s0/CLK
1239.572	0.333	tC2Q	RR	4	R8C18[0][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_rd_rst_s0/Q
1240.337	0.765	tNET	RR	1	R4C18[2][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_w_0_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1238.992	1238.992					active clock edge time
1238.992	0.000					HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
1239.323	0.330	tCL	FF	620	BOTTOMSIDE[1]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
1239.514	0.191	tNET	FF	1	R4C18[2][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_w_0_s0/CLK
1239.544	0.030	tUnc				Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_w_0_s0
1239.556	0.012	tHld		1	R4C18[2][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_w_0_s0

Path Statistics:

Clock Skew	0.338
Hold Relationship	-0.064
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.765, 69.653%; tC2Q: 0.333, 30.347%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.191, 100.000%

Path2

Path Summary:

Slack	0.781
Data Arrival Time	1240.337
Data Required Time	1239.556
From	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_rd_rst_s0
To	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_w_1_s0
Launch Clk	pix_clk:[R]
Latch Clk	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1239.056	1239.056					active clock edge time
1239.056	0.000					pix_clk
1239.056	0.000	tCL	RR	176	RIGHTSIDE[1]	u_clkdiv/CLKOUT
1239.239	0.183	tNET	RR	1	R8C18[0][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_rd_rst_s0/CLK
1239.572	0.333	tC2Q	RR	4	R8C18[0][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_rd_rst_s0/Q
1240.337	0.765	tNET	RR	1	R4C18[2][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_w_1_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1238.992	1238.992					active clock edge time
1238.992	0.000					HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
1239.323	0.330	tCL	FF	620	BOTTOMSIDE[1]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
1239.514	0.191	tNET	FF	1	R4C18[2][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_w_1_s0/CLK
1239.544	0.030	tUnc				Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_w_1_s0
1239.556	0.012	tHld		1	R4C18[2][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_w_1_s0

Path Statistics:

Clock Skew	0.338
Hold Relationship	-0.064
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.183, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.765, 69.653%; tC2Q: 0.333, 30.347%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.191, 100.000%

Path3

Path Summary:

Slack	1.293
Data Arrival Time	1001.856
Data Required Time	1000.563
From	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_s0
To	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0
Launch Clk	ch0_vfb_clk_in:[R]
Latch Clk	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1000.000	1000.000					active clock edge time
1000.000	0.000					ch0_vfb_clk_in
1000.000	0.000	tCL	RR	63	R2C20[0][A]	ch0_vfb_clk_in_s0/F
1000.684	0.684	tNET	RR	1	R14C23[0][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_s0/CLK
1001.017	0.333	tC2Q	RR	4	R14C23[0][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_s0/Q
1001.856	0.839	tNET	RR	1	R11C22[1][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
999.999	999.999					active clock edge time
999.999	0.000					HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
1000.329	0.330	tCL	FF	620	BOTTOMSIDE[1]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
1000.520	0.191	tNET	FF	1	R11C22[1][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0/CLK
1000.550	0.030	tUnc				Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0
1000.563	0.012	tHld		1	R11C22[1][B]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_1_s0

Path Statistics:

Clock Skew	-0.162
Hold Relationship	-0.001
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.684, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.839, 71.568%; tC2Q: 0.333, 28.432%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.191, 100.000%

Path4

Path Summary:

Slack	1.293
Data Arrival Time	1001.856
Data Required Time	1000.563
From	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_s0
To	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_0_s0
Launch Clk	ch0_vfb_clk_in:[R]
Latch Clk	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk:[F]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
1000.000	1000.000					active clock edge time
1000.000	0.000					ch0_vfb_clk_in
1000.000	0.000	tCL	RR	63	R2C20[0][A]	ch0_vfb_clk_in_s0/F
1000.684	0.684	tNET	RR	1	R14C23[0][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_s0/CLK
1001.017	0.333	tC2Q	RR	4	R14C23[0][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_wr_rst_s0/Q
1001.856	0.839	tNET	RR	1	R11C22[2][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_0_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
999.999	999.999					active clock edge time
999.999	0.000					HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
1000.329	0.330	tCL	FF	620	BOTTOMSIDE[1]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
1000.520	0.191	tNET	FF	1	R11C22[2][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_0_s0/CLK
1000.550	0.030	tUnc				Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_0_s0
1000.563	0.012	tHld		1	R11C22[2][A]	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r_0_s0

Path Statistics:

Clock Skew	-0.162
Hold Relationship	-0.001
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.684, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.839, 71.568%; tC2Q: 0.333, 28.432%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.191, 100.000%

Path5

Path Summary:

Slack	2.507
Data Arrival Time	4.878
Data Required Time	2.371
From	u_Reset_Sync/reset_cnt_1_s0
To	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_0_s3
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/CLK
2.692	0.333	tC2Q	RR	2	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/Q
2.929	0.238	tNET	RR	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I1
3.314	0.385	tINS	RR	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
4.878	1.564	tNET	RR	1	R5C7[2][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R5C7[2][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_0_s3/CLK
2.371	0.012	tHld		1	R5C7[2][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_0_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%
Arrival Data Path Delay	cell: 0.385, 15.281%; route: 1.801, 71.489%; tC2Q: 0.333, 13.230%
Required Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%

Path6

Path Summary:

Slack	2.507
Data Arrival Time	4.878
Data Required Time	2.371
From	u_Reset_Sync/reset_cnt_1_s0
To	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_1_s3
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/CLK
2.692	0.333	tC2Q	RR	2	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/Q
2.929	0.238	tNET	RR	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I1
3.314	0.385	tINS	RR	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
4.878	1.564	tNET	RR	1	R3C9[2][B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_1_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R3C9[2][B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_1_s3/CLK
2.371	0.012	tHld		1	R3C9[2][B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_1_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%
Arrival Data Path Delay	cell: 0.385, 15.281%; route: 1.801, 71.489%; tC2Q: 0.333, 13.230%
Required Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%

Path7

Path Summary:

Slack	2.507
Data Arrival Time	4.878
Data Required Time	2.371
From	u_Reset_Sync/reset_cnt_1_s0
To	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_4_s3
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/CLK
2.692	0.333	tC2Q	RR	2	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/Q
2.929	0.238	tNET	RR	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I1
3.314	0.385	tINS	RR	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
4.878	1.564	tNET	RR	1	R3C10[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_4_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R3C10[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_4_s3/CLK
2.371	0.012	tHld		1	R3C10[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_4_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%
Arrival Data Path Delay	cell: 0.385, 15.281%; route: 1.801, 71.489%; tC2Q: 0.333, 13.230%
Required Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%

Path8

Path Summary:

Slack	2.507
Data Arrival Time	4.878
Data Required Time	2.371
From	u_Reset_Sync/reset_cnt_1_s0
To	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_6_s3
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/CLK
2.692	0.333	tC2Q	RR	2	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/Q
2.929	0.238	tNET	RR	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I1
3.314	0.385	tINS	RR	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
4.878	1.564	tNET	RR	1	R5C7[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_6_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R5C7[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_6_s3/CLK
2.371	0.012	tHld		1	R5C7[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_6_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%
Arrival Data Path Delay	cell: 0.385, 15.281%; route: 1.801, 71.489%; tC2Q: 0.333, 13.230%
Required Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%

Path9

Path Summary:

Slack	2.507
Data Arrival Time	4.878
Data Required Time	2.371
From	u_Reset_Sync/reset_cnt_1_s0
To	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_12_s3
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/CLK
2.692	0.333	tC2Q	RR	2	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/Q
2.929	0.238	tNET	RR	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I1
3.314	0.385	tINS	RR	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
4.878	1.564	tNET	RR	1	R3C10[0][B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_12_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R3C10[0][B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_12_s3/CLK
2.371	0.012	tHld		1	R3C10[0][B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_12_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%
Arrival Data Path Delay	cell: 0.385, 15.281%; route: 1.801, 71.489%; tC2Q: 0.333, 13.230%
Required Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%

Path10

Path Summary:

Slack	2.507
Data Arrival Time	4.878
Data Required Time	2.371
From	u_Reset_Sync/reset_cnt_1_s0
To	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_2_s1
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/CLK
2.692	0.333	tC2Q	RR	2	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/Q
2.929	0.238	tNET	RR	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I1
3.314	0.385	tINS	RR	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
4.878	1.564	tNET	RR	1	R3C9[0][B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R3C9[0][B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_2_s1/CLK
2.371	0.012	tHld		1	R3C9[0][B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%
Arrival Data Path Delay	cell: 0.385, 15.281%; route: 1.801, 71.489%; tC2Q: 0.333, 13.230%
Required Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%

Path11

Path Summary:

Slack	2.507
Data Arrival Time	4.878
Data Required Time	2.371
From	u_Reset_Sync/reset_cnt_1_s0
To	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_3_s1
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/CLK
2.692	0.333	tC2Q	RR	2	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/Q
2.929	0.238	tNET	RR	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I1
3.314	0.385	tINS	RR	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
4.878	1.564	tNET	RR	1	R3C9[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R3C9[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_3_s1/CLK
2.371	0.012	tHld		1	R3C9[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%
Arrival Data Path Delay	cell: 0.385, 15.281%; route: 1.801, 71.489%; tC2Q: 0.333, 13.230%
Required Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%

Path12

Path Summary:

Slack	2.507
Data Arrival Time	4.878
Data Required Time	2.371
From	u_Reset_Sync/reset_cnt_1_s0
To	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_5_s1
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/CLK
2.692	0.333	tC2Q	RR	2	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/Q
2.929	0.238	tNET	RR	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I1
3.314	0.385	tINS	RR	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
4.878	1.564	tNET	RR	1	R3C10[1][B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R3C10[1][B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_5_s1/CLK
2.371	0.012	tHld		1	R3C10[1][B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%
Arrival Data Path Delay	cell: 0.385, 15.281%; route: 1.801, 71.489%; tC2Q: 0.333, 13.230%
Required Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%

Path13

Path Summary:

Slack	2.507
Data Arrival Time	4.878
Data Required Time	2.371
From	u_Reset_Sync/reset_cnt_1_s0
To	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_7_s1
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/CLK
2.692	0.333	tC2Q	RR	2	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/Q
2.929	0.238	tNET	RR	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I1
3.314	0.385	tINS	RR	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
4.878	1.564	tNET	RR	1	R5C7[1][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R5C7[1][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_7_s1/CLK
2.371	0.012	tHld		1	R5C7[1][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_7_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%
Arrival Data Path Delay	cell: 0.385, 15.281%; route: 1.801, 71.489%; tC2Q: 0.333, 13.230%
Required Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%

Path14

Path Summary:

Slack	2.507
Data Arrival Time	4.878
Data Required Time	2.371
From	u_Reset_Sync/reset_cnt_1_s0
To	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_8_s1
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/CLK
2.692	0.333	tC2Q	RR	2	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/Q
2.929	0.238	tNET	RR	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I1
3.314	0.385	tINS	RR	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
4.878	1.564	tNET	RR	1	R3C8[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R3C8[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_8_s1/CLK
2.371	0.012	tHld		1	R3C8[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_8_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%
Arrival Data Path Delay	cell: 0.385, 15.281%; route: 1.801, 71.489%; tC2Q: 0.333, 13.230%
Required Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%

Path15

Path Summary:

Slack	2.507
Data Arrival Time	4.878
Data Required Time	2.371
From	u_Reset_Sync/reset_cnt_1_s0
To	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_9_s1
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/CLK
2.692	0.333	tC2Q	RR	2	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/Q
2.929	0.238	tNET	RR	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I1
3.314	0.385	tINS	RR	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
4.878	1.564	tNET	RR	1	R4C8[2][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R4C8[2][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_9_s1/CLK
2.371	0.012	tHld		1	R4C8[2][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_9_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%
Arrival Data Path Delay	cell: 0.385, 15.281%; route: 1.801, 71.489%; tC2Q: 0.333, 13.230%
Required Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%

Path16

Path Summary:

Slack	2.507
Data Arrival Time	4.878
Data Required Time	2.371
From	u_Reset_Sync/reset_cnt_1_s0
To	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_10_s1
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/CLK
2.692	0.333	tC2Q	RR	2	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/Q
2.929	0.238	tNET	RR	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I1
3.314	0.385	tINS	RR	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
4.878	1.564	tNET	RR	1	R4C8[0][B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_10_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R4C8[0][B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_10_s1/CLK
2.371	0.012	tHld		1	R4C8[0][B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_10_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%
Arrival Data Path Delay	cell: 0.385, 15.281%; route: 1.801, 71.489%; tC2Q: 0.333, 13.230%
Required Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%

Path17

Path Summary:

Slack	2.507
Data Arrival Time	4.878
Data Required Time	2.371
From	u_Reset_Sync/reset_cnt_1_s0
To	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_11_s1
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/CLK
2.692	0.333	tC2Q	RR	2	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/Q
2.929	0.238	tNET	RR	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I1
3.314	0.385	tINS	RR	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
4.878	1.564	tNET	RR	1	R4C8[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_11_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R4C8[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_11_s1/CLK
2.371	0.012	tHld		1	R4C8[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_11_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%
Arrival Data Path Delay	cell: 0.385, 15.281%; route: 1.801, 71.489%; tC2Q: 0.333, 13.230%
Required Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%

Path18

Path Summary:

Slack	2.507
Data Arrival Time	4.878
Data Required Time	2.371
From	u_Reset_Sync/reset_cnt_1_s0
To	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_13_s1
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/CLK
2.692	0.333	tC2Q	RR	2	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/Q
2.929	0.238	tNET	RR	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I1
3.314	0.385	tINS	RR	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
4.878	1.564	tNET	RR	1	R3C10[2][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_13_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R3C10[2][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_13_s1/CLK
2.371	0.012	tHld		1	R3C10[2][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_13_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%
Arrival Data Path Delay	cell: 0.385, 15.281%; route: 1.801, 71.489%; tC2Q: 0.333, 13.230%
Required Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%

Path19

Path Summary:

Slack	2.507
Data Arrival Time	4.878
Data Required Time	2.371
From	u_Reset_Sync/reset_cnt_1_s0
To	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_14_s1
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/CLK
2.692	0.333	tC2Q	RR	2	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/Q
2.929	0.238	tNET	RR	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I1
3.314	0.385	tINS	RR	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
4.878	1.564	tNET	RR	1	R3C10[1][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_14_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R3C10[1][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_14_s1/CLK
2.371	0.012	tHld		1	R3C10[1][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_14_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%
Arrival Data Path Delay	cell: 0.385, 15.281%; route: 1.801, 71.489%; tC2Q: 0.333, 13.230%
Required Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%

Path20

Path Summary:

Slack	2.507
Data Arrival Time	4.878
Data Required Time	2.371
From	u_Reset_Sync/reset_cnt_1_s0
To	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_15_s1
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/CLK
2.692	0.333	tC2Q	RR	2	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/Q
2.929	0.238	tNET	RR	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I1
3.314	0.385	tINS	RR	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
4.878	1.564	tNET	RR	1	R3C9[1][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_15_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R3C9[1][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_15_s1/CLK
2.371	0.012	tHld		1	R3C9[1][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_cnt_15_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%
Arrival Data Path Delay	cell: 0.385, 15.281%; route: 1.801, 71.489%; tC2Q: 0.333, 13.230%
Required Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%

Path21

Path Summary:

Slack	2.507
Data Arrival Time	4.878
Data Required Time	2.371
From	u_Reset_Sync/reset_cnt_1_s0
To	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/cs_memsync_1_s0
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/CLK
2.692	0.333	tC2Q	RR	2	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/Q
2.929	0.238	tNET	RR	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I1
3.314	0.385	tINS	RR	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
4.878	1.564	tNET	RR	1	R5C10[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/cs_memsync_1_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R5C10[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/cs_memsync_1_s0/CLK
2.371	0.012	tHld		1	R5C10[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/cs_memsync_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%
Arrival Data Path Delay	cell: 0.385, 15.281%; route: 1.801, 71.489%; tC2Q: 0.333, 13.230%
Required Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%

Path22

Path Summary:

Slack	2.507
Data Arrival Time	4.878
Data Required Time	2.371
From	u_Reset_Sync/reset_cnt_1_s0
To	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_syn_1_s0
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/CLK
2.692	0.333	tC2Q	RR	2	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/Q
2.929	0.238	tNET	RR	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I1
3.314	0.385	tINS	RR	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
4.878	1.564	tNET	RR	1	R5C6[1][B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R5C6[1][B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_syn_1_s0/CLK
2.371	0.012	tHld		1	R5C6[1][B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/lock_syn_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%
Arrival Data Path Delay	cell: 0.385, 15.281%; route: 1.801, 71.489%; tC2Q: 0.333, 13.230%
Required Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%

Path23

Path Summary:

Slack	2.507
Data Arrival Time	4.878
Data Required Time	2.371
From	u_Reset_Sync/reset_cnt_1_s0
To	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/count_0_s0
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/CLK
2.692	0.333	tC2Q	RR	2	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/Q
2.929	0.238	tNET	RR	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I1
3.314	0.385	tINS	RR	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
4.878	1.564	tNET	RR	1	R4C10[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/count_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R4C10[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/count_0_s0/CLK
2.371	0.012	tHld		1	R4C10[0][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/count_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%
Arrival Data Path Delay	cell: 0.385, 15.281%; route: 1.801, 71.489%; tC2Q: 0.333, 13.230%
Required Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%

Path24

Path Summary:

Slack	2.507
Data Arrival Time	4.878
Data Required Time	2.371
From	u_Reset_Sync/reset_cnt_1_s0
To	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/count_1_s0
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/CLK
2.692	0.333	tC2Q	RR	2	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/Q
2.929	0.238	tNET	RR	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I1
3.314	0.385	tINS	RR	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
4.878	1.564	tNET	RR	1	R4C10[2][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/count_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R4C10[2][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/count_1_s0/CLK
2.371	0.012	tHld		1	R4C10[2][A]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/count_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%
Arrival Data Path Delay	cell: 0.385, 15.281%; route: 1.801, 71.489%; tC2Q: 0.333, 13.230%
Required Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%

Path25

Path Summary:

Slack	2.507
Data Arrival Time	4.878
Data Required Time	2.371
From	u_Reset_Sync/reset_cnt_1_s0
To	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/count_2_s0
Launch Clk	I_clk:[R]
Latch Clk	I_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/CLK
2.692	0.333	tC2Q	RR	2	R11C28[0][B]	u_Reset_Sync/reset_cnt_1_s0/Q
2.929	0.238	tNET	RR	1	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/I1
3.314	0.385	tINS	RR	122	R11C28[3][B]	u_Reset_Sync/sys_resetn_s/F
4.878	1.564	tNET	RR	1	R4C10[1][B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/count_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					I_clk
0.000	0.000	tCL	RR	1	IOT13[A]	I_clk_ibuf/I
1.392	1.392	tINS	RR	159	IOT13[A]	I_clk_ibuf/O
2.358	0.966	tNET	RR	1	R4C10[1][B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/count_2_s0/CLK
2.371	0.012	tHld		1	R4C10[1][B]	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/u_hpram_sync/count_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%
Arrival Data Path Delay	cell: 0.385, 15.281%; route: 1.801, 71.489%; tC2Q: 0.333, 13.230%
Required Clock Path Delay	cell: 1.392, 59.024%; route: 0.966, 40.976%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	4.965
Actual Width:	6.215
Required Width:	1.250
Type:	Low Pulse Width
Clock:	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
Objects:	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_grant_i_d1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.289	0.000			active clock edge time
6.289	0.000			HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
6.619	0.330	tCL	FF	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
6.876	0.257	tNET	FF	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_grant_i_d1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
12.579	0.000			active clock edge time
12.579	0.000			HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
12.909	0.330	tCL	RR	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
13.092	0.183	tNET	RR	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_grant_i_d1_s0/CLK

MPW2

MPW Summary:

Slack:	4.965
Actual Width:	6.215
Required Width:	1.250
Type:	Low Pulse Width
Clock:	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
Objects:	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_grant_i_d2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.289	0.000			active clock edge time
6.289	0.000			HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
6.619	0.330	tCL	FF	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
6.876	0.257	tNET	FF	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_grant_i_d2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
12.579	0.000			active clock edge time
12.579	0.000			HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
12.909	0.330	tCL	RR	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
13.092	0.183	tNET	RR	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/dma_wr_grant_i_d2_s0/CLK

MPW3

MPW Summary:

Slack:	4.965
Actual Width:	6.215
Required Width:	1.250
Type:	Low Pulse Width
Clock:	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
Objects:	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_6_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.289	0.000			active clock edge time
6.289	0.000			HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
6.619	0.330	tCL	FF	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
6.876	0.257	tNET	FF	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_6_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
12.579	0.000			active clock edge time
12.579	0.000			HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
12.909	0.330	tCL	RR	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
13.092	0.183	tNET	RR	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Big.rq1_wptr_6_s1/CLK

MPW4

MPW Summary:

Slack:	4.965
Actual Width:	6.215
Required Width:	1.250
Type:	Low Pulse Width
Clock:	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
Objects:	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_4_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.289	0.000			active clock edge time
6.289	0.000			HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
6.619	0.330	tCL	FF	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
6.876	0.257	tNET	FF	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_4_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
12.579	0.000			active clock edge time
12.579	0.000			HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
12.909	0.330	tCL	RR	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
13.092	0.183	tNET	RR	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/Rnum_4_s0/CLK

MPW5

MPW Summary:

Slack:	4.965
Actual Width:	6.215
Required Width:	1.250
Type:	Low Pulse Width
Clock:	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
Objects:	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/read_dog_cnt_8_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.289	0.000			active clock edge time
6.289	0.000			HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
6.619	0.330	tCL	FF	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
6.876	0.257	tNET	FF	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/read_dog_cnt_8_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
12.579	0.000			active clock edge time
12.579	0.000			HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
12.909	0.330	tCL	RR	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
13.092	0.183	tNET	RR	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/read_dog_cnt_8_s0/CLK

MPW6

MPW Summary:

Slack:	4.965
Actual Width:	6.215
Required Width:	1.250
Type:	Low Pulse Width
Clock:	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
Objects:	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/read_dog_cnt_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.289	0.000			active clock edge time
6.289	0.000			HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
6.619	0.330	tCL	FF	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
6.876	0.257	tNET	FF	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/read_dog_cnt_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
12.579	0.000			active clock edge time
12.579	0.000			HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
12.909	0.330	tCL	RR	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
13.092	0.183	tNET	RR	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/read_dog_cnt_0_s0/CLK

MPW7

MPW Summary:

Slack:	4.965
Actual Width:	6.215
Required Width:	1.250
Type:	Low Pulse Width
Clock:	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
Objects:	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d3_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.289	0.000			active clock edge time
6.289	0.000			HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
6.619	0.330	tCL	FF	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
6.876	0.257	tNET	FF	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d3_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
12.579	0.000			active clock edge time
12.579	0.000			HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
12.909	0.330	tCL	RR	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
13.092	0.183	tNET	RR	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d3_s0/CLK

MPW8

MPW Summary:

Slack:	4.965
Actual Width:	6.215
Required Width:	1.250
Type:	Low Pulse Width
Clock:	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
Objects:	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d5_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.289	0.000			active clock edge time
6.289	0.000			HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
6.619	0.330	tCL	FF	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
6.876	0.257	tNET	FF	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d5_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
12.579	0.000			active clock edge time
12.579	0.000			HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
12.909	0.330	tCL	RR	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
13.092	0.183	tNET	RR	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d5_s0/CLK

MPW9

MPW Summary:

Slack:	4.965
Actual Width:	6.215
Required Width:	1.250
Type:	Low Pulse Width
Clock:	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
Objects:	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d6_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.289	0.000			active clock edge time
6.289	0.000			HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
6.619	0.330	tCL	FF	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
6.876	0.257	tNET	FF	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d6_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
12.579	0.000			active clock edge time
12.579	0.000			HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
12.909	0.330	tCL	RR	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
13.092	0.183	tNET	RR	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d6_s0/CLK

MPW10

MPW Summary:

Slack:	4.965
Actual Width:	6.215
Required Width:	1.250
Type:	Low Pulse Width
Clock:	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
Objects:	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d4_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.289	0.000			active clock edge time
6.289	0.000			HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
6.619	0.330	tCL	FF	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
6.876	0.257	tNET	FF	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d4_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
12.579	0.000			active clock edge time
12.579	0.000			HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk
12.909	0.330	tCL	RR	HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT
13.092	0.183	tNET	RR	Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/dma_vs_n_d4_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
620	dma_clk	-6.329	0.257
395	ddr_rsti	-6.778	2.462
176	pix_clk	-4.457	0.257
159	I_clk_d	-8.805	2.041
141	init_calib	-6.329	2.186
129	n14_11	-6.329	3.294
122	sys_resetn	-8.805	3.278
84	XCLK_d	68.824	0.661
70	busy_sr[31]	71.765	2.610
63	ch0_vfb_clk_in	-2.897	1.078

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R9C29	83.33%
R11C8	83.33%
R12C19	81.94%
R4C18	81.94%
R11C7	81.94%
R15C11	80.56%
R12C9	80.56%
R17C12	80.56%
R18C7	80.56%
R7C29	79.17%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name I_clk -period 37.037 -waveform {0 18.518} [get_ports {I_clk}] -add
TC_CLOCK	Actived	create_clock -name serial_clk -period 2.694 -waveform {0 1.347} [get_nets {serial_clk}] -add
TC_CLOCK	Actived	create_clock -name pix_clk -period 13.468 -waveform {0 6.734} [get_nets {pix_clk}] -add