PnR Messages

Report Title PnR Report
Design File /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/camera_hdmi/impl/gwsynthesis/camera_hdmi.vg
Physical Constraints File /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/camera_hdmi/src/dk_video.cst
Timing Constraints File /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/camera_hdmi/src/dk_video.sdc
Tool Version V1.9.11
Part Number GW1NSR-LV4CQN48PC6/I5
Device GW1NSR-4C
Created Time Wed Mar 26 11:03:54 2025
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

PnR Details

Place & Route Process Running placement: Placement Phase 0: CPU time = 0h 0m 0.839s, Elapsed time = 0h 0m 0.843s Placement Phase 1: CPU time = 0h 0m 0.277s, Elapsed time = 0h 0m 0.287s Placement Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s Placement Phase 3: CPU time = 0h 0m 12s, Elapsed time = 0h 0m 12s Total Placement: CPU time = 0h 0m 14s, Elapsed time = 0h 0m 14s Running routing: Routing Phase 0: CPU time = 0h 0m 0.002s, Elapsed time = 0h 0m 0.003s Routing Phase 1: CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.368s Routing Phase 2: CPU time = 0h 0m 13s, Elapsed time = 0h 0m 13s Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Total Routing: CPU time = 0h 0m 13s, Elapsed time = 0h 0m 13s Generate output files: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
Total Time and Memory Usage CPU time = 0h 0m 29s, Elapsed time = 0h 0m 28s, Peak memory usage = 270MB

Resource

Resource Usage Summary:

Resource Usage Utilization
Logic 1838/4608 40%
    --LUT,ALU,ROM16 1838(1653 LUT, 185 ALU, 0 ROM16) -
    --SSRAM(RAM16) 0 -
Register 1067/3612 30%
    --Logic Register as Latch 0/3456 0%
    --Logic Register as FF 1065/3456 31%
    --I/O Register as Latch 0/156 0%
    --I/O Register as FF 2/156 2%
CLS 1253/2304 55%
I/O Port 29/39 75%
I/O Buf 21 -
    --Input Buf 12 -
    --Output Buf 9 -
    --Inout Buf 0 -
IOLOGIC 8 IDES4
12 OSER4
4 OSER10
10 IODELAY
 53%
BSRAM 2 SDPB
1 SDPX9B
1 pROM
 40%

I/O Bank Usage Summary:

I/O Bank UsageUtilization
bank 0 1/912%
bank 1 8/1080%
bank 2 9/9100%
bank 3 11/11100%

Clock Resource Usage Summary:

Clock Resource Usage Utilization
PRIMARY 5/8 63%
LW 6/8 75%
GCLK_PIN 5/5 100%
CLKDIV 2/6 34%
DHCEN 1/12 9%
DLL 1/2 50%
PLLVR 2/2 100%

Global Clock Signals:

Signal Global Clock Location
I_clk_d PRIMARY LEFT RIGHT
ch0_vfb_clk_in PRIMARY RIGHT
pix_clk PRIMARY LEFT RIGHT
dma_clk PRIMARY LEFT RIGHT
XCLK_d PRIMARY LEFT RIGHT
hdmi_rst_n LW -
sys_resetn LW -
n14_11 LW -
Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r[1] LW -
Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r[1] LW -
HyperRAM_Memory_Interface_Top_inst/u_hpram_top/ddr_rsti LW -
memory_clk HCLK TOP[1] BOTTOM[1]
serial_clk HCLK RIGHT[1]

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site CFG IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor BankVccio
I_clk - 45/1 Y in IOT13[A] LPLL_T_in LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
I_rst_n - 14/3 Y in IOB4[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
VSYNC - 43/1 Y in IOT17[A] GCLKT_0 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
HREF - 42/1 Y in IOT20[B] GCLKC_1 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
PIXDATA[0] - 22/3 Y in IOB22[A] GCLKT_4 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
PIXDATA[1] - 21/3 Y in IOB16[B] GCLKC_5 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
PIXDATA[2] - 17/3 Y in IOB6[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
PIXDATA[3] - 19/3 Y in IOB13[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
PIXDATA[4] - 20/3 Y in IOB16[A] GCLKT_5 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
PIXDATA[5] - 18/3 Y in IOB13[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
PIXDATA[6] - 16/3 Y in IOB6[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
PIXDATA[7] - 23/3 Y in IOB22[B] GCLKC_4 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
PIXDATA[8] - 39/1 Y in IOT26[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
PIXDATA[9] - 40/1 Y in IOT26[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
PIXCLK - 41/1 Y in IOT20[A] GCLKT_1 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
key - 15/3 Y in IOB5[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
O_led[0] - 10/0 Y out IOT7[A] MODE1 LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
O_led[1] - 13/3 N out IOB4[A] - LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
XCLK - 33/2 Y out IOR9[B] GCLKC_2 LVCMOS25 8 NONE NA NA OFF NA OFF NA 2.5
O_hpram_ck[0] - p1-13/3 - out IOB23[A] - LVCMOS18 - NONE - - - - - - -
O_hpram_ck_n[0] - p1-14/3 - out IOB15[B] - LVCMOS18 - NONE - - - - - - -
O_hpram_cs_n[0] - p1-15/3 - out IOB15[A] - LVCMOS18 - NONE - - - - - - -
O_hpram_reset_n[0] - p1-22/3 - out IOB5[B] - LVCMOS18 - NONE - - - - - - -
O_tmds_clk_p O_tmds_clk_n 28,27/2 Y out IOR17 - LVDS25 3.5 NONE NA NA NA NA NA NA 2.5
O_tmds_data_p[0] O_tmds_data_n[0] 30,29/2 Y out IOR15 - LVDS25 3.5 NONE NA NA NA NA NA NA 2.5
O_tmds_data_p[1] O_tmds_data_n[1] 32,31/2 Y out IOR11 GCLKT_3 LVDS25 3.5 NONE NA NA NA NA NA NA 2.5
O_tmds_data_p[2] O_tmds_data_n[2] 35,34/2 Y out IOR2 RPLL_T_in LVDS25 3.5 NONE NA NA NA NA NA NA 2.5
SDA - 46/1 Y io IOT13[B] LPLL_C_in LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
SCL - 44/1 Y io IOT17[B] GCLKC_0 LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
IO_hpram_dq[0] - p1-19/3 - io IOB7[A] - LVCMOS18 - UP - - - - - - -
IO_hpram_dq[1] - p1-18/3 - io IOB7[B] - LVCMOS18 - UP - - - - - - -
IO_hpram_dq[2] - p1-17/3 - io IOB14[A] - LVCMOS18 - UP - - - - - - -
IO_hpram_dq[3] - p1-16/3 - io IOB14[B] - LVCMOS18 - UP - - - - - - -
IO_hpram_dq[4] - p1-10/3 - io IOB24[B] - LVCMOS18 - UP - - - - - - -
IO_hpram_dq[5] - p1-9/3 - io IOB25[A] - LVCMOS18 - UP - - - - - - -
IO_hpram_dq[6] - p1-8/3 - io IOB25[B] - LVCMOS18 - UP - - - - - - -
IO_hpram_dq[7] - p1-7/3 - io IOB29[A] - LVCMOS18 - UP - - - - - - -
IO_hpram_rwds[0] - p1-6/3 - io IOB29[B] - LVCMOS18 - UP - - - - - - -

All Package Pins:

Loc./Bank Signal Dir. Site CFG IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor Bank Vccio
3/0 - in IOT2[A] TDI LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
4/0 - out IOT2[B] TDO LVCMOS18 8 NONE NA NA OFF NA NA NA 3.3
6/0 - in IOT3[A] TMS LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
7/0 - in IOT3[B] TCK LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
8/0 - in IOT4[B] JTAGSEL_N LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
9/0 - in IOT5[B] DONE LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
10/0 O_led[0] out IOT7[A] MODE1 LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
1/0 - in IOT10[A] MCLK/D4 LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
2/0 - in IOT10[B] MCS_N/D5 LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
48/1 - in IOT11[A] MO/D6 LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
47/1 - in IOT11[B] MI/D7 LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
45/1 I_clk in IOT13[A] LPLL_T_in LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
46/1 SDA out IOT13[B] LPLL_C_in LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
43/1 VSYNC in IOT17[A] GCLKT_0 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
44/1 SCL out IOT17[B] GCLKC_0 LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
41/1 PIXCLK in IOT20[A] GCLKT_1 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
42/1 HREF in IOT20[B] GCLKC_1 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
39/1 PIXDATA[8] in IOT26[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
40/1 PIXDATA[9] in IOT26[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
13/3 O_led[1] out IOB4[A] - LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
14/3 I_rst_n in IOB4[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
15/3 key in IOB5[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
p1-22/3 O_hpram_reset_n[0] out IOB5[B] - LVCMOS18 - NONE - - - - - - -
16/3 PIXDATA[6] in IOB6[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
17/3 PIXDATA[2] in IOB6[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
p1-19/3 IO_hpram_dq[0] io IOB7[A] - LVCMOS18 - UP - - - - - - -
p1-18/3 IO_hpram_dq[1] io IOB7[B] - LVCMOS18 - UP - - - - - - -
18/3 PIXDATA[5] in IOB13[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
19/3 PIXDATA[3] in IOB13[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
p1-17/3 IO_hpram_dq[2] io IOB14[A] - LVCMOS18 - UP - - - - - - -
p1-16/3 IO_hpram_dq[3] io IOB14[B] - LVCMOS18 - UP - - - - - - -
p1-15/3 O_hpram_cs_n[0] out IOB15[A] - LVCMOS18 - NONE - - - - - - -
p1-14/3 O_hpram_ck_n[0] out IOB15[B] - LVCMOS18 - NONE - - - - - - -
20/3 PIXDATA[4] in IOB16[A] GCLKT_5 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
21/3 PIXDATA[1] in IOB16[B] GCLKC_5 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
22/3 PIXDATA[0] in IOB22[A] GCLKT_4 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
23/3 PIXDATA[7] in IOB22[B] GCLKC_4 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
p1-13/3 O_hpram_ck[0] out IOB23[A] - LVCMOS18 - NONE - - - - - - -
p1-10/3 IO_hpram_dq[4] io IOB24[B] - LVCMOS18 - UP - - - - - - -
p1-9/3 IO_hpram_dq[5] io IOB25[A] - LVCMOS18 - UP - - - - - - -
p1-8/3 IO_hpram_dq[6] io IOB25[B] - LVCMOS18 - UP - - - - - - -
p1-7/3 IO_hpram_dq[7] io IOB29[A] - LVCMOS18 - UP - - - - - - -
p1-6/3 IO_hpram_rwds[0] io IOB29[B] - LVCMOS18 - UP - - - - - - -
35/2 O_tmds_data_p[2] out IOR2[A] RPLL_T_in LVDS25 3.5 NONE NA NA NA NA NA NA 2.5
34/2 O_tmds_data_n[2] out IOR2[B] RPLL_C_in LVDS25 3.5 NONE NA NA NA NA NA NA 2.5
33/2 XCLK out IOR9[B] GCLKC_2 LVCMOS25 8 NONE NA NA OFF NA OFF NA 2.5
32/2 O_tmds_data_p[1] out IOR11[A] GCLKT_3 LVDS25 3.5 NONE NA NA NA NA NA NA 2.5
31/2 O_tmds_data_n[1] out IOR11[B] GCLKC_3 LVDS25 3.5 NONE NA NA NA NA NA NA 2.5
30/2 O_tmds_data_p[0] out IOR15[A] - LVDS25 3.5 NONE NA NA NA NA NA NA 2.5
29/2 O_tmds_data_n[0] out IOR15[B] - LVDS25 3.5 NONE NA NA NA NA NA NA 2.5
28/2 O_tmds_clk_p out IOR17[A] - LVDS25 3.5 NONE NA NA NA NA NA NA 2.5
27/2 O_tmds_clk_n out IOR17[B] - LVDS25 3.5 NONE NA NA NA NA NA NA 2.5