Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/camera_hdmi/src/dvi_tx/dvi_tx.v /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/camera_hdmi/src/gowin_pllvr/GW_PLLVR.v /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/camera_hdmi/src/gowin_pllvr/TMDS_PLLVR.v /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/camera_hdmi/src/hyperram_memory_interface/hyperram_memory_interface.v /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/camera_hdmi/src/ov2640/I2C_Interface.v /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/camera_hdmi/src/ov2640/OV2640_Controller.v /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/camera_hdmi/src/ov2640/OV2640_Registers.v /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/camera_hdmi/src/syn_code/syn_gen.v /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/camera_hdmi/src/testpattern.v /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/camera_hdmi/src/video_frame_buffer/video_frame_buffer.v /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/camera_hdmi/src/video_top.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.11 |
| Part Number | GW1NSR-LV4CQN48PC6/I5 |
| Device | GW1NSR-4C |
| Created Time | Wed Mar 26 11:03:23 2025 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | video_top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.452s, Elapsed time = 0h 0m 0.437s, Peak memory usage = 163.777MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.048s, Elapsed time = 0h 0m 0.048s, Peak memory usage = 164.551MB Optimizing Phase 1: CPU time = 0h 0m 0.098s, Elapsed time = 0h 0m 0.097s, Peak memory usage = 164.551MB Optimizing Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.077s, Peak memory usage = 164.551MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.024s, Elapsed time = 0h 0m 0.034s, Peak memory usage = 164.867MB Inferring Phase 1: CPU time = 0h 0m 0.005s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 164.867MB Inferring Phase 2: CPU time = 0h 0m 0.007s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 165.004MB Inferring Phase 3: CPU time = 0h 0m 0.006s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 165.004MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.051s, Elapsed time = 0h 0m 0.048s, Peak memory usage = 165.004MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.019s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 165.004MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.01s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 165.004MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 192.297MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.186s, Elapsed time = 0h 0m 0.194s, Peak memory usage = 192.453MB Generate output files: CPU time = 0h 0m 0.422s, Elapsed time = 0h 0m 0.451s, Peak memory usage = 192.453MB |
| Total Time and Memory Usage | CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 192.453MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 29 |
| Embedded Port | 13 |
| I/O Buf | 34 |
| IBUF | 12 |
| OBUF | 8 |
| TBUF | 1 |
| IOBUF | 9 |
| TLVDS_OBUF | 4 |
| Register | 1067 |
| DFF | 2 |
| DFFE | 49 |
| DFFS | 10 |
| DFFSE | 32 |
| DFFR | 3 |
| DFFP | 47 |
| DFFPE | 5 |
| DFFC | 652 |
| DFFCE | 267 |
| LUT | 1639 |
| LUT2 | 426 |
| LUT3 | 487 |
| LUT4 | 726 |
| ALU | 149 |
| ALU | 149 |
| INV | 25 |
| INV | 25 |
| IOLOGIC | 34 |
| IDES4 | 8 |
| OSER4 | 12 |
| OSER10 | 4 |
| IODELAY | 10 |
| BSRAM | 4 |
| SDPB | 2 |
| SDPX9B | 1 |
| pROM | 1 |
| CLOCK | 5 |
| CLKDIV | 2 |
| DHCEN | 1 |
| PLLVR | 2 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 1813(1664 LUT, 149 ALU) / 4608 | 40% |
| Register | 1067 / 3612 | 30% |
| --Register as Latch | 0 / 3612 | 0% |
| --Register as FF | 1067 / 3612 | 30% |
| BSRAM | 4 / 10 | 40% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | I_clk | Base | 37.037 | 27.000 | 0.000 | 18.519 | I_clk_ibuf/I | ||
| 2 | ch0_vfb_clk_in | Base | 20.000 | 50.000 | 0.000 | 10.000 | ch0_vfb_clk_in_s0/F | ||
| 3 | GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk | Generated | 6.289 | 159.000 | 0.000 | 3.145 | I_clk_ibuf/I | I_clk | GW_PLLVR_inst/pllvr_inst/CLKOUT |
| 4 | GW_PLLVR_inst/pllvr_inst/CLKOUTP.default_gen_clk | Generated | 6.289 | 159.000 | 0.000 | 3.145 | I_clk_ibuf/I | I_clk | GW_PLLVR_inst/pllvr_inst/CLKOUTP |
| 5 | GW_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk | Generated | 12.579 | 79.500 | 0.000 | 6.289 | I_clk_ibuf/I | I_clk | GW_PLLVR_inst/pllvr_inst/CLKOUTD |
| 6 | GW_PLLVR_inst/pllvr_inst/CLKOUTD3.default_gen_clk | Generated | 18.868 | 53.000 | 0.000 | 9.434 | I_clk_ibuf/I | I_clk | GW_PLLVR_inst/pllvr_inst/CLKOUTD3 |
| 7 | TMDS_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk | Generated | 2.694 | 371.250 | 0.000 | 1.347 | I_clk_ibuf/I | I_clk | TMDS_PLLVR_inst/pllvr_inst/CLKOUT |
| 8 | TMDS_PLLVR_inst/pllvr_inst/CLKOUTP.default_gen_clk | Generated | 2.694 | 371.250 | 0.000 | 1.347 | I_clk_ibuf/I | I_clk | TMDS_PLLVR_inst/pllvr_inst/CLKOUTP |
| 9 | TMDS_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk | Generated | 80.808 | 12.375 | 0.000 | 40.404 | I_clk_ibuf/I | I_clk | TMDS_PLLVR_inst/pllvr_inst/CLKOUTD |
| 10 | TMDS_PLLVR_inst/pllvr_inst/CLKOUTD3.default_gen_clk | Generated | 8.081 | 123.750 | 0.000 | 4.040 | I_clk_ibuf/I | I_clk | TMDS_PLLVR_inst/pllvr_inst/CLKOUTD3 |
| 11 | u_clkdiv/CLKOUT.default_gen_clk | Generated | 13.468 | 74.250 | 0.000 | 6.734 | TMDS_PLLVR_inst/pllvr_inst/CLKOUT | TMDS_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk | u_clkdiv/CLKOUT |
| 12 | HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk | Generated | 12.579 | 79.500 | 0.000 | 6.289 | GW_PLLVR_inst/pllvr_inst/CLKOUT | GW_PLLVR_inst/pllvr_inst/CLKOUT.default_gen_clk | HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | I_clk | 27.000(MHz) | 99.460(MHz) | 5 | TOP |
| 2 | ch0_vfb_clk_in | 50.000(MHz) | 84.486(MHz) | 6 | TOP |
| 3 | TMDS_PLLVR_inst/pllvr_inst/CLKOUTD.default_gen_clk | 12.375(MHz) | 78.253(MHz) | 5 | TOP |
| 4 | u_clkdiv/CLKOUT.default_gen_clk | 74.250(MHz) | 46.526(MHz) | 12 | TOP |
| 5 | HyperRAM_Memory_Interface_Top_inst/u_hpram_top/clkdiv/CLKOUT.default_gen_clk | 79.500(MHz) | 66.062(MHz) | 8 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -8.025 |
| Data Arrival Time | 22.546 |
| Data Required Time | 14.521 |
| From | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0 |
| To | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0 |
| Launch Clk | u_clkdiv/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_clkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | |||
| 0.727 | 0.727 | tCL | RR | 176 | u_clkdiv/CLKOUT |
| 1.453 | 0.726 | tNET | RR | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0/CLK |
| 1.911 | 0.458 | tC2Q | RF | 5 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0/Q |
| 2.871 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n658_s3/I1 |
| 3.970 | 1.099 | tINS | FF | 2 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n658_s3/F |
| 4.930 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n658_s4/I3 |
| 5.556 | 0.626 | tINS | FF | 5 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n658_s4/F |
| 6.516 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s15/I0 |
| 7.548 | 1.032 | tINS | FF | 4 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s15/F |
| 8.508 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n605_s2/I0 |
| 9.540 | 1.032 | tINS | FF | 5 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n605_s2/F |
| 10.500 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_3_s11/I1 |
| 11.599 | 1.099 | tINS | FF | 5 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_3_s11/F |
| 12.559 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15/I2 |
| 13.381 | 0.822 | tINS | FF | 4 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15/F |
| 14.341 | 0.960 | tNET | FF | 2 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n237_s5/I1 |
| 15.386 | 1.045 | tINS | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n237_s5/COUT |
| 15.386 | 0.000 | tNET | FF | 2 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n236_s4/CIN |
| 15.949 | 0.563 | tINS | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n236_s4/SUM |
| 16.909 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n578_s6/I3 |
| 17.535 | 0.626 | tINS | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n578_s6/F |
| 18.495 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n578_s3/I0 |
| 19.527 | 1.032 | tINS | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n578_s3/F |
| 20.487 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n578_s1/I1 |
| 21.586 | 1.099 | tINS | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n578_s1/F |
| 22.546 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 13.468 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | |||
| 14.195 | 0.727 | tCL | RR | 176 | u_clkdiv/CLKOUT |
| 14.921 | 0.726 | tNET | RR | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0/CLK |
| 14.521 | -0.400 | tSu | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_4_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 13.468 |
| Logic Level: | 12 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 10.075, 47.764%; route: 10.560, 50.063%; tC2Q: 0.458, 2.173% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 2
Path Summary:| Slack | -6.324 |
| Data Arrival Time | 20.845 |
| Data Required Time | 14.521 |
| From | Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s |
| To | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor_s0 |
| Launch Clk | u_clkdiv/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_clkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | |||
| 0.727 | 0.727 | tCL | RR | 176 | u_clkdiv/CLKOUT |
| 1.453 | 0.726 | tNET | RR | 32 | Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s/CLKB |
| 4.913 | 3.460 | tC2Q | RF | 1 | Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s/DO[5] |
| 5.873 | 0.960 | tNET | FF | 1 | Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/O_vout0_data_d_5_s/I1 |
| 6.972 | 1.099 | tINS | FF | 1 | Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/O_vout0_data_d_5_s/F |
| 7.932 | 0.960 | tNET | FF | 1 | rgb_data_10_s1/I1 |
| 9.031 | 1.099 | tINS | FF | 4 | rgb_data_10_s1/F |
| 9.991 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n114_s8/I2 |
| 10.813 | 0.822 | tINS | FF | 2 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n114_s8/F |
| 11.773 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n114_s6/I1 |
| 12.872 | 1.099 | tINS | FF | 2 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n114_s6/F |
| 13.832 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n114_s5/I2 |
| 14.654 | 0.822 | tINS | FF | 2 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n114_s5/F |
| 15.614 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n114_s2/I1 |
| 16.713 | 1.099 | tINS | FF | 2 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n114_s2/F |
| 17.673 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n114_s3/I3 |
| 18.299 | 0.626 | tINS | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n114_s3/F |
| 19.259 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n114_s0/I3 |
| 19.885 | 0.626 | tINS | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/n114_s0/F |
| 20.845 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 13.468 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | |||
| 14.195 | 0.727 | tCL | RR | 176 | u_clkdiv/CLKOUT |
| 14.921 | 0.726 | tNET | RR | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor_s0/CLK |
| 14.521 | -0.400 | tSu | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/sel_xnor_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 13.468 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 7.292, 37.603%; route: 8.640, 44.555%; tC2Q: 3.460, 17.842% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 3
Path Summary:| Slack | -6.061 |
| Data Arrival Time | 20.582 |
| Data Required Time | 14.521 |
| From | Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s |
| To | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0 |
| Launch Clk | u_clkdiv/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_clkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | |||
| 0.727 | 0.727 | tCL | RR | 176 | u_clkdiv/CLKOUT |
| 1.453 | 0.726 | tNET | RR | 32 | Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s/CLKB |
| 4.913 | 3.460 | tC2Q | RF | 1 | Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s/DO[1] |
| 5.873 | 0.960 | tNET | FF | 1 | Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/O_vout0_data_d_1_s/I1 |
| 6.972 | 1.099 | tINS | FF | 1 | Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/O_vout0_data_d_1_s/F |
| 7.932 | 0.960 | tNET | FF | 1 | rgb_data_4_s2/I0 |
| 8.964 | 1.032 | tINS | FF | 4 | rgb_data_4_s2/F |
| 9.924 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n114_s8/I3 |
| 10.550 | 0.626 | tINS | FF | 2 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n114_s8/F |
| 11.510 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n114_s6/I1 |
| 12.609 | 1.099 | tINS | FF | 2 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n114_s6/F |
| 13.569 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n114_s5/I2 |
| 14.391 | 0.822 | tINS | FF | 2 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n114_s5/F |
| 15.351 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n114_s2/I1 |
| 16.450 | 1.099 | tINS | FF | 2 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n114_s2/F |
| 17.410 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n114_s3/I3 |
| 18.036 | 0.626 | tINS | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n114_s3/F |
| 18.996 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n114_s0/I3 |
| 19.622 | 0.626 | tINS | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/n114_s0/F |
| 20.582 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 13.468 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | |||
| 14.195 | 0.727 | tCL | RR | 176 | u_clkdiv/CLKOUT |
| 14.921 | 0.726 | tNET | RR | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0/CLK |
| 14.521 | -0.400 | tSu | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/sel_xnor_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 13.468 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 7.029, 36.745%; route: 8.640, 45.167%; tC2Q: 3.460, 18.088% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 4
Path Summary:| Slack | -5.865 |
| Data Arrival Time | 20.386 |
| Data Required Time | 14.521 |
| From | Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s |
| To | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor_s0 |
| Launch Clk | u_clkdiv/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_clkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | |||
| 0.727 | 0.727 | tCL | RR | 176 | u_clkdiv/CLKOUT |
| 1.453 | 0.726 | tNET | RR | 32 | Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s/CLKB |
| 4.913 | 3.460 | tC2Q | RF | 1 | Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/Small.mem_Small.mem_0_0_s/DO[12] |
| 5.873 | 0.960 | tNET | FF | 1 | Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/O_vout0_data_d_12_s/I1 |
| 6.972 | 1.099 | tINS | FF | 1 | Video_Frame_Buffer_Top_inst/vfb_hyperram_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/O_vout0_data_d_12_s/F |
| 7.932 | 0.960 | tNET | FF | 1 | rgb_data_20_s1/I1 |
| 9.031 | 1.099 | tINS | FF | 4 | rgb_data_20_s1/F |
| 9.991 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n114_s9/I3 |
| 10.617 | 0.626 | tINS | FF | 2 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n114_s9/F |
| 11.577 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n114_s8/I1 |
| 12.676 | 1.099 | tINS | FF | 2 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n114_s8/F |
| 13.636 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n114_s10/I3 |
| 14.262 | 0.626 | tINS | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n114_s10/F |
| 15.222 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n114_s2/I0 |
| 16.254 | 1.032 | tINS | FF | 2 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n114_s2/F |
| 17.214 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n114_s3/I3 |
| 17.840 | 0.626 | tINS | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n114_s3/F |
| 18.800 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n114_s0/I3 |
| 19.426 | 0.626 | tINS | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n114_s0/F |
| 20.386 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 13.468 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | |||
| 14.195 | 0.727 | tCL | RR | 176 | u_clkdiv/CLKOUT |
| 14.921 | 0.726 | tNET | RR | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor_s0/CLK |
| 14.521 | -0.400 | tSu | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/sel_xnor_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 13.468 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 6.833, 36.090%; route: 8.640, 45.635%; tC2Q: 3.460, 18.275% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 5
Path Summary:| Slack | -5.601 |
| Data Arrival Time | 20.122 |
| Data Required Time | 14.521 |
| From | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0 |
| To | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0 |
| Launch Clk | u_clkdiv/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_clkdiv/CLKOUT.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | |||
| 0.727 | 0.727 | tCL | RR | 176 | u_clkdiv/CLKOUT |
| 1.453 | 0.726 | tNET | RR | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0/CLK |
| 1.911 | 0.458 | tC2Q | RF | 5 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/din_d_3_s0/Q |
| 2.871 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n658_s3/I1 |
| 3.970 | 1.099 | tINS | FF | 2 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n658_s3/F |
| 4.930 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n658_s4/I3 |
| 5.556 | 0.626 | tINS | FF | 5 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n658_s4/F |
| 6.516 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s15/I0 |
| 7.548 | 1.032 | tINS | FF | 4 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_1_s15/F |
| 8.508 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n605_s2/I0 |
| 9.540 | 1.032 | tINS | FF | 5 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n605_s2/F |
| 10.500 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_3_s11/I1 |
| 11.599 | 1.099 | tINS | FF | 5 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_3_s11/F |
| 12.559 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15/I2 |
| 13.381 | 0.822 | tINS | FF | 4 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_one_9bit_2_s15/F |
| 14.341 | 0.960 | tNET | FF | 2 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n365_s3/I1 |
| 15.044 | 0.703 | tINS | FF | 2 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n365_s3/SUM |
| 16.004 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n579_s3/I1 |
| 17.103 | 1.099 | tINS | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n579_s3/F |
| 18.063 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n579_s1/I1 |
| 19.162 | 1.099 | tINS | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/n579_s1/F |
| 20.122 | 0.960 | tNET | FF | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 13.468 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | |||
| 14.195 | 0.727 | tCL | RR | 176 | u_clkdiv/CLKOUT |
| 14.921 | 0.726 | tNET | RR | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0/CLK |
| 14.521 | -0.400 | tSu | 1 | DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/cnt_3_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 13.468 |
| Logic Level: | 10 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 8.611, 46.124%; route: 9.600, 51.421%; tC2Q: 0.458, 2.455% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |