Timing Messages

Report Title	Timing Analysis Report
Design File	/home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/UART_transmit_receive_multiple_byte/impl/gwsynthesis/uart_loopback.vg
Physical Constraints File	/home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/UART_transmit_receive_multiple_byte/src/uart_loopback.cst
Timing Constraint File	---
Tool Version	V1.9.11
Part Number	GW1NSR-LV4CQN48PC6/I5
Device	GW1NSR-4C
Created Time	Tue Apr 22 18:37:40 2025
Legal Announcement	Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 1.14V 85C C6/I5
Hold Delay Model	Fast 1.26V 0C C6/I5
Numbers of Paths Analyzed	769
Numbers of Endpoints Analyzed	718
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	Clk	Base	20.000	50.000	0.000	10.000			Clk_ibuf/I

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	Clk	50.000(MHz)	120.967(MHz)	4	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
Clk	Setup	0.000	0
Clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	11.733	uart_data_tx/uart_byte_tx/bps_cnt_2_s1/Q	uart_data_tx/uart_byte_tx/uart_tx_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	7.867
2	11.794	uart_data_rx/uart_byte_rx/div_cnt_11_s0/Q	uart_data_rx/uart_byte_rx/div_cnt_2_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	7.806
3	11.794	uart_data_rx/uart_byte_rx/div_cnt_11_s0/Q	uart_data_rx/uart_byte_rx/div_cnt_11_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	7.806
4	12.044	uart_data_rx/uart_byte_rx/div_cnt_11_s0/Q	uart_data_rx/uart_byte_rx/div_cnt_9_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	7.556
5	12.055	uart_data_rx/uart_byte_rx/bps_cnt_5_s1/Q	uart_data_rx/uart_byte_rx/bps_cnt_2_s1/CE	Clk:[R]	Clk:[R]	20.000	0.000	7.902
6	12.055	uart_data_rx/uart_byte_rx/bps_cnt_5_s1/Q	uart_data_rx/uart_byte_rx/bps_cnt_1_s1/CE	Clk:[R]	Clk:[R]	20.000	0.000	7.902
7	12.068	uart_data_rx/uart_byte_rx/div_cnt_11_s0/Q	uart_data_rx/uart_byte_rx/div_cnt_7_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	7.532
8	12.068	uart_data_rx/uart_byte_rx/div_cnt_11_s0/Q	uart_data_rx/uart_byte_rx/div_cnt_3_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	7.532
9	12.068	uart_data_rx/uart_byte_rx/div_cnt_11_s0/Q	uart_data_rx/uart_byte_rx/div_cnt_1_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	7.532
10	12.242	uart_data_rx/uart_byte_rx/div_cnt_11_s0/Q	uart_data_rx/uart_byte_rx/div_cnt_5_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	7.358
11	12.242	uart_data_rx/uart_byte_rx/div_cnt_11_s0/Q	uart_data_rx/uart_byte_rx/div_cnt_6_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	7.358
12	12.242	uart_data_rx/uart_byte_rx/div_cnt_11_s0/Q	uart_data_rx/uart_byte_rx/div_cnt_8_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	7.358
13	12.242	uart_data_rx/uart_byte_rx/div_cnt_11_s0/Q	uart_data_rx/uart_byte_rx/div_cnt_12_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	7.358
14	12.250	uart_data_rx/uart_byte_rx/div_cnt_11_s0/Q	uart_data_rx/uart_byte_rx/div_cnt_10_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	7.350
15	12.250	uart_data_rx/uart_byte_rx/div_cnt_11_s0/Q	uart_data_rx/uart_byte_rx/div_cnt_4_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	7.350
16	12.425	uart_data_rx/uart_byte_rx/bps_cnt_5_s1/Q	uart_data_rx/uart_byte_rx/bps_cnt_6_s1/CE	Clk:[R]	Clk:[R]	20.000	0.000	7.531
17	12.453	uart_data_tx/uart_byte_tx/div_cnt_10_s0/Q	uart_data_tx/uart_byte_tx/div_cnt_7_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	7.147
18	12.501	uart_data_rx/uart_byte_rx/bps_cnt_5_s1/Q	uart_data_rx/uart_byte_rx/data_byte_pre[2]_1_s0/CE	Clk:[R]	Clk:[R]	20.000	0.000	7.455
19	12.501	uart_data_rx/uart_byte_rx/bps_cnt_5_s1/Q	uart_data_rx/uart_byte_rx/data_byte_pre[2]_2_s0/CE	Clk:[R]	Clk:[R]	20.000	0.000	7.455
20	12.520	uart_data_tx/uart_byte_tx/div_cnt_10_s0/Q	uart_data_tx/uart_byte_tx/div_cnt_5_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	7.080
21	12.523	uart_data_rx/uart_byte_rx/bps_cnt_5_s1/Q	uart_data_rx/uart_byte_rx/bps_cnt_0_s1/D	Clk:[R]	Clk:[R]	20.000	0.000	7.077
22	12.566	uart_data_rx/uart_byte_rx/div_cnt_11_s0/Q	uart_data_rx/uart_byte_rx/div_cnt_13_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	7.034
23	12.599	uart_data_rx/uart_byte_rx/bps_cnt_5_s1/Q	uart_data_rx/uart_byte_rx/data_byte_pre[3]_0_s0/CE	Clk:[R]	Clk:[R]	20.000	0.000	7.357
24	12.627	uart_data_rx/uart_byte_rx/bps_cnt_5_s1/Q	uart_data_rx/uart_byte_rx/data_byte_pre[7]_0_s0/CE	Clk:[R]	Clk:[R]	20.000	0.000	7.330
25	12.753	uart_data_tx/uart_byte_tx/div_cnt_10_s0/Q	uart_data_tx/uart_byte_tx/div_cnt_3_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	6.847

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.562	uart_data_rx/to_state_s4/Q	uart_data_rx/timeout_cnt_11_s0/CE	Clk:[R]	Clk:[R]	0.000	0.000	0.574
2	0.562	uart_data_rx/to_state_s4/Q	uart_data_rx/timeout_cnt_14_s0/CE	Clk:[R]	Clk:[R]	0.000	0.000	0.574
3	0.708	uart_data_tx/uart_byte_tx/div_cnt_1_s0/Q	uart_data_tx/uart_byte_tx/div_cnt_1_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.708
4	0.708	uart_data_tx/data_byte_0_s2/Q	uart_data_tx/data_byte_0_s2/D	Clk:[R]	Clk:[R]	0.000	0.000	0.708
5	0.708	uart_data_tx/data_byte_2_s2/Q	uart_data_tx/data_byte_2_s2/D	Clk:[R]	Clk:[R]	0.000	0.000	0.708
6	0.708	uart_data_tx/data_byte_4_s2/Q	uart_data_tx/data_byte_4_s2/D	Clk:[R]	Clk:[R]	0.000	0.000	0.708
7	0.708	uart_data_tx/data_byte_5_s2/Q	uart_data_tx/data_byte_5_s2/D	Clk:[R]	Clk:[R]	0.000	0.000	0.708
8	0.708	uart_data_rx/uart_byte_rx/STOP_BIT_1_s0/Q	uart_data_rx/uart_byte_rx/STOP_BIT_1_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.708
9	0.708	uart_data_rx/uart_byte_rx/STOP_BIT_2_s0/Q	uart_data_rx/uart_byte_rx/STOP_BIT_2_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.708
10	0.708	uart_data_rx/uart_byte_rx/data_byte_pre[0]_2_s0/Q	uart_data_rx/uart_byte_rx/data_byte_pre[0]_2_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.708
11	0.708	uart_data_rx/uart_byte_rx/data_byte_pre[1]_1_s0/Q	uart_data_rx/uart_byte_rx/data_byte_pre[1]_1_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.708
12	0.708	uart_data_rx/uart_byte_rx/data_byte_pre[1]_2_s0/Q	uart_data_rx/uart_byte_rx/data_byte_pre[1]_2_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.708
13	0.708	uart_data_rx/uart_byte_rx/data_byte_pre[2]_0_s0/Q	uart_data_rx/uart_byte_rx/data_byte_pre[2]_0_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.708
14	0.708	uart_data_rx/uart_byte_rx/data_byte_pre[2]_2_s0/Q	uart_data_rx/uart_byte_rx/data_byte_pre[2]_2_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.708
15	0.708	uart_data_rx/uart_byte_rx/data_byte_pre[3]_2_s0/Q	uart_data_rx/uart_byte_rx/data_byte_pre[3]_2_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.708
16	0.708	uart_data_rx/uart_byte_rx/data_byte_pre[4]_0_s0/Q	uart_data_rx/uart_byte_rx/data_byte_pre[4]_0_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.708
17	0.708	uart_data_rx/uart_byte_rx/data_byte_pre[4]_1_s0/Q	uart_data_rx/uart_byte_rx/data_byte_pre[4]_1_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.708
18	0.708	uart_data_rx/uart_byte_rx/data_byte_pre[6]_0_s0/Q	uart_data_rx/uart_byte_rx/data_byte_pre[6]_0_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.708
19	0.708	uart_data_rx/uart_byte_rx/data_byte_pre[7]_0_s0/Q	uart_data_rx/uart_byte_rx/data_byte_pre[7]_0_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.708
20	0.708	uart_data_rx/uart_byte_rx/data_byte_pre[7]_2_s0/Q	uart_data_rx/uart_byte_rx/data_byte_pre[7]_2_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.708
21	0.708	uart_data_rx/uart_byte_rx/div_cnt_3_s0/Q	uart_data_rx/uart_byte_rx/div_cnt_3_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.708
22	0.708	uart_data_rx/uart_byte_rx/div_cnt_6_s0/Q	uart_data_rx/uart_byte_rx/div_cnt_6_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.708
23	0.708	uart_data_rx/uart_byte_rx/div_cnt_12_s0/Q	uart_data_rx/uart_byte_rx/div_cnt_12_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.708
24	0.708	uart_data_rx/uart_byte_rx/div_cnt_15_s0/Q	uart_data_rx/uart_byte_rx/div_cnt_15_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.708
25	0.708	uart_data_rx/cnt_7_s1/Q	uart_data_rx/cnt_7_s1/D	Clk:[R]	Clk:[R]	0.000	0.000	0.708

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	6.521	7.771	1.250	High Pulse Width	Clk	uart_data_rx/timeout_cnt_17_s0
2	6.521	7.771	1.250	High Pulse Width	Clk	uart_data_rx/timeout_cnt_16_s0
3	6.521	7.771	1.250	High Pulse Width	Clk	uart_data_rx/timeout_cnt_14_s0
4	6.521	7.771	1.250	High Pulse Width	Clk	uart_data_rx/timeout_cnt_10_s0
5	6.521	7.771	1.250	High Pulse Width	Clk	uart_data_rx/timeout_cnt_2_s0
6	6.521	7.771	1.250	High Pulse Width	Clk	uart_data_rx/data_r_26_s0
7	6.521	7.771	1.250	High Pulse Width	Clk	uart_data_rx/data_34_s0
8	6.521	7.771	1.250	High Pulse Width	Clk	uart_data_rx/uart_byte_rx/div_cnt_0_s0
9	6.521	7.771	1.250	High Pulse Width	Clk	uart_data_tx/uart_byte_tx/div_cnt_4_s0
10	6.521	7.771	1.250	High Pulse Width	Clk	uart_data_tx/uart_byte_tx/div_cnt_5_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	11.733
Data Arrival Time	13.458
Data Required Time	25.191
From	uart_data_tx/uart_byte_tx/bps_cnt_2_s1
To	uart_data_tx/uart_byte_tx/uart_tx_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
5.591	1.361	tNET	RR	1	R15C11[0][B]	uart_data_tx/uart_byte_tx/bps_cnt_2_s1/CLK
6.049	0.458	tC2Q	RR	6	R15C11[0][B]	uart_data_tx/uart_byte_tx/bps_cnt_2_s1/Q
6.475	0.426	tNET	RR	1	R15C10[0][A]	uart_data_tx/uart_byte_tx/n177_s30/I0
7.574	1.099	tINS	RF	1	R15C10[0][A]	uart_data_tx/uart_byte_tx/n177_s30/F
9.358	1.784	tNET	FF	1	R15C10[3][A]	uart_data_tx/uart_byte_tx/n177_s26/S0
9.830	0.472	tINS	FR	1	R15C10[3][A]	uart_data_tx/uart_byte_tx/n177_s26/O
10.256	0.426	tNET	RR	1	R15C11[1][B]	uart_data_tx/uart_byte_tx/n177_s28/I2
11.355	1.099	tINS	RF	1	R15C11[1][B]	uart_data_tx/uart_byte_tx/n177_s28/F
13.458	2.103	tNET	FF	1	IOT13[B]	uart_data_tx/uart_byte_tx/uart_tx_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
25.591	1.361	tNET	RR	1	IOT13[B]	uart_data_tx/uart_byte_tx/uart_tx_s0/CLK
25.191	-0.400	tSu		1	IOT13[B]	uart_data_tx/uart_byte_tx/uart_tx_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 2.670, 33.941%; route: 4.738, 60.233%; tC2Q: 0.458, 5.826%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path2

Path Summary:

Slack	11.794
Data Arrival Time	13.397
Data Required Time	25.191
From	uart_data_rx/uart_byte_rx/div_cnt_11_s0
To	uart_data_rx/uart_byte_rx/div_cnt_2_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
5.591	1.361	tNET	RR	1	R7C5[1][B]	uart_data_rx/uart_byte_rx/div_cnt_11_s0/CLK
6.049	0.458	tC2Q	RF	5	R7C5[1][B]	uart_data_rx/uart_byte_rx/div_cnt_11_s0/Q
6.865	0.815	tNET	FF	1	R6C6[1][A]	uart_data_rx/uart_byte_rx/n124_s5/I3
7.926	1.061	tINS	FR	1	R6C6[1][A]	uart_data_rx/uart_byte_rx/n124_s5/F
8.345	0.419	tNET	RR	1	R6C7[0][B]	uart_data_rx/uart_byte_rx/n124_s2/I3
9.377	1.032	tINS	RF	3	R6C7[0][B]	uart_data_rx/uart_byte_rx/n124_s2/F
10.676	1.300	tNET	FF	1	R7C7[1][B]	uart_data_rx/uart_byte_rx/n104_s4/I1
11.498	0.822	tINS	FF	13	R7C7[1][B]	uart_data_rx/uart_byte_rx/n104_s4/F
12.365	0.866	tNET	FF	1	R7C5[0][B]	uart_data_rx/uart_byte_rx/n102_s4/I3
13.397	1.032	tINS	FF	1	R7C5[0][B]	uart_data_rx/uart_byte_rx/n102_s4/F
13.397	0.000	tNET	FF	1	R7C5[0][B]	uart_data_rx/uart_byte_rx/div_cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
25.591	1.361	tNET	RR	1	R7C5[0][B]	uart_data_rx/uart_byte_rx/div_cnt_2_s0/CLK
25.191	-0.400	tSu		1	R7C5[0][B]	uart_data_rx/uart_byte_rx/div_cnt_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.947, 50.566%; route: 3.400, 43.562%; tC2Q: 0.458, 5.872%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path3

Path Summary:

Slack	11.794
Data Arrival Time	13.397
Data Required Time	25.191
From	uart_data_rx/uart_byte_rx/div_cnt_11_s0
To	uart_data_rx/uart_byte_rx/div_cnt_11_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
5.591	1.361	tNET	RR	1	R7C5[1][B]	uart_data_rx/uart_byte_rx/div_cnt_11_s0/CLK
6.049	0.458	tC2Q	RF	5	R7C5[1][B]	uart_data_rx/uart_byte_rx/div_cnt_11_s0/Q
6.865	0.815	tNET	FF	1	R6C6[1][A]	uart_data_rx/uart_byte_rx/n124_s5/I3
7.926	1.061	tINS	FR	1	R6C6[1][A]	uart_data_rx/uart_byte_rx/n124_s5/F
8.345	0.419	tNET	RR	1	R6C7[0][B]	uart_data_rx/uart_byte_rx/n124_s2/I3
9.377	1.032	tINS	RF	3	R6C7[0][B]	uart_data_rx/uart_byte_rx/n124_s2/F
10.676	1.300	tNET	FF	1	R7C7[1][B]	uart_data_rx/uart_byte_rx/n104_s4/I1
11.498	0.822	tINS	FF	13	R7C7[1][B]	uart_data_rx/uart_byte_rx/n104_s4/F
12.365	0.866	tNET	FF	1	R7C5[1][B]	uart_data_rx/uart_byte_rx/n93_s2/I3
13.397	1.032	tINS	FF	1	R7C5[1][B]	uart_data_rx/uart_byte_rx/n93_s2/F
13.397	0.000	tNET	FF	1	R7C5[1][B]	uart_data_rx/uart_byte_rx/div_cnt_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
25.591	1.361	tNET	RR	1	R7C5[1][B]	uart_data_rx/uart_byte_rx/div_cnt_11_s0/CLK
25.191	-0.400	tSu		1	R7C5[1][B]	uart_data_rx/uart_byte_rx/div_cnt_11_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.947, 50.566%; route: 3.400, 43.562%; tC2Q: 0.458, 5.872%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path4

Path Summary:

Slack	12.044
Data Arrival Time	13.147
Data Required Time	25.191
From	uart_data_rx/uart_byte_rx/div_cnt_11_s0
To	uart_data_rx/uart_byte_rx/div_cnt_9_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
5.591	1.361	tNET	RR	1	R7C5[1][B]	uart_data_rx/uart_byte_rx/div_cnt_11_s0/CLK
6.049	0.458	tC2Q	RF	5	R7C5[1][B]	uart_data_rx/uart_byte_rx/div_cnt_11_s0/Q
6.865	0.815	tNET	FF	1	R6C6[1][A]	uart_data_rx/uart_byte_rx/n124_s5/I3
7.926	1.061	tINS	FR	1	R6C6[1][A]	uart_data_rx/uart_byte_rx/n124_s5/F
8.345	0.419	tNET	RR	1	R6C7[0][B]	uart_data_rx/uart_byte_rx/n124_s2/I3
9.377	1.032	tINS	RF	3	R6C7[0][B]	uart_data_rx/uart_byte_rx/n124_s2/F
10.676	1.300	tNET	FF	1	R7C7[1][B]	uart_data_rx/uart_byte_rx/n104_s4/I1
11.498	0.822	tINS	FF	13	R7C7[1][B]	uart_data_rx/uart_byte_rx/n104_s4/F
12.325	0.826	tNET	FF	1	R6C5[0][B]	uart_data_rx/uart_byte_rx/n95_s2/I3
13.147	0.822	tINS	FF	1	R6C5[0][B]	uart_data_rx/uart_byte_rx/n95_s2/F
13.147	0.000	tNET	FF	1	R6C5[0][B]	uart_data_rx/uart_byte_rx/div_cnt_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
25.591	1.361	tNET	RR	1	R6C5[0][B]	uart_data_rx/uart_byte_rx/div_cnt_9_s0/CLK
25.191	-0.400	tSu		1	R6C5[0][B]	uart_data_rx/uart_byte_rx/div_cnt_9_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.737, 49.460%; route: 3.360, 44.474%; tC2Q: 0.458, 6.066%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path5

Path Summary:

Slack	12.055
Data Arrival Time	13.493
Data Required Time	25.548
From	uart_data_rx/uart_byte_rx/bps_cnt_5_s1
To	uart_data_rx/uart_byte_rx/bps_cnt_2_s1
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
5.591	1.361	tNET	RR	1	R7C9[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_5_s1/CLK
6.049	0.458	tC2Q	RF	15	R7C9[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_5_s1/Q
6.880	0.831	tNET	FF	1	R8C8[3][A]	uart_data_rx/uart_byte_rx/START_BIT_2_s5/I0
7.979	1.099	tINS	FF	1	R8C8[3][A]	uart_data_rx/uart_byte_rx/START_BIT_2_s5/F
7.985	0.005	tNET	FF	1	R8C8[2][B]	uart_data_rx/uart_byte_rx/bps_cnt_7_s6/I3
8.807	0.822	tINS	FF	2	R8C8[2][B]	uart_data_rx/uart_byte_rx/bps_cnt_7_s6/F
9.632	0.825	tNET	FF	1	R8C10[2][B]	uart_data_rx/uart_byte_rx/bps_cnt_7_s4/I2
10.258	0.626	tINS	FF	5	R8C10[2][B]	uart_data_rx/uart_byte_rx/bps_cnt_7_s4/F
11.415	1.157	tNET	FF	1	R7C8[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s3/I3
12.040	0.625	tINS	FR	8	R7C8[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s3/F
13.493	1.452	tNET	RR	1	R6C10[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_2_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
25.591	1.361	tNET	RR	1	R6C10[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_2_s1/CLK
25.548	-0.043	tSu		1	R6C10[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_2_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.172, 40.144%; route: 4.271, 54.055%; tC2Q: 0.458, 5.801%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path6

Path Summary:

Slack	12.055
Data Arrival Time	13.493
Data Required Time	25.548
From	uart_data_rx/uart_byte_rx/bps_cnt_5_s1
To	uart_data_rx/uart_byte_rx/bps_cnt_1_s1
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
5.591	1.361	tNET	RR	1	R7C9[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_5_s1/CLK
6.049	0.458	tC2Q	RF	15	R7C9[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_5_s1/Q
6.880	0.831	tNET	FF	1	R8C8[3][A]	uart_data_rx/uart_byte_rx/START_BIT_2_s5/I0
7.979	1.099	tINS	FF	1	R8C8[3][A]	uart_data_rx/uart_byte_rx/START_BIT_2_s5/F
7.985	0.005	tNET	FF	1	R8C8[2][B]	uart_data_rx/uart_byte_rx/bps_cnt_7_s6/I3
8.807	0.822	tINS	FF	2	R8C8[2][B]	uart_data_rx/uart_byte_rx/bps_cnt_7_s6/F
9.632	0.825	tNET	FF	1	R8C10[2][B]	uart_data_rx/uart_byte_rx/bps_cnt_7_s4/I2
10.258	0.626	tINS	FF	5	R8C10[2][B]	uart_data_rx/uart_byte_rx/bps_cnt_7_s4/F
11.415	1.157	tNET	FF	1	R7C8[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s3/I3
12.040	0.625	tINS	FR	8	R7C8[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s3/F
13.493	1.452	tNET	RR	1	R6C10[0][A]	uart_data_rx/uart_byte_rx/bps_cnt_1_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
25.591	1.361	tNET	RR	1	R6C10[0][A]	uart_data_rx/uart_byte_rx/bps_cnt_1_s1/CLK
25.548	-0.043	tSu		1	R6C10[0][A]	uart_data_rx/uart_byte_rx/bps_cnt_1_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.172, 40.144%; route: 4.271, 54.055%; tC2Q: 0.458, 5.801%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path7

Path Summary:

Slack	12.068
Data Arrival Time	13.123
Data Required Time	25.191
From	uart_data_rx/uart_byte_rx/div_cnt_11_s0
To	uart_data_rx/uart_byte_rx/div_cnt_7_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
5.591	1.361	tNET	RR	1	R7C5[1][B]	uart_data_rx/uart_byte_rx/div_cnt_11_s0/CLK
6.049	0.458	tC2Q	RF	5	R7C5[1][B]	uart_data_rx/uart_byte_rx/div_cnt_11_s0/Q
6.865	0.815	tNET	FF	1	R6C6[1][A]	uart_data_rx/uart_byte_rx/n124_s5/I3
7.926	1.061	tINS	FR	1	R6C6[1][A]	uart_data_rx/uart_byte_rx/n124_s5/F
8.345	0.419	tNET	RR	1	R6C7[0][B]	uart_data_rx/uart_byte_rx/n124_s2/I3
9.377	1.032	tINS	RF	3	R6C7[0][B]	uart_data_rx/uart_byte_rx/n124_s2/F
10.676	1.300	tNET	FF	1	R7C7[1][B]	uart_data_rx/uart_byte_rx/n104_s4/I1
11.498	0.822	tINS	FF	13	R7C7[1][B]	uart_data_rx/uart_byte_rx/n104_s4/F
12.024	0.526	tNET	FF	1	R7C5[2][B]	uart_data_rx/uart_byte_rx/n97_s2/I2
13.123	1.099	tINS	FF	1	R7C5[2][B]	uart_data_rx/uart_byte_rx/n97_s2/F
13.123	0.000	tNET	FF	1	R7C5[2][B]	uart_data_rx/uart_byte_rx/div_cnt_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
25.591	1.361	tNET	RR	1	R7C5[2][B]	uart_data_rx/uart_byte_rx/div_cnt_7_s0/CLK
25.191	-0.400	tSu		1	R7C5[2][B]	uart_data_rx/uart_byte_rx/div_cnt_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 4.014, 53.293%; route: 3.060, 40.622%; tC2Q: 0.458, 6.085%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path8

Path Summary:

Slack	12.068
Data Arrival Time	13.123
Data Required Time	25.191
From	uart_data_rx/uart_byte_rx/div_cnt_11_s0
To	uart_data_rx/uart_byte_rx/div_cnt_3_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
5.591	1.361	tNET	RR	1	R7C5[1][B]	uart_data_rx/uart_byte_rx/div_cnt_11_s0/CLK
6.049	0.458	tC2Q	RF	5	R7C5[1][B]	uart_data_rx/uart_byte_rx/div_cnt_11_s0/Q
6.865	0.815	tNET	FF	1	R6C6[1][A]	uart_data_rx/uart_byte_rx/n124_s5/I3
7.926	1.061	tINS	FR	1	R6C6[1][A]	uart_data_rx/uart_byte_rx/n124_s5/F
8.345	0.419	tNET	RR	1	R6C7[0][B]	uart_data_rx/uart_byte_rx/n124_s2/I3
9.377	1.032	tINS	RF	3	R6C7[0][B]	uart_data_rx/uart_byte_rx/n124_s2/F
10.676	1.300	tNET	FF	1	R7C7[1][B]	uart_data_rx/uart_byte_rx/n104_s4/I1
11.498	0.822	tINS	FF	13	R7C7[1][B]	uart_data_rx/uart_byte_rx/n104_s4/F
12.024	0.526	tNET	FF	1	R7C5[0][A]	uart_data_rx/uart_byte_rx/n101_s2/I3
13.123	1.099	tINS	FF	1	R7C5[0][A]	uart_data_rx/uart_byte_rx/n101_s2/F
13.123	0.000	tNET	FF	1	R7C5[0][A]	uart_data_rx/uart_byte_rx/div_cnt_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
25.591	1.361	tNET	RR	1	R7C5[0][A]	uart_data_rx/uart_byte_rx/div_cnt_3_s0/CLK
25.191	-0.400	tSu		1	R7C5[0][A]	uart_data_rx/uart_byte_rx/div_cnt_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 4.014, 53.293%; route: 3.060, 40.622%; tC2Q: 0.458, 6.085%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path9

Path Summary:

Slack	12.068
Data Arrival Time	13.123
Data Required Time	25.191
From	uart_data_rx/uart_byte_rx/div_cnt_11_s0
To	uart_data_rx/uart_byte_rx/div_cnt_1_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
5.591	1.361	tNET	RR	1	R7C5[1][B]	uart_data_rx/uart_byte_rx/div_cnt_11_s0/CLK
6.049	0.458	tC2Q	RF	5	R7C5[1][B]	uart_data_rx/uart_byte_rx/div_cnt_11_s0/Q
6.865	0.815	tNET	FF	1	R6C6[1][A]	uart_data_rx/uart_byte_rx/n124_s5/I3
7.926	1.061	tINS	FR	1	R6C6[1][A]	uart_data_rx/uart_byte_rx/n124_s5/F
8.345	0.419	tNET	RR	1	R6C7[0][B]	uart_data_rx/uart_byte_rx/n124_s2/I3
9.377	1.032	tINS	RF	3	R6C7[0][B]	uart_data_rx/uart_byte_rx/n124_s2/F
10.676	1.300	tNET	FF	1	R7C7[1][B]	uart_data_rx/uart_byte_rx/n104_s4/I1
11.498	0.822	tINS	FF	13	R7C7[1][B]	uart_data_rx/uart_byte_rx/n104_s4/F
12.024	0.526	tNET	FF	1	R7C5[1][A]	uart_data_rx/uart_byte_rx/n103_s2/I2
13.123	1.099	tINS	FF	1	R7C5[1][A]	uart_data_rx/uart_byte_rx/n103_s2/F
13.123	0.000	tNET	FF	1	R7C5[1][A]	uart_data_rx/uart_byte_rx/div_cnt_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
25.591	1.361	tNET	RR	1	R7C5[1][A]	uart_data_rx/uart_byte_rx/div_cnt_1_s0/CLK
25.191	-0.400	tSu		1	R7C5[1][A]	uart_data_rx/uart_byte_rx/div_cnt_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 4.014, 53.293%; route: 3.060, 40.622%; tC2Q: 0.458, 6.085%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path10

Path Summary:

Slack	12.242
Data Arrival Time	12.949
Data Required Time	25.191
From	uart_data_rx/uart_byte_rx/div_cnt_11_s0
To	uart_data_rx/uart_byte_rx/div_cnt_5_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
5.591	1.361	tNET	RR	1	R7C5[1][B]	uart_data_rx/uart_byte_rx/div_cnt_11_s0/CLK
6.049	0.458	tC2Q	RF	5	R7C5[1][B]	uart_data_rx/uart_byte_rx/div_cnt_11_s0/Q
6.865	0.815	tNET	FF	1	R6C6[1][A]	uart_data_rx/uart_byte_rx/n124_s5/I3
7.926	1.061	tINS	FR	1	R6C6[1][A]	uart_data_rx/uart_byte_rx/n124_s5/F
8.345	0.419	tNET	RR	1	R6C7[0][B]	uart_data_rx/uart_byte_rx/n124_s2/I3
9.377	1.032	tINS	RF	3	R6C7[0][B]	uart_data_rx/uart_byte_rx/n124_s2/F
10.676	1.300	tNET	FF	1	R7C7[1][B]	uart_data_rx/uart_byte_rx/n104_s4/I1
11.478	0.802	tINS	FR	13	R7C7[1][B]	uart_data_rx/uart_byte_rx/n104_s4/F
11.917	0.439	tNET	RR	1	R7C6[0][B]	uart_data_rx/uart_byte_rx/n99_s2/I3
12.949	1.032	tINS	RF	1	R7C6[0][B]	uart_data_rx/uart_byte_rx/n99_s2/F
12.949	0.000	tNET	FF	1	R7C6[0][B]	uart_data_rx/uart_byte_rx/div_cnt_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
25.591	1.361	tNET	RR	1	R7C6[0][B]	uart_data_rx/uart_byte_rx/div_cnt_5_s0/CLK
25.191	-0.400	tSu		1	R7C6[0][B]	uart_data_rx/uart_byte_rx/div_cnt_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.927, 53.371%; route: 2.973, 40.399%; tC2Q: 0.458, 6.229%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path11

Path Summary:

Slack	12.242
Data Arrival Time	12.949
Data Required Time	25.191
From	uart_data_rx/uart_byte_rx/div_cnt_11_s0
To	uart_data_rx/uart_byte_rx/div_cnt_6_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
5.591	1.361	tNET	RR	1	R7C5[1][B]	uart_data_rx/uart_byte_rx/div_cnt_11_s0/CLK
6.049	0.458	tC2Q	RF	5	R7C5[1][B]	uart_data_rx/uart_byte_rx/div_cnt_11_s0/Q
6.865	0.815	tNET	FF	1	R6C6[1][A]	uart_data_rx/uart_byte_rx/n124_s5/I3
7.926	1.061	tINS	FR	1	R6C6[1][A]	uart_data_rx/uart_byte_rx/n124_s5/F
8.345	0.419	tNET	RR	1	R6C7[0][B]	uart_data_rx/uart_byte_rx/n124_s2/I3
9.377	1.032	tINS	RF	3	R6C7[0][B]	uart_data_rx/uart_byte_rx/n124_s2/F
10.676	1.300	tNET	FF	1	R7C7[1][B]	uart_data_rx/uart_byte_rx/n104_s4/I1
11.478	0.802	tINS	FR	13	R7C7[1][B]	uart_data_rx/uart_byte_rx/n104_s4/F
11.917	0.439	tNET	RR	1	R7C6[1][A]	uart_data_rx/uart_byte_rx/n98_s2/I2
12.949	1.032	tINS	RF	1	R7C6[1][A]	uart_data_rx/uart_byte_rx/n98_s2/F
12.949	0.000	tNET	FF	1	R7C6[1][A]	uart_data_rx/uart_byte_rx/div_cnt_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
25.591	1.361	tNET	RR	1	R7C6[1][A]	uart_data_rx/uart_byte_rx/div_cnt_6_s0/CLK
25.191	-0.400	tSu		1	R7C6[1][A]	uart_data_rx/uart_byte_rx/div_cnt_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.927, 53.371%; route: 2.973, 40.399%; tC2Q: 0.458, 6.229%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path12

Path Summary:

Slack	12.242
Data Arrival Time	12.949
Data Required Time	25.191
From	uart_data_rx/uart_byte_rx/div_cnt_11_s0
To	uart_data_rx/uart_byte_rx/div_cnt_8_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
5.591	1.361	tNET	RR	1	R7C5[1][B]	uart_data_rx/uart_byte_rx/div_cnt_11_s0/CLK
6.049	0.458	tC2Q	RF	5	R7C5[1][B]	uart_data_rx/uart_byte_rx/div_cnt_11_s0/Q
6.865	0.815	tNET	FF	1	R6C6[1][A]	uart_data_rx/uart_byte_rx/n124_s5/I3
7.926	1.061	tINS	FR	1	R6C6[1][A]	uart_data_rx/uart_byte_rx/n124_s5/F
8.345	0.419	tNET	RR	1	R6C7[0][B]	uart_data_rx/uart_byte_rx/n124_s2/I3
9.377	1.032	tINS	RF	3	R6C7[0][B]	uart_data_rx/uart_byte_rx/n124_s2/F
10.676	1.300	tNET	FF	1	R7C7[1][B]	uart_data_rx/uart_byte_rx/n104_s4/I1
11.478	0.802	tINS	FR	13	R7C7[1][B]	uart_data_rx/uart_byte_rx/n104_s4/F
11.917	0.439	tNET	RR	1	R7C6[2][A]	uart_data_rx/uart_byte_rx/n96_s2/I3
12.949	1.032	tINS	RF	1	R7C6[2][A]	uart_data_rx/uart_byte_rx/n96_s2/F
12.949	0.000	tNET	FF	1	R7C6[2][A]	uart_data_rx/uart_byte_rx/div_cnt_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
25.591	1.361	tNET	RR	1	R7C6[2][A]	uart_data_rx/uart_byte_rx/div_cnt_8_s0/CLK
25.191	-0.400	tSu		1	R7C6[2][A]	uart_data_rx/uart_byte_rx/div_cnt_8_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.927, 53.371%; route: 2.973, 40.399%; tC2Q: 0.458, 6.229%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path13

Path Summary:

Slack	12.242
Data Arrival Time	12.949
Data Required Time	25.191
From	uart_data_rx/uart_byte_rx/div_cnt_11_s0
To	uart_data_rx/uart_byte_rx/div_cnt_12_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
5.591	1.361	tNET	RR	1	R7C5[1][B]	uart_data_rx/uart_byte_rx/div_cnt_11_s0/CLK
6.049	0.458	tC2Q	RF	5	R7C5[1][B]	uart_data_rx/uart_byte_rx/div_cnt_11_s0/Q
6.865	0.815	tNET	FF	1	R6C6[1][A]	uart_data_rx/uart_byte_rx/n124_s5/I3
7.926	1.061	tINS	FR	1	R6C6[1][A]	uart_data_rx/uart_byte_rx/n124_s5/F
8.345	0.419	tNET	RR	1	R6C7[0][B]	uart_data_rx/uart_byte_rx/n124_s2/I3
9.377	1.032	tINS	RF	3	R6C7[0][B]	uart_data_rx/uart_byte_rx/n124_s2/F
10.676	1.300	tNET	FF	1	R7C7[1][B]	uart_data_rx/uart_byte_rx/n104_s4/I1
11.478	0.802	tINS	FR	13	R7C7[1][B]	uart_data_rx/uart_byte_rx/n104_s4/F
11.917	0.439	tNET	RR	1	R7C6[0][A]	uart_data_rx/uart_byte_rx/n92_s2/I3
12.949	1.032	tINS	RF	1	R7C6[0][A]	uart_data_rx/uart_byte_rx/n92_s2/F
12.949	0.000	tNET	FF	1	R7C6[0][A]	uart_data_rx/uart_byte_rx/div_cnt_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
25.591	1.361	tNET	RR	1	R7C6[0][A]	uart_data_rx/uart_byte_rx/div_cnt_12_s0/CLK
25.191	-0.400	tSu		1	R7C6[0][A]	uart_data_rx/uart_byte_rx/div_cnt_12_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.927, 53.371%; route: 2.973, 40.399%; tC2Q: 0.458, 6.229%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path14

Path Summary:

Slack	12.250
Data Arrival Time	12.941
Data Required Time	25.191
From	uart_data_rx/uart_byte_rx/div_cnt_11_s0
To	uart_data_rx/uart_byte_rx/div_cnt_10_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
5.591	1.361	tNET	RR	1	R7C5[1][B]	uart_data_rx/uart_byte_rx/div_cnt_11_s0/CLK
6.049	0.458	tC2Q	RF	5	R7C5[1][B]	uart_data_rx/uart_byte_rx/div_cnt_11_s0/Q
6.865	0.815	tNET	FF	1	R6C6[1][A]	uart_data_rx/uart_byte_rx/n124_s5/I3
7.926	1.061	tINS	FR	1	R6C6[1][A]	uart_data_rx/uart_byte_rx/n124_s5/F
8.345	0.419	tNET	RR	1	R6C7[0][B]	uart_data_rx/uart_byte_rx/n124_s2/I3
9.377	1.032	tINS	RF	3	R6C7[0][B]	uart_data_rx/uart_byte_rx/n124_s2/F
10.676	1.300	tNET	FF	1	R7C7[1][B]	uart_data_rx/uart_byte_rx/n104_s4/I1
11.478	0.802	tINS	FR	13	R7C7[1][B]	uart_data_rx/uart_byte_rx/n104_s4/F
11.909	0.431	tNET	RR	1	R6C7[1][A]	uart_data_rx/uart_byte_rx/n94_s2/I3
12.941	1.032	tINS	RF	1	R6C7[1][A]	uart_data_rx/uart_byte_rx/n94_s2/F
12.941	0.000	tNET	FF	1	R6C7[1][A]	uart_data_rx/uart_byte_rx/div_cnt_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
25.591	1.361	tNET	RR	1	R6C7[1][A]	uart_data_rx/uart_byte_rx/div_cnt_10_s0/CLK
25.191	-0.400	tSu		1	R6C7[1][A]	uart_data_rx/uart_byte_rx/div_cnt_10_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.927, 53.429%; route: 2.965, 40.335%; tC2Q: 0.458, 6.236%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path15

Path Summary:

Slack	12.250
Data Arrival Time	12.941
Data Required Time	25.191
From	uart_data_rx/uart_byte_rx/div_cnt_11_s0
To	uart_data_rx/uart_byte_rx/div_cnt_4_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
5.591	1.361	tNET	RR	1	R7C5[1][B]	uart_data_rx/uart_byte_rx/div_cnt_11_s0/CLK
6.049	0.458	tC2Q	RF	5	R7C5[1][B]	uart_data_rx/uart_byte_rx/div_cnt_11_s0/Q
6.865	0.815	tNET	FF	1	R6C6[1][A]	uart_data_rx/uart_byte_rx/n124_s5/I3
7.926	1.061	tINS	FR	1	R6C6[1][A]	uart_data_rx/uart_byte_rx/n124_s5/F
8.345	0.419	tNET	RR	1	R6C7[0][B]	uart_data_rx/uart_byte_rx/n124_s2/I3
9.377	1.032	tINS	RF	3	R6C7[0][B]	uart_data_rx/uart_byte_rx/n124_s2/F
10.676	1.300	tNET	FF	1	R7C7[1][B]	uart_data_rx/uart_byte_rx/n104_s4/I1
11.478	0.802	tINS	FR	13	R7C7[1][B]	uart_data_rx/uart_byte_rx/n104_s4/F
11.909	0.431	tNET	RR	1	R6C7[1][B]	uart_data_rx/uart_byte_rx/n100_s2/I2
12.941	1.032	tINS	RF	1	R6C7[1][B]	uart_data_rx/uart_byte_rx/n100_s2/F
12.941	0.000	tNET	FF	1	R6C7[1][B]	uart_data_rx/uart_byte_rx/div_cnt_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
25.591	1.361	tNET	RR	1	R6C7[1][B]	uart_data_rx/uart_byte_rx/div_cnt_4_s0/CLK
25.191	-0.400	tSu		1	R6C7[1][B]	uart_data_rx/uart_byte_rx/div_cnt_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.927, 53.429%; route: 2.965, 40.335%; tC2Q: 0.458, 6.236%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path16

Path Summary:

Slack	12.425
Data Arrival Time	13.122
Data Required Time	25.548
From	uart_data_rx/uart_byte_rx/bps_cnt_5_s1
To	uart_data_rx/uart_byte_rx/bps_cnt_6_s1
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
5.591	1.361	tNET	RR	1	R7C9[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_5_s1/CLK
6.049	0.458	tC2Q	RF	15	R7C9[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_5_s1/Q
6.880	0.831	tNET	FF	1	R8C8[3][A]	uart_data_rx/uart_byte_rx/START_BIT_2_s5/I0
7.979	1.099	tINS	FF	1	R8C8[3][A]	uart_data_rx/uart_byte_rx/START_BIT_2_s5/F
7.985	0.005	tNET	FF	1	R8C8[2][B]	uart_data_rx/uart_byte_rx/bps_cnt_7_s6/I3
8.807	0.822	tINS	FF	2	R8C8[2][B]	uart_data_rx/uart_byte_rx/bps_cnt_7_s6/F
9.632	0.825	tNET	FF	1	R8C10[2][B]	uart_data_rx/uart_byte_rx/bps_cnt_7_s4/I2
10.258	0.626	tINS	FF	5	R8C10[2][B]	uart_data_rx/uart_byte_rx/bps_cnt_7_s4/F
11.415	1.157	tNET	FF	1	R7C8[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s3/I3
12.040	0.625	tINS	FR	8	R7C8[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s3/F
13.122	1.082	tNET	RR	1	R6C9[0][A]	uart_data_rx/uart_byte_rx/bps_cnt_6_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
25.591	1.361	tNET	RR	1	R6C9[0][A]	uart_data_rx/uart_byte_rx/bps_cnt_6_s1/CLK
25.548	-0.043	tSu		1	R6C9[0][A]	uart_data_rx/uart_byte_rx/bps_cnt_6_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.172, 42.118%; route: 3.901, 51.796%; tC2Q: 0.458, 6.086%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path17

Path Summary:

Slack	12.453
Data Arrival Time	12.738
Data Required Time	25.191
From	uart_data_tx/uart_byte_tx/div_cnt_10_s0
To	uart_data_tx/uart_byte_tx/div_cnt_7_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
5.591	1.361	tNET	RR	1	R14C8[0][A]	uart_data_tx/uart_byte_tx/div_cnt_10_s0/CLK
6.049	0.458	tC2Q	RF	3	R14C8[0][A]	uart_data_tx/uart_byte_tx/div_cnt_10_s0/Q
6.861	0.811	tNET	FF	1	R15C9[2][A]	uart_data_tx/uart_byte_tx/n145_s5/I0
7.887	1.026	tINS	FR	1	R15C9[2][A]	uart_data_tx/uart_byte_tx/n145_s5/F
8.306	0.419	tNET	RR	1	R14C9[3][B]	uart_data_tx/uart_byte_tx/n145_s2/I3
8.932	0.626	tINS	RF	2	R14C9[3][B]	uart_data_tx/uart_byte_tx/n145_s2/F
9.741	0.810	tNET	FF	1	R15C8[2][A]	uart_data_tx/uart_byte_tx/n123_s3/I0
10.773	1.032	tINS	FF	12	R15C8[2][A]	uart_data_tx/uart_byte_tx/n123_s3/F
11.639	0.866	tNET	FF	1	R14C10[2][A]	uart_data_tx/uart_byte_tx/n118_s2/I3
12.738	1.099	tINS	FF	1	R14C10[2][A]	uart_data_tx/uart_byte_tx/n118_s2/F
12.738	0.000	tNET	FF	1	R14C10[2][A]	uart_data_tx/uart_byte_tx/div_cnt_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
25.591	1.361	tNET	RR	1	R14C10[2][A]	uart_data_tx/uart_byte_tx/div_cnt_7_s0/CLK
25.191	-0.400	tSu		1	R14C10[2][A]	uart_data_tx/uart_byte_tx/div_cnt_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.783, 52.932%; route: 2.906, 40.655%; tC2Q: 0.458, 6.413%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path18

Path Summary:

Slack	12.501
Data Arrival Time	13.046
Data Required Time	25.548
From	uart_data_rx/uart_byte_rx/bps_cnt_5_s1
To	uart_data_rx/uart_byte_rx/data_byte_pre[2]_1_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
5.591	1.361	tNET	RR	1	R7C9[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_5_s1/CLK
6.049	0.458	tC2Q	RF	15	R7C9[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_5_s1/Q
6.880	0.831	tNET	FF	1	R8C8[3][A]	uart_data_rx/uart_byte_rx/START_BIT_2_s5/I0
7.979	1.099	tINS	FF	1	R8C8[3][A]	uart_data_rx/uart_byte_rx/START_BIT_2_s5/F
7.985	0.005	tNET	FF	1	R8C8[2][B]	uart_data_rx/uart_byte_rx/bps_cnt_7_s6/I3
8.807	0.822	tINS	FF	2	R8C8[2][B]	uart_data_rx/uart_byte_rx/bps_cnt_7_s6/F
9.301	0.495	tNET	FF	1	R8C10[3][B]	uart_data_rx/uart_byte_rx/START_BIT_2_s3/I2
10.333	1.032	tINS	FF	10	R8C10[3][B]	uart_data_rx/uart_byte_rx/START_BIT_2_s3/F
11.505	1.172	tNET	FF	1	R6C6[0][B]	uart_data_rx/uart_byte_rx/data_byte_pre[2]_2_s2/I1
12.307	0.802	tINS	FR	3	R6C6[0][B]	uart_data_rx/uart_byte_rx/data_byte_pre[2]_2_s2/F
13.046	0.739	tNET	RR	1	R8C5[1][B]	uart_data_rx/uart_byte_rx/data_byte_pre[2]_1_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
25.591	1.361	tNET	RR	1	R8C5[1][B]	uart_data_rx/uart_byte_rx/data_byte_pre[2]_1_s0/CLK
25.548	-0.043	tSu		1	R8C5[1][B]	uart_data_rx/uart_byte_rx/data_byte_pre[2]_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.755, 50.368%; route: 3.242, 43.484%; tC2Q: 0.458, 6.148%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path19

Path Summary:

Slack	12.501
Data Arrival Time	13.046
Data Required Time	25.548
From	uart_data_rx/uart_byte_rx/bps_cnt_5_s1
To	uart_data_rx/uart_byte_rx/data_byte_pre[2]_2_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
5.591	1.361	tNET	RR	1	R7C9[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_5_s1/CLK
6.049	0.458	tC2Q	RF	15	R7C9[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_5_s1/Q
6.880	0.831	tNET	FF	1	R8C8[3][A]	uart_data_rx/uart_byte_rx/START_BIT_2_s5/I0
7.979	1.099	tINS	FF	1	R8C8[3][A]	uart_data_rx/uart_byte_rx/START_BIT_2_s5/F
7.985	0.005	tNET	FF	1	R8C8[2][B]	uart_data_rx/uart_byte_rx/bps_cnt_7_s6/I3
8.807	0.822	tINS	FF	2	R8C8[2][B]	uart_data_rx/uart_byte_rx/bps_cnt_7_s6/F
9.301	0.495	tNET	FF	1	R8C10[3][B]	uart_data_rx/uart_byte_rx/START_BIT_2_s3/I2
10.333	1.032	tINS	FF	10	R8C10[3][B]	uart_data_rx/uart_byte_rx/START_BIT_2_s3/F
11.505	1.172	tNET	FF	1	R6C6[0][B]	uart_data_rx/uart_byte_rx/data_byte_pre[2]_2_s2/I1
12.307	0.802	tINS	FR	3	R6C6[0][B]	uart_data_rx/uart_byte_rx/data_byte_pre[2]_2_s2/F
13.046	0.739	tNET	RR	1	R8C5[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[2]_2_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
25.591	1.361	tNET	RR	1	R8C5[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[2]_2_s0/CLK
25.548	-0.043	tSu		1	R8C5[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[2]_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.755, 50.368%; route: 3.242, 43.484%; tC2Q: 0.458, 6.148%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path20

Path Summary:

Slack	12.520
Data Arrival Time	12.671
Data Required Time	25.191
From	uart_data_tx/uart_byte_tx/div_cnt_10_s0
To	uart_data_tx/uart_byte_tx/div_cnt_5_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
5.591	1.361	tNET	RR	1	R14C8[0][A]	uart_data_tx/uart_byte_tx/div_cnt_10_s0/CLK
6.049	0.458	tC2Q	RF	3	R14C8[0][A]	uart_data_tx/uart_byte_tx/div_cnt_10_s0/Q
6.861	0.811	tNET	FF	1	R15C9[2][A]	uart_data_tx/uart_byte_tx/n145_s5/I0
7.887	1.026	tINS	FR	1	R15C9[2][A]	uart_data_tx/uart_byte_tx/n145_s5/F
8.306	0.419	tNET	RR	1	R14C9[3][B]	uart_data_tx/uart_byte_tx/n145_s2/I3
8.932	0.626	tINS	RF	2	R14C9[3][B]	uart_data_tx/uart_byte_tx/n145_s2/F
9.741	0.810	tNET	FF	1	R15C8[2][A]	uart_data_tx/uart_byte_tx/n123_s3/I0
10.773	1.032	tINS	FF	12	R15C8[2][A]	uart_data_tx/uart_byte_tx/n123_s3/F
11.639	0.866	tNET	FF	1	R14C7[1][A]	uart_data_tx/uart_byte_tx/n120_s2/I2
12.671	1.032	tINS	FF	1	R14C7[1][A]	uart_data_tx/uart_byte_tx/n120_s2/F
12.671	0.000	tNET	FF	1	R14C7[1][A]	uart_data_tx/uart_byte_tx/div_cnt_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
25.591	1.361	tNET	RR	1	R14C7[1][A]	uart_data_tx/uart_byte_tx/div_cnt_5_s0/CLK
25.191	-0.400	tSu		1	R14C7[1][A]	uart_data_tx/uart_byte_tx/div_cnt_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.716, 52.486%; route: 2.906, 41.040%; tC2Q: 0.458, 6.474%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path21

Path Summary:

Slack	12.523
Data Arrival Time	12.668
Data Required Time	25.191
From	uart_data_rx/uart_byte_rx/bps_cnt_5_s1
To	uart_data_rx/uart_byte_rx/bps_cnt_0_s1
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
5.591	1.361	tNET	RR	1	R7C9[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_5_s1/CLK
6.049	0.458	tC2Q	RF	15	R7C9[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_5_s1/Q
6.880	0.831	tNET	FF	1	R8C8[3][A]	uart_data_rx/uart_byte_rx/START_BIT_2_s5/I0
7.979	1.099	tINS	FF	1	R8C8[3][A]	uart_data_rx/uart_byte_rx/START_BIT_2_s5/F
7.985	0.005	tNET	FF	1	R8C8[2][B]	uart_data_rx/uart_byte_rx/bps_cnt_7_s6/I3
8.807	0.822	tINS	FF	2	R8C8[2][B]	uart_data_rx/uart_byte_rx/bps_cnt_7_s6/F
9.632	0.825	tNET	FF	1	R8C10[2][B]	uart_data_rx/uart_byte_rx/bps_cnt_7_s4/I2
10.258	0.626	tINS	FF	5	R8C10[2][B]	uart_data_rx/uart_byte_rx/bps_cnt_7_s4/F
11.569	1.311	tNET	FF	1	R5C8[0][A]	uart_data_rx/uart_byte_rx/n156_s3/I1
12.668	1.099	tINS	FF	1	R5C8[0][A]	uart_data_rx/uart_byte_rx/n156_s3/F
12.668	0.000	tNET	FF	1	R5C8[0][A]	uart_data_rx/uart_byte_rx/bps_cnt_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
25.591	1.361	tNET	RR	1	R5C8[0][A]	uart_data_rx/uart_byte_rx/bps_cnt_0_s1/CLK
25.191	-0.400	tSu		1	R5C8[0][A]	uart_data_rx/uart_byte_rx/bps_cnt_0_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.646, 51.518%; route: 2.973, 42.005%; tC2Q: 0.458, 6.476%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path22

Path Summary:

Slack	12.566
Data Arrival Time	12.625
Data Required Time	25.191
From	uart_data_rx/uart_byte_rx/div_cnt_11_s0
To	uart_data_rx/uart_byte_rx/div_cnt_13_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
5.591	1.361	tNET	RR	1	R7C5[1][B]	uart_data_rx/uart_byte_rx/div_cnt_11_s0/CLK
6.049	0.458	tC2Q	RF	5	R7C5[1][B]	uart_data_rx/uart_byte_rx/div_cnt_11_s0/Q
6.865	0.815	tNET	FF	1	R6C6[1][A]	uart_data_rx/uart_byte_rx/n124_s5/I3
7.926	1.061	tINS	FR	1	R6C6[1][A]	uart_data_rx/uart_byte_rx/n124_s5/F
8.345	0.419	tNET	RR	1	R6C7[0][B]	uart_data_rx/uart_byte_rx/n124_s2/I3
9.377	1.032	tINS	RF	3	R6C7[0][B]	uart_data_rx/uart_byte_rx/n124_s2/F
10.676	1.300	tNET	FF	1	R7C7[1][B]	uart_data_rx/uart_byte_rx/n104_s4/I1
11.498	0.822	tINS	FF	13	R7C7[1][B]	uart_data_rx/uart_byte_rx/n104_s4/F
11.526	0.027	tNET	FF	1	R7C7[0][B]	uart_data_rx/uart_byte_rx/n91_s2/I3
12.625	1.099	tINS	FF	1	R7C7[0][B]	uart_data_rx/uart_byte_rx/n91_s2/F
12.625	0.000	tNET	FF	1	R7C7[0][B]	uart_data_rx/uart_byte_rx/div_cnt_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
25.591	1.361	tNET	RR	1	R7C7[0][B]	uart_data_rx/uart_byte_rx/div_cnt_13_s0/CLK
25.191	-0.400	tSu		1	R7C7[0][B]	uart_data_rx/uart_byte_rx/div_cnt_13_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 4.014, 57.067%; route: 2.561, 36.416%; tC2Q: 0.458, 6.516%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path23

Path Summary:

Slack	12.599
Data Arrival Time	12.949
Data Required Time	25.548
From	uart_data_rx/uart_byte_rx/bps_cnt_5_s1
To	uart_data_rx/uart_byte_rx/data_byte_pre[3]_0_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
5.591	1.361	tNET	RR	1	R7C9[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_5_s1/CLK
6.049	0.458	tC2Q	RF	15	R7C9[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_5_s1/Q
6.880	0.831	tNET	FF	1	R8C8[3][A]	uart_data_rx/uart_byte_rx/START_BIT_2_s5/I0
7.979	1.099	tINS	FF	1	R8C8[3][A]	uart_data_rx/uart_byte_rx/START_BIT_2_s5/F
7.985	0.005	tNET	FF	1	R8C8[2][B]	uart_data_rx/uart_byte_rx/bps_cnt_7_s6/I3
8.807	0.822	tINS	FF	2	R8C8[2][B]	uart_data_rx/uart_byte_rx/bps_cnt_7_s6/F
9.301	0.495	tNET	FF	1	R8C10[3][B]	uart_data_rx/uart_byte_rx/START_BIT_2_s3/I2
10.333	1.032	tINS	FF	10	R8C10[3][B]	uart_data_rx/uart_byte_rx/START_BIT_2_s3/F
11.182	0.849	tNET	FF	1	R8C7[3][A]	uart_data_rx/uart_byte_rx/data_byte_pre[3]_2_s2/I1
12.243	1.061	tINS	FR	3	R8C7[3][A]	uart_data_rx/uart_byte_rx/data_byte_pre[3]_2_s2/F
12.949	0.706	tNET	RR	1	R6C7[2][A]	uart_data_rx/uart_byte_rx/data_byte_pre[3]_0_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
25.591	1.361	tNET	RR	1	R6C7[2][A]	uart_data_rx/uart_byte_rx/data_byte_pre[3]_0_s0/CLK
25.548	-0.043	tSu		1	R6C7[2][A]	uart_data_rx/uart_byte_rx/data_byte_pre[3]_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 4.014, 54.557%; route: 2.885, 39.213%; tC2Q: 0.458, 6.230%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path24

Path Summary:

Slack	12.627
Data Arrival Time	12.921
Data Required Time	25.548
From	uart_data_rx/uart_byte_rx/bps_cnt_5_s1
To	uart_data_rx/uart_byte_rx/data_byte_pre[7]_0_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
5.591	1.361	tNET	RR	1	R7C9[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_5_s1/CLK
6.049	0.458	tC2Q	RF	15	R7C9[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_5_s1/Q
6.880	0.831	tNET	FF	1	R8C8[3][A]	uart_data_rx/uart_byte_rx/START_BIT_2_s5/I0
7.979	1.099	tINS	FF	1	R8C8[3][A]	uart_data_rx/uart_byte_rx/START_BIT_2_s5/F
7.985	0.005	tNET	FF	1	R8C8[2][B]	uart_data_rx/uart_byte_rx/bps_cnt_7_s6/I3
8.807	0.822	tINS	FF	2	R8C8[2][B]	uart_data_rx/uart_byte_rx/bps_cnt_7_s6/F
9.301	0.495	tNET	FF	1	R8C10[3][B]	uart_data_rx/uart_byte_rx/START_BIT_2_s3/I2
10.333	1.032	tINS	FF	10	R8C10[3][B]	uart_data_rx/uart_byte_rx/START_BIT_2_s3/F
10.372	0.038	tNET	FF	1	R8C10[0][B]	uart_data_rx/uart_byte_rx/data_byte_pre[7]_2_s2/I1
11.398	1.026	tINS	FR	3	R8C10[0][B]	uart_data_rx/uart_byte_rx/data_byte_pre[7]_2_s2/F
12.921	1.524	tNET	RR	1	R8C10[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[7]_0_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
25.591	1.361	tNET	RR	1	R8C10[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[7]_0_s0/CLK
25.548	-0.043	tSu		1	R8C10[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[7]_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.979, 54.283%; route: 2.893, 39.464%; tC2Q: 0.458, 6.253%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path25

Path Summary:

Slack	12.753
Data Arrival Time	12.438
Data Required Time	25.191
From	uart_data_tx/uart_byte_tx/div_cnt_10_s0
To	uart_data_tx/uart_byte_tx/div_cnt_3_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
5.591	1.361	tNET	RR	1	R14C8[0][A]	uart_data_tx/uart_byte_tx/div_cnt_10_s0/CLK
6.049	0.458	tC2Q	RF	3	R14C8[0][A]	uart_data_tx/uart_byte_tx/div_cnt_10_s0/Q
6.861	0.811	tNET	FF	1	R15C9[2][A]	uart_data_tx/uart_byte_tx/n145_s5/I0
7.887	1.026	tINS	FR	1	R15C9[2][A]	uart_data_tx/uart_byte_tx/n145_s5/F
8.306	0.419	tNET	RR	1	R14C9[3][B]	uart_data_tx/uart_byte_tx/n145_s2/I3
8.932	0.626	tINS	RF	2	R14C9[3][B]	uart_data_tx/uart_byte_tx/n145_s2/F
9.741	0.810	tNET	FF	1	R15C8[2][A]	uart_data_tx/uart_byte_tx/n123_s3/I0
10.773	1.032	tINS	FF	12	R15C8[2][A]	uart_data_tx/uart_byte_tx/n123_s3/F
11.616	0.843	tNET	FF	1	R14C7[1][B]	uart_data_tx/uart_byte_tx/n122_s2/I2
12.438	0.822	tINS	FF	1	R14C7[1][B]	uart_data_tx/uart_byte_tx/n122_s2/F
12.438	0.000	tNET	FF	1	R14C7[1][B]	uart_data_tx/uart_byte_tx/div_cnt_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	268	IOT13[A]	Clk_ibuf/O
25.591	1.361	tNET	RR	1	R14C7[1][B]	uart_data_tx/uart_byte_tx/div_cnt_3_s0/CLK
25.191	-0.400	tSu		1	R14C7[1][B]	uart_data_tx/uart_byte_tx/div_cnt_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.506, 51.203%; route: 2.883, 42.104%; tC2Q: 0.458, 6.694%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.562
Data Arrival Time	4.667
Data Required Time	4.105
From	uart_data_rx/to_state_s4
To	uart_data_rx/timeout_cnt_11_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R5C12[0][A]	uart_data_rx/to_state_s4/CLK
4.426	0.333	tC2Q	RR	19	R5C12[0][A]	uart_data_rx/to_state_s4/Q
4.667	0.241	tNET	RR	1	R5C12[1][A]	uart_data_rx/timeout_cnt_11_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R5C12[1][A]	uart_data_rx/timeout_cnt_11_s0/CLK
4.105	0.012	tHld		1	R5C12[1][A]	uart_data_rx/timeout_cnt_11_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.241, 41.973%; tC2Q: 0.333, 58.027%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path2

Path Summary:

Slack	0.562
Data Arrival Time	4.667
Data Required Time	4.105
From	uart_data_rx/to_state_s4
To	uart_data_rx/timeout_cnt_14_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R5C12[0][A]	uart_data_rx/to_state_s4/CLK
4.426	0.333	tC2Q	RR	19	R5C12[0][A]	uart_data_rx/to_state_s4/Q
4.667	0.241	tNET	RR	1	R5C12[1][B]	uart_data_rx/timeout_cnt_14_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R5C12[1][B]	uart_data_rx/timeout_cnt_14_s0/CLK
4.105	0.012	tHld		1	R5C12[1][B]	uart_data_rx/timeout_cnt_14_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.241, 41.973%; tC2Q: 0.333, 58.027%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path3

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	uart_data_tx/uart_byte_tx/div_cnt_1_s0
To	uart_data_tx/uart_byte_tx/div_cnt_1_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R15C8[1][A]	uart_data_tx/uart_byte_tx/div_cnt_1_s0/CLK
4.426	0.333	tC2Q	RR	5	R15C8[1][A]	uart_data_tx/uart_byte_tx/div_cnt_1_s0/Q
4.428	0.002	tNET	RR	1	R15C8[1][A]	uart_data_tx/uart_byte_tx/n124_s2/I1
4.800	0.372	tINS	RF	1	R15C8[1][A]	uart_data_tx/uart_byte_tx/n124_s2/F
4.800	0.000	tNET	FF	1	R15C8[1][A]	uart_data_tx/uart_byte_tx/div_cnt_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R15C8[1][A]	uart_data_tx/uart_byte_tx/div_cnt_1_s0/CLK
4.093	0.000	tHld		1	R15C8[1][A]	uart_data_tx/uart_byte_tx/div_cnt_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path4

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	uart_data_tx/data_byte_0_s2
To	uart_data_tx/data_byte_0_s2
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R13C13[0][A]	uart_data_tx/data_byte_0_s2/CLK
4.426	0.333	tC2Q	RR	2	R13C13[0][A]	uart_data_tx/data_byte_0_s2/Q
4.428	0.002	tNET	RR	1	R13C13[0][A]	uart_data_tx/n97_s6/I2
4.800	0.372	tINS	RF	1	R13C13[0][A]	uart_data_tx/n97_s6/F
4.800	0.000	tNET	FF	1	R13C13[0][A]	uart_data_tx/data_byte_0_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R13C13[0][A]	uart_data_tx/data_byte_0_s2/CLK
4.093	0.000	tHld		1	R13C13[0][A]	uart_data_tx/data_byte_0_s2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path5

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	uart_data_tx/data_byte_2_s2
To	uart_data_tx/data_byte_2_s2
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R13C12[0][A]	uart_data_tx/data_byte_2_s2/CLK
4.426	0.333	tC2Q	RR	2	R13C12[0][A]	uart_data_tx/data_byte_2_s2/Q
4.428	0.002	tNET	RR	1	R13C12[0][A]	uart_data_tx/n95_s6/I2
4.800	0.372	tINS	RF	1	R13C12[0][A]	uart_data_tx/n95_s6/F
4.800	0.000	tNET	FF	1	R13C12[0][A]	uart_data_tx/data_byte_2_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R13C12[0][A]	uart_data_tx/data_byte_2_s2/CLK
4.093	0.000	tHld		1	R13C12[0][A]	uart_data_tx/data_byte_2_s2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path6

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	uart_data_tx/data_byte_4_s2
To	uart_data_tx/data_byte_4_s2
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R13C12[1][A]	uart_data_tx/data_byte_4_s2/CLK
4.426	0.333	tC2Q	RR	2	R13C12[1][A]	uart_data_tx/data_byte_4_s2/Q
4.428	0.002	tNET	RR	1	R13C12[1][A]	uart_data_tx/n93_s6/I2
4.800	0.372	tINS	RF	1	R13C12[1][A]	uart_data_tx/n93_s6/F
4.800	0.000	tNET	FF	1	R13C12[1][A]	uart_data_tx/data_byte_4_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R13C12[1][A]	uart_data_tx/data_byte_4_s2/CLK
4.093	0.000	tHld		1	R13C12[1][A]	uart_data_tx/data_byte_4_s2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path7

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	uart_data_tx/data_byte_5_s2
To	uart_data_tx/data_byte_5_s2
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R13C11[0][A]	uart_data_tx/data_byte_5_s2/CLK
4.426	0.333	tC2Q	RR	2	R13C11[0][A]	uart_data_tx/data_byte_5_s2/Q
4.428	0.002	tNET	RR	1	R13C11[0][A]	uart_data_tx/n92_s6/I2
4.800	0.372	tINS	RF	1	R13C11[0][A]	uart_data_tx/n92_s6/F
4.800	0.000	tNET	FF	1	R13C11[0][A]	uart_data_tx/data_byte_5_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R13C11[0][A]	uart_data_tx/data_byte_5_s2/CLK
4.093	0.000	tHld		1	R13C11[0][A]	uart_data_tx/data_byte_5_s2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path8

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	uart_data_rx/uart_byte_rx/STOP_BIT_1_s0
To	uart_data_rx/uart_byte_rx/STOP_BIT_1_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R5C10[0][A]	uart_data_rx/uart_byte_rx/STOP_BIT_1_s0/CLK
4.426	0.333	tC2Q	RR	2	R5C10[0][A]	uart_data_rx/uart_byte_rx/STOP_BIT_1_s0/Q
4.428	0.002	tNET	RR	1	R5C10[0][A]	uart_data_rx/uart_byte_rx/n592_s5/I2
4.800	0.372	tINS	RF	1	R5C10[0][A]	uart_data_rx/uart_byte_rx/n592_s5/F
4.800	0.000	tNET	FF	1	R5C10[0][A]	uart_data_rx/uart_byte_rx/STOP_BIT_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R5C10[0][A]	uart_data_rx/uart_byte_rx/STOP_BIT_1_s0/CLK
4.093	0.000	tHld		1	R5C10[0][A]	uart_data_rx/uart_byte_rx/STOP_BIT_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path9

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	uart_data_rx/uart_byte_rx/STOP_BIT_2_s0
To	uart_data_rx/uart_byte_rx/STOP_BIT_2_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C11[1][A]	uart_data_rx/uart_byte_rx/STOP_BIT_2_s0/CLK
4.426	0.333	tC2Q	RR	2	R8C11[1][A]	uart_data_rx/uart_byte_rx/STOP_BIT_2_s0/Q
4.428	0.002	tNET	RR	1	R8C11[1][A]	uart_data_rx/uart_byte_rx/n589_s5/I2
4.800	0.372	tINS	RF	1	R8C11[1][A]	uart_data_rx/uart_byte_rx/n589_s5/F
4.800	0.000	tNET	FF	1	R8C11[1][A]	uart_data_rx/uart_byte_rx/STOP_BIT_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C11[1][A]	uart_data_rx/uart_byte_rx/STOP_BIT_2_s0/CLK
4.093	0.000	tHld		1	R8C11[1][A]	uart_data_rx/uart_byte_rx/STOP_BIT_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path10

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	uart_data_rx/uart_byte_rx/data_byte_pre[0]_2_s0
To	uart_data_rx/uart_byte_rx/data_byte_pre[0]_2_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C6[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[0]_2_s0/CLK
4.426	0.333	tC2Q	RR	2	R8C6[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[0]_2_s0/Q
4.428	0.002	tNET	RR	1	R8C6[1][A]	uart_data_rx/uart_byte_rx/n580_s5/I2
4.800	0.372	tINS	RF	1	R8C6[1][A]	uart_data_rx/uart_byte_rx/n580_s5/F
4.800	0.000	tNET	FF	1	R8C6[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[0]_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C6[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[0]_2_s0/CLK
4.093	0.000	tHld		1	R8C6[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[0]_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path11

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	uart_data_rx/uart_byte_rx/data_byte_pre[1]_1_s0
To	uart_data_rx/uart_byte_rx/data_byte_pre[1]_1_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C7[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[1]_1_s0/CLK
4.426	0.333	tC2Q	RR	2	R8C7[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[1]_1_s0/Q
4.428	0.002	tNET	RR	1	R8C7[0][A]	uart_data_rx/uart_byte_rx/n574_s6/I0
4.800	0.372	tINS	RF	1	R8C7[0][A]	uart_data_rx/uart_byte_rx/n574_s6/F
4.800	0.000	tNET	FF	1	R8C7[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[1]_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C7[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[1]_1_s0/CLK
4.093	0.000	tHld		1	R8C7[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[1]_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path12

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	uart_data_rx/uart_byte_rx/data_byte_pre[1]_2_s0
To	uart_data_rx/uart_byte_rx/data_byte_pre[1]_2_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C5[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[1]_2_s0/CLK
4.426	0.333	tC2Q	RR	2	R8C5[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[1]_2_s0/Q
4.428	0.002	tNET	RR	1	R8C5[0][A]	uart_data_rx/uart_byte_rx/n571_s5/I2
4.800	0.372	tINS	RF	1	R8C5[0][A]	uart_data_rx/uart_byte_rx/n571_s5/F
4.800	0.000	tNET	FF	1	R8C5[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[1]_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C5[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[1]_2_s0/CLK
4.093	0.000	tHld		1	R8C5[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[1]_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path13

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	uart_data_rx/uart_byte_rx/data_byte_pre[2]_0_s0
To	uart_data_rx/uart_byte_rx/data_byte_pre[2]_0_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R6C6[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[2]_0_s0/CLK
4.426	0.333	tC2Q	RR	3	R6C6[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[2]_0_s0/Q
4.428	0.002	tNET	RR	1	R6C6[0][A]	uart_data_rx/uart_byte_rx/n568_s5/I1
4.800	0.372	tINS	RF	1	R6C6[0][A]	uart_data_rx/uart_byte_rx/n568_s5/F
4.800	0.000	tNET	FF	1	R6C6[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[2]_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R6C6[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[2]_0_s0/CLK
4.093	0.000	tHld		1	R6C6[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[2]_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path14

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	uart_data_rx/uart_byte_rx/data_byte_pre[2]_2_s0
To	uart_data_rx/uart_byte_rx/data_byte_pre[2]_2_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C5[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[2]_2_s0/CLK
4.426	0.333	tC2Q	RR	2	R8C5[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[2]_2_s0/Q
4.428	0.002	tNET	RR	1	R8C5[1][A]	uart_data_rx/uart_byte_rx/n562_s5/I2
4.800	0.372	tINS	RF	1	R8C5[1][A]	uart_data_rx/uart_byte_rx/n562_s5/F
4.800	0.000	tNET	FF	1	R8C5[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[2]_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C5[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[2]_2_s0/CLK
4.093	0.000	tHld		1	R8C5[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[2]_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path15

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	uart_data_rx/uart_byte_rx/data_byte_pre[3]_2_s0
To	uart_data_rx/uart_byte_rx/data_byte_pre[3]_2_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C7[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[3]_2_s0/CLK
4.426	0.333	tC2Q	RR	2	R8C7[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[3]_2_s0/Q
4.428	0.002	tNET	RR	1	R8C7[1][A]	uart_data_rx/uart_byte_rx/n553_s5/I2
4.800	0.372	tINS	RF	1	R8C7[1][A]	uart_data_rx/uart_byte_rx/n553_s5/F
4.800	0.000	tNET	FF	1	R8C7[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[3]_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C7[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[3]_2_s0/CLK
4.093	0.000	tHld		1	R8C7[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[3]_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path16

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	uart_data_rx/uart_byte_rx/data_byte_pre[4]_0_s0
To	uart_data_rx/uart_byte_rx/data_byte_pre[4]_0_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C9[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[4]_0_s0/CLK
4.426	0.333	tC2Q	RR	3	R8C9[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[4]_0_s0/Q
4.428	0.002	tNET	RR	1	R8C9[0][A]	uart_data_rx/uart_byte_rx/n550_s5/I1
4.800	0.372	tINS	RF	1	R8C9[0][A]	uart_data_rx/uart_byte_rx/n550_s5/F
4.800	0.000	tNET	FF	1	R8C9[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[4]_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C9[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[4]_0_s0/CLK
4.093	0.000	tHld		1	R8C9[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[4]_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path17

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	uart_data_rx/uart_byte_rx/data_byte_pre[4]_1_s0
To	uart_data_rx/uart_byte_rx/data_byte_pre[4]_1_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C9[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[4]_1_s0/CLK
4.426	0.333	tC2Q	RR	2	R8C9[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[4]_1_s0/Q
4.428	0.002	tNET	RR	1	R8C9[1][A]	uart_data_rx/uart_byte_rx/n547_s6/I0
4.800	0.372	tINS	RF	1	R8C9[1][A]	uart_data_rx/uart_byte_rx/n547_s6/F
4.800	0.000	tNET	FF	1	R8C9[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[4]_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C9[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[4]_1_s0/CLK
4.093	0.000	tHld		1	R8C9[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[4]_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path18

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	uart_data_rx/uart_byte_rx/data_byte_pre[6]_0_s0
To	uart_data_rx/uart_byte_rx/data_byte_pre[6]_0_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C10[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[6]_0_s0/CLK
4.426	0.333	tC2Q	RR	3	R8C10[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[6]_0_s0/Q
4.428	0.002	tNET	RR	1	R8C10[1][A]	uart_data_rx/uart_byte_rx/n532_s5/I1
4.800	0.372	tINS	RF	1	R8C10[1][A]	uart_data_rx/uart_byte_rx/n532_s5/F
4.800	0.000	tNET	FF	1	R8C10[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[6]_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C10[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[6]_0_s0/CLK
4.093	0.000	tHld		1	R8C10[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[6]_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path19

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	uart_data_rx/uart_byte_rx/data_byte_pre[7]_0_s0
To	uart_data_rx/uart_byte_rx/data_byte_pre[7]_0_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C10[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[7]_0_s0/CLK
4.426	0.333	tC2Q	RR	3	R8C10[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[7]_0_s0/Q
4.428	0.002	tNET	RR	1	R8C10[0][A]	uart_data_rx/uart_byte_rx/n523_s5/I1
4.800	0.372	tINS	RF	1	R8C10[0][A]	uart_data_rx/uart_byte_rx/n523_s5/F
4.800	0.000	tNET	FF	1	R8C10[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[7]_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C10[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[7]_0_s0/CLK
4.093	0.000	tHld		1	R8C10[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[7]_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path20

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	uart_data_rx/uart_byte_rx/data_byte_pre[7]_2_s0
To	uart_data_rx/uart_byte_rx/data_byte_pre[7]_2_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R7C10[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[7]_2_s0/CLK
4.426	0.333	tC2Q	RR	2	R7C10[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[7]_2_s0/Q
4.428	0.002	tNET	RR	1	R7C10[1][A]	uart_data_rx/uart_byte_rx/n517_s5/I2
4.800	0.372	tINS	RF	1	R7C10[1][A]	uart_data_rx/uart_byte_rx/n517_s5/F
4.800	0.000	tNET	FF	1	R7C10[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[7]_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R7C10[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[7]_2_s0/CLK
4.093	0.000	tHld		1	R7C10[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[7]_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path21

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	uart_data_rx/uart_byte_rx/div_cnt_3_s0
To	uart_data_rx/uart_byte_rx/div_cnt_3_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R7C5[0][A]	uart_data_rx/uart_byte_rx/div_cnt_3_s0/CLK
4.426	0.333	tC2Q	RR	4	R7C5[0][A]	uart_data_rx/uart_byte_rx/div_cnt_3_s0/Q
4.428	0.002	tNET	RR	1	R7C5[0][A]	uart_data_rx/uart_byte_rx/n101_s2/I2
4.800	0.372	tINS	RF	1	R7C5[0][A]	uart_data_rx/uart_byte_rx/n101_s2/F
4.800	0.000	tNET	FF	1	R7C5[0][A]	uart_data_rx/uart_byte_rx/div_cnt_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R7C5[0][A]	uart_data_rx/uart_byte_rx/div_cnt_3_s0/CLK
4.093	0.000	tHld		1	R7C5[0][A]	uart_data_rx/uart_byte_rx/div_cnt_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path22

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	uart_data_rx/uart_byte_rx/div_cnt_6_s0
To	uart_data_rx/uart_byte_rx/div_cnt_6_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R7C6[1][A]	uart_data_rx/uart_byte_rx/div_cnt_6_s0/CLK
4.426	0.333	tC2Q	RR	3	R7C6[1][A]	uart_data_rx/uart_byte_rx/div_cnt_6_s0/Q
4.428	0.002	tNET	RR	1	R7C6[1][A]	uart_data_rx/uart_byte_rx/n98_s2/I0
4.800	0.372	tINS	RF	1	R7C6[1][A]	uart_data_rx/uart_byte_rx/n98_s2/F
4.800	0.000	tNET	FF	1	R7C6[1][A]	uart_data_rx/uart_byte_rx/div_cnt_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R7C6[1][A]	uart_data_rx/uart_byte_rx/div_cnt_6_s0/CLK
4.093	0.000	tHld		1	R7C6[1][A]	uart_data_rx/uart_byte_rx/div_cnt_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path23

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	uart_data_rx/uart_byte_rx/div_cnt_12_s0
To	uart_data_rx/uart_byte_rx/div_cnt_12_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R7C6[0][A]	uart_data_rx/uart_byte_rx/div_cnt_12_s0/CLK
4.426	0.333	tC2Q	RR	5	R7C6[0][A]	uart_data_rx/uart_byte_rx/div_cnt_12_s0/Q
4.428	0.002	tNET	RR	1	R7C6[0][A]	uart_data_rx/uart_byte_rx/n92_s2/I2
4.800	0.372	tINS	RF	1	R7C6[0][A]	uart_data_rx/uart_byte_rx/n92_s2/F
4.800	0.000	tNET	FF	1	R7C6[0][A]	uart_data_rx/uart_byte_rx/div_cnt_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R7C6[0][A]	uart_data_rx/uart_byte_rx/div_cnt_12_s0/CLK
4.093	0.000	tHld		1	R7C6[0][A]	uart_data_rx/uart_byte_rx/div_cnt_12_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path24

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	uart_data_rx/uart_byte_rx/div_cnt_15_s0
To	uart_data_rx/uart_byte_rx/div_cnt_15_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R7C7[1][A]	uart_data_rx/uart_byte_rx/div_cnt_15_s0/CLK
4.426	0.333	tC2Q	RR	2	R7C7[1][A]	uart_data_rx/uart_byte_rx/div_cnt_15_s0/Q
4.428	0.002	tNET	RR	1	R7C7[1][A]	uart_data_rx/uart_byte_rx/n89_s2/I2
4.800	0.372	tINS	RF	1	R7C7[1][A]	uart_data_rx/uart_byte_rx/n89_s2/F
4.800	0.000	tNET	FF	1	R7C7[1][A]	uart_data_rx/uart_byte_rx/div_cnt_15_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R7C7[1][A]	uart_data_rx/uart_byte_rx/div_cnt_15_s0/CLK
4.093	0.000	tHld		1	R7C7[1][A]	uart_data_rx/uart_byte_rx/div_cnt_15_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path25

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	uart_data_rx/cnt_7_s1
To	uart_data_rx/cnt_7_s1
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R11C6[0][A]	uart_data_rx/cnt_7_s1/CLK
4.426	0.333	tC2Q	RR	3	R11C6[0][A]	uart_data_rx/cnt_7_s1/Q
4.428	0.002	tNET	RR	1	R11C6[0][A]	uart_data_rx/n477_s6/I1
4.800	0.372	tINS	RF	1	R11C6[0][A]	uart_data_rx/n477_s6/F
4.800	0.000	tNET	FF	1	R11C6[0][A]	uart_data_rx/cnt_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOT13[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	268	IOT13[A]	Clk_ibuf/O
4.093	0.966	tNET	RR	1	R11C6[0][A]	uart_data_rx/cnt_7_s1/CLK
4.093	0.000	tHld		1	R11C6[0][A]	uart_data_rx/cnt_7_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	Clk
Objects:	uart_data_rx/timeout_cnt_17_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
5.591	1.361	tNET	RR	uart_data_rx/timeout_cnt_17_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
13.362	1.222	tNET	FF	uart_data_rx/timeout_cnt_17_s0/CLK

MPW2

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	Clk
Objects:	uart_data_rx/timeout_cnt_16_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
5.591	1.361	tNET	RR	uart_data_rx/timeout_cnt_16_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
13.362	1.222	tNET	FF	uart_data_rx/timeout_cnt_16_s0/CLK

MPW3

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	Clk
Objects:	uart_data_rx/timeout_cnt_14_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
5.591	1.361	tNET	RR	uart_data_rx/timeout_cnt_14_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
13.362	1.222	tNET	FF	uart_data_rx/timeout_cnt_14_s0/CLK

MPW4

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	Clk
Objects:	uart_data_rx/timeout_cnt_10_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
5.591	1.361	tNET	RR	uart_data_rx/timeout_cnt_10_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
13.362	1.222	tNET	FF	uart_data_rx/timeout_cnt_10_s0/CLK

MPW5

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	Clk
Objects:	uart_data_rx/timeout_cnt_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
5.591	1.361	tNET	RR	uart_data_rx/timeout_cnt_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
13.362	1.222	tNET	FF	uart_data_rx/timeout_cnt_2_s0/CLK

MPW6

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	Clk
Objects:	uart_data_rx/data_r_26_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
5.591	1.361	tNET	RR	uart_data_rx/data_r_26_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
13.362	1.222	tNET	FF	uart_data_rx/data_r_26_s0/CLK

MPW7

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	Clk
Objects:	uart_data_rx/data_34_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
5.591	1.361	tNET	RR	uart_data_rx/data_34_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
13.362	1.222	tNET	FF	uart_data_rx/data_34_s0/CLK

MPW8

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	Clk
Objects:	uart_data_rx/uart_byte_rx/div_cnt_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
5.591	1.361	tNET	RR	uart_data_rx/uart_byte_rx/div_cnt_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
13.362	1.222	tNET	FF	uart_data_rx/uart_byte_rx/div_cnt_0_s0/CLK

MPW9

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	Clk
Objects:	uart_data_tx/uart_byte_tx/div_cnt_4_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
5.591	1.361	tNET	RR	uart_data_tx/uart_byte_tx/div_cnt_4_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
13.362	1.222	tNET	FF	uart_data_tx/uart_byte_tx/div_cnt_4_s0/CLK

MPW10

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	Clk
Objects:	uart_data_tx/uart_byte_tx/div_cnt_5_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
5.591	1.361	tNET	RR	uart_data_tx/uart_byte_tx/div_cnt_5_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
13.362	1.222	tNET	FF	uart_data_tx/uart_byte_tx/div_cnt_5_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
268	Clk_d	11.733	1.727
64	byte_rx_done	13.269	3.775
51	state[0]	15.040	2.831
50	state[0]	13.975	1.854
45	led_d[0]	15.095	2.810
40	n482_9	13.692	1.514
40	data_r_39_8	13.269	3.149
32	data_r_39_8	12.940	2.277
31	uart_rx_sync2	15.068	2.283
23	state[1]	12.940	2.188

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R11C11	83.33%
R11C10	81.94%
R13C7	81.94%
R13C10	80.56%
R13C8	80.56%
R13C9	77.78%
R14C10	76.39%
R12C8	76.39%
R11C12	76.39%
R13C11	75.00%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command