Power Messages
| Report Title | Power Analysis Report |
| Design File | /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/UART_transmit_receive_multiple_byte/impl/gwsynthesis/uart_loopback.vg |
| Physical Constraints File | /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/UART_transmit_receive_multiple_byte/src/uart_loopback.cst |
| Timing Constraints File | --- |
| Tool Version | V1.9.11 |
| Part Number | GW1NSR-LV4CQN48PC6/I5 |
| Device | GW1NSR-4C |
| Created Time | Tue Apr 22 18:37:40 2025 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved. |
Configure Information:
| Grade | Commercial |
| Process | Typical |
| Ambient Temperature | 25.000 |
| Use Custom Theta JA | false |
| Heat Sink | None |
| Air Flow | LFM_0 |
| Use Custom Theta SA | false |
| Board Thermal Model | None |
| Use Custom Theta JB | false |
| Related Vcd File | |
| Related Saif File | |
| Filter Glitches | false |
| Default IO Toggle Rate | 0.125 |
| Default Remain Toggle Rate | 0.125 |
Power Summary
Power Information:
| Total Power (mW) | 10.789 |
| Quiescent Power (mW) | 10.328 |
| Dynamic Power (mW) | 0.461 |
Thermal Information:
| Junction Temperature | 25.386 |
| Theta JA | 40.580 |
| Max Allowed Ambient Temperature | 84.614 |
Supply Information:
| Voltage Source | Voltage | Dynamic Current(mA) | Quiescent Current(mA) | Power(mW) |
|---|---|---|---|---|
| VCC | 1.200 | 0.116 | 3.247 | 4.037 |
| VCCX | 3.300 | 0.063 | 1.584 | 5.436 |
| VCCIO18 | 1.800 | 0.063 | 0.669 | 1.316 |
Power Details
Power By Block Type:
| Block Type | Total Power(mW) | Static Power(mW) | Average Toggle Rate(millions of transitions/sec) |
|---|---|---|---|
| Logic | 0.063 | NA | 6.250 |
| IO | 1.775 | 1.378 | 13.542 |
Power By Hierarchy:
| Hierarchy Entity | Total Power(mW) | Block Dynamic Power(mW) |
|---|---|---|
| uart_loopback | 0.063 | 0.063(0.063) |
| uart_loopback/uart_data_rx/ | 0.042 | 0.042(0.021) |
| uart_loopback/uart_data_rx/uart_byte_rx/ | 0.021 | 0.021(0.000) |
| uart_loopback/uart_data_tx/ | 0.021 | 0.021(0.009) |
| uart_loopback/uart_data_tx/uart_byte_tx/ | 0.009 | 0.009(0.000) |
Power By Clock Domain:
| Clock Domain | Clock Frequency(Mhz) | Total Dynamic Power(mW) |
|---|---|---|
| Clk | 50.000 | 0.064 |