Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/UART_transmit_receive_multiple_byte/src/uart_byte_rx.v /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/UART_transmit_receive_multiple_byte/src/uart_byte_tx.v /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/UART_transmit_receive_multiple_byte/src/uart_data_rx.v /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/UART_transmit_receive_multiple_byte/src/uart_data_tx.v /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/UART_transmit_receive_multiple_byte/src/uart_loopback.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.11 |
| Part Number | GW1NSR-LV4CQN48PC6/I5 |
| Device | GW1NSR-4C |
| Created Time | Tue Apr 22 18:36:21 2025 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | uart_loopback |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.082s, Elapsed time = 0h 0m 0.069s, Peak memory usage = 339.660MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.021s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 339.660MB Optimizing Phase 1: CPU time = 0h 0m 0.011s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 339.660MB Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 339.660MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.003s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 339.660MB Inferring Phase 1: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0s, Peak memory usage = 339.660MB Inferring Phase 2: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 339.660MB Inferring Phase 3: CPU time = 0h 0m 0.003s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 339.660MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.017s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 339.660MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.005s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 339.660MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.003s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 339.660MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 0.997s, Peak memory usage = 339.660MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.106s, Elapsed time = 0h 0m 0.102s, Peak memory usage = 339.660MB Generate output files: CPU time = 0h 0m 0.086s, Elapsed time = 0h 0m 0.084s, Peak memory usage = 339.660MB |
| Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 339.660MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 6 |
| I/O Buf | 6 |
| IBUF | 3 |
| OBUF | 3 |
| Register | 268 |
| DFFE | 34 |
| DFFRE | 8 |
| DFFP | 1 |
| DFFC | 54 |
| DFFCE | 171 |
| LUT | 335 |
| LUT2 | 36 |
| LUT3 | 115 |
| LUT4 | 184 |
| INV | 1 |
| INV | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 336(336 LUT, 0 ALU) / 4608 | 8% |
| Register | 268 / 3573 | 8% |
| --Register as Latch | 0 / 3573 | 0% |
| --Register as FF | 268 / 3573 | 8% |
| BSRAM | 0 / 10 | 0% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | Clk | Base | 20.000 | 50.000 | 0.000 | 10.000 | Clk_ibuf/I |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | Clk | 50.000(MHz) | 100.127(MHz) | 5 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 10.013 |
| Data Arrival Time | 10.313 |
| Data Required Time | 20.326 |
| From | uart_data_rx/timeout_cnt_5_s0 |
| To | uart_data_rx/timeout_cnt_15_s0 |
| Launch Clk | Clk[R] |
| Latch Clk | Clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | Clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | Clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 268 | Clk_ibuf/O |
| 0.726 | 0.726 | tNET | RR | 1 | uart_data_rx/timeout_cnt_5_s0/CLK |
| 1.184 | 0.458 | tC2Q | RF | 5 | uart_data_rx/timeout_cnt_5_s0/Q |
| 2.144 | 0.960 | tNET | FF | 1 | uart_data_rx/n187_s4/I1 |
| 3.243 | 1.099 | tINS | FF | 3 | uart_data_rx/n187_s4/F |
| 4.203 | 0.960 | tNET | FF | 1 | uart_data_rx/n181_s3/I1 |
| 5.302 | 1.099 | tINS | FF | 3 | uart_data_rx/n181_s3/F |
| 6.262 | 0.960 | tNET | FF | 1 | uart_data_rx/n180_s3/I1 |
| 7.361 | 1.099 | tINS | FF | 1 | uart_data_rx/n180_s3/F |
| 8.321 | 0.960 | tNET | FF | 1 | uart_data_rx/n180_s2/I0 |
| 9.353 | 1.032 | tINS | FF | 1 | uart_data_rx/n180_s2/F |
| 10.313 | 0.960 | tNET | FF | 1 | uart_data_rx/timeout_cnt_15_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | Clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | Clk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 268 | Clk_ibuf/O |
| 20.726 | 0.726 | tNET | RR | 1 | uart_data_rx/timeout_cnt_15_s0/CLK |
| 20.326 | -0.400 | tSu | 1 | uart_data_rx/timeout_cnt_15_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 4.329, 45.153%; route: 4.800, 50.066%; tC2Q: 0.458, 4.781% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 2
Path Summary:| Slack | 10.080 |
| Data Arrival Time | 10.246 |
| Data Required Time | 20.326 |
| From | uart_data_rx/timeout_cnt_1_s0 |
| To | uart_data_rx/timeout_cnt_2_s0 |
| Launch Clk | Clk[R] |
| Latch Clk | Clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | Clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | Clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 268 | Clk_ibuf/O |
| 0.726 | 0.726 | tNET | RR | 1 | uart_data_rx/timeout_cnt_1_s0/CLK |
| 1.184 | 0.458 | tC2Q | RF | 5 | uart_data_rx/timeout_cnt_1_s0/Q |
| 2.144 | 0.960 | tNET | FF | 1 | uart_data_rx/n98_s101/I1 |
| 3.243 | 1.099 | tINS | FF | 1 | uart_data_rx/n98_s101/F |
| 4.203 | 0.960 | tNET | FF | 1 | uart_data_rx/n98_s98/I0 |
| 5.235 | 1.032 | tINS | FF | 1 | uart_data_rx/n98_s98/F |
| 6.195 | 0.960 | tNET | FF | 1 | uart_data_rx/n98_s109/I0 |
| 7.227 | 1.032 | tINS | FF | 19 | uart_data_rx/n98_s109/F |
| 8.187 | 0.960 | tNET | FF | 1 | uart_data_rx/n193_s2/I1 |
| 9.286 | 1.099 | tINS | FF | 1 | uart_data_rx/n193_s2/F |
| 10.246 | 0.960 | tNET | FF | 1 | uart_data_rx/timeout_cnt_2_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | Clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | Clk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 268 | Clk_ibuf/O |
| 20.726 | 0.726 | tNET | RR | 1 | uart_data_rx/timeout_cnt_2_s0/CLK |
| 20.326 | -0.400 | tSu | 1 | uart_data_rx/timeout_cnt_2_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 4.262, 44.767%; route: 4.800, 50.419%; tC2Q: 0.458, 4.814% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 3
Path Summary:| Slack | 10.080 |
| Data Arrival Time | 10.246 |
| Data Required Time | 20.326 |
| From | uart_data_rx/timeout_cnt_1_s0 |
| To | uart_data_rx/timeout_cnt_3_s0 |
| Launch Clk | Clk[R] |
| Latch Clk | Clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | Clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | Clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 268 | Clk_ibuf/O |
| 0.726 | 0.726 | tNET | RR | 1 | uart_data_rx/timeout_cnt_1_s0/CLK |
| 1.184 | 0.458 | tC2Q | RF | 5 | uart_data_rx/timeout_cnt_1_s0/Q |
| 2.144 | 0.960 | tNET | FF | 1 | uart_data_rx/n98_s101/I1 |
| 3.243 | 1.099 | tINS | FF | 1 | uart_data_rx/n98_s101/F |
| 4.203 | 0.960 | tNET | FF | 1 | uart_data_rx/n98_s98/I0 |
| 5.235 | 1.032 | tINS | FF | 1 | uart_data_rx/n98_s98/F |
| 6.195 | 0.960 | tNET | FF | 1 | uart_data_rx/n98_s109/I0 |
| 7.227 | 1.032 | tINS | FF | 19 | uart_data_rx/n98_s109/F |
| 8.187 | 0.960 | tNET | FF | 1 | uart_data_rx/n192_s2/I1 |
| 9.286 | 1.099 | tINS | FF | 1 | uart_data_rx/n192_s2/F |
| 10.246 | 0.960 | tNET | FF | 1 | uart_data_rx/timeout_cnt_3_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | Clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | Clk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 268 | Clk_ibuf/O |
| 20.726 | 0.726 | tNET | RR | 1 | uart_data_rx/timeout_cnt_3_s0/CLK |
| 20.326 | -0.400 | tSu | 1 | uart_data_rx/timeout_cnt_3_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 4.262, 44.767%; route: 4.800, 50.419%; tC2Q: 0.458, 4.814% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 4
Path Summary:| Slack | 10.080 |
| Data Arrival Time | 10.246 |
| Data Required Time | 20.326 |
| From | uart_data_rx/timeout_cnt_1_s0 |
| To | uart_data_rx/timeout_cnt_6_s0 |
| Launch Clk | Clk[R] |
| Latch Clk | Clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | Clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | Clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 268 | Clk_ibuf/O |
| 0.726 | 0.726 | tNET | RR | 1 | uart_data_rx/timeout_cnt_1_s0/CLK |
| 1.184 | 0.458 | tC2Q | RF | 5 | uart_data_rx/timeout_cnt_1_s0/Q |
| 2.144 | 0.960 | tNET | FF | 1 | uart_data_rx/n98_s101/I1 |
| 3.243 | 1.099 | tINS | FF | 1 | uart_data_rx/n98_s101/F |
| 4.203 | 0.960 | tNET | FF | 1 | uart_data_rx/n98_s98/I0 |
| 5.235 | 1.032 | tINS | FF | 1 | uart_data_rx/n98_s98/F |
| 6.195 | 0.960 | tNET | FF | 1 | uart_data_rx/n98_s109/I0 |
| 7.227 | 1.032 | tINS | FF | 19 | uart_data_rx/n98_s109/F |
| 8.187 | 0.960 | tNET | FF | 1 | uart_data_rx/n189_s2/I1 |
| 9.286 | 1.099 | tINS | FF | 1 | uart_data_rx/n189_s2/F |
| 10.246 | 0.960 | tNET | FF | 1 | uart_data_rx/timeout_cnt_6_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | Clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | Clk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 268 | Clk_ibuf/O |
| 20.726 | 0.726 | tNET | RR | 1 | uart_data_rx/timeout_cnt_6_s0/CLK |
| 20.326 | -0.400 | tSu | 1 | uart_data_rx/timeout_cnt_6_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 4.262, 44.767%; route: 4.800, 50.419%; tC2Q: 0.458, 4.814% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 5
Path Summary:| Slack | 10.080 |
| Data Arrival Time | 10.246 |
| Data Required Time | 20.326 |
| From | uart_data_rx/timeout_cnt_1_s0 |
| To | uart_data_rx/timeout_cnt_7_s0 |
| Launch Clk | Clk[R] |
| Latch Clk | Clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | Clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | Clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 268 | Clk_ibuf/O |
| 0.726 | 0.726 | tNET | RR | 1 | uart_data_rx/timeout_cnt_1_s0/CLK |
| 1.184 | 0.458 | tC2Q | RF | 5 | uart_data_rx/timeout_cnt_1_s0/Q |
| 2.144 | 0.960 | tNET | FF | 1 | uart_data_rx/n98_s101/I1 |
| 3.243 | 1.099 | tINS | FF | 1 | uart_data_rx/n98_s101/F |
| 4.203 | 0.960 | tNET | FF | 1 | uart_data_rx/n98_s98/I0 |
| 5.235 | 1.032 | tINS | FF | 1 | uart_data_rx/n98_s98/F |
| 6.195 | 0.960 | tNET | FF | 1 | uart_data_rx/n98_s109/I0 |
| 7.227 | 1.032 | tINS | FF | 19 | uart_data_rx/n98_s109/F |
| 8.187 | 0.960 | tNET | FF | 1 | uart_data_rx/n188_s2/I1 |
| 9.286 | 1.099 | tINS | FF | 1 | uart_data_rx/n188_s2/F |
| 10.246 | 0.960 | tNET | FF | 1 | uart_data_rx/timeout_cnt_7_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | Clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | Clk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 268 | Clk_ibuf/O |
| 20.726 | 0.726 | tNET | RR | 1 | uart_data_rx/timeout_cnt_7_s0/CLK |
| 20.326 | -0.400 | tSu | 1 | uart_data_rx/timeout_cnt_7_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
| Arrival Data Path Delay: | cell: 4.262, 44.767%; route: 4.800, 50.419%; tC2Q: 0.458, 4.814% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |