Timing Messages

Report Title	Timing Analysis Report
Design File	/home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/UART_RX_1BYTE/impl/gwsynthesis/uart_rx.vg
Physical Constraints File	/home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/UART_RX_1BYTE/src/uart_rx.cst
Timing Constraint File	---
Tool Version	V1.9.11
Part Number	GW1NSR-LV4CQN48PC6/I5
Device	GW1NSR-4C
Created Time	Tue Apr 22 18:29:38 2025
Legal Announcement	Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 1.14V 85C C6/I5
Hold Delay Model	Fast 1.26V 0C C6/I5
Numbers of Paths Analyzed	285
Numbers of Endpoints Analyzed	285
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	clk	Base	20.000	50.000	0.000	10.000			clk_ibuf/I

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk	50.000(MHz)	125.417(MHz)	4	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk	Setup	0.000	0
clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Data Delay
1	12.027	uart_byte_rx/bps_cnt_3_s1/Q	uart_byte_rx/data_byte_pre[5]_0_s0/D	clk:[R]	clk:[R]	20.000	7.573
2	12.232	uart_byte_rx/bps_cnt_3_s1/Q	uart_byte_rx/data_byte_pre[5]_2_s0/D	clk:[R]	clk:[R]	20.000	7.368
3	12.398	uart_byte_rx/bps_cnt_3_s1/Q	uart_byte_rx/data_byte_pre[5]_0_s0/CE	clk:[R]	clk:[R]	20.000	7.559
4	12.398	uart_byte_rx/bps_cnt_3_s1/Q	uart_byte_rx/data_byte_pre[5]_1_s0/CE	clk:[R]	clk:[R]	20.000	7.559
5	12.398	uart_byte_rx/bps_cnt_3_s1/Q	uart_byte_rx/data_byte_pre[5]_2_s0/CE	clk:[R]	clk:[R]	20.000	7.559
6	12.428	uart_byte_rx/bps_cnt_3_s1/Q	uart_byte_rx/data_byte_pre[5]_1_s0/D	clk:[R]	clk:[R]	20.000	7.172
7	12.535	uart_byte_rx/bps_cnt_5_s1/Q	uart_byte_rx/data_byte_pre[2]_2_s0/CE	clk:[R]	clk:[R]	20.000	7.421
8	12.535	uart_byte_rx/bps_cnt_5_s1/Q	uart_byte_rx/data_byte_pre[2]_0_s0/CE	clk:[R]	clk:[R]	20.000	7.421
9	12.618	uart_byte_rx/bps_cnt_5_s1/Q	uart_byte_rx/data_byte_pre[2]_1_s0/CE	clk:[R]	clk:[R]	20.000	7.339
10	12.627	uart_byte_rx/bps_cnt_3_s1/Q	uart_byte_rx/data_byte_pre[6]_0_s0/CE	clk:[R]	clk:[R]	20.000	7.330
11	12.900	uart_byte_rx/bps_cnt_3_s1/Q	uart_byte_rx/data_byte_pre[7]_1_s0/D	clk:[R]	clk:[R]	20.000	6.700
12	12.921	uart_byte_rx/bps_cnt_3_s1/Q	uart_byte_rx/data_byte_pre[1]_0_s0/D	clk:[R]	clk:[R]	20.000	6.679
13	12.921	uart_byte_rx/bps_cnt_3_s1/Q	uart_byte_rx/data_byte_pre[1]_1_s0/D	clk:[R]	clk:[R]	20.000	6.679
14	12.944	uart_byte_rx/bps_cnt_6_s1/Q	uart_byte_rx/data_byte_pre[2]_2_s0/D	clk:[R]	clk:[R]	20.000	6.656
15	12.944	uart_byte_rx/bps_cnt_6_s1/Q	uart_byte_rx/data_byte_pre[2]_1_s0/D	clk:[R]	clk:[R]	20.000	6.656
16	13.022	uart_byte_tx/div_cnt_6_s0/Q	uart_byte_tx/div_cnt_14_s0/D	clk:[R]	clk:[R]	20.000	6.578
17	13.022	uart_byte_tx/div_cnt_6_s0/Q	uart_byte_tx/div_cnt_12_s0/D	clk:[R]	clk:[R]	20.000	6.578
18	13.023	uart_byte_rx/bps_cnt_6_s1/Q	uart_byte_rx/data_byte_pre[2]_0_s0/D	clk:[R]	clk:[R]	20.000	6.577
19	13.028	uart_byte_rx/bps_cnt_3_s1/Q	uart_byte_rx/data_byte_pre[6]_1_s0/CE	clk:[R]	clk:[R]	20.000	6.929
20	13.028	uart_byte_rx/bps_cnt_3_s1/Q	uart_byte_rx/data_byte_pre[6]_2_s0/CE	clk:[R]	clk:[R]	20.000	6.929
21	13.047	uart_byte_tx/data_byte_reg_4_s0/Q	uart_byte_tx/uart_tx_s0/D	clk:[R]	clk:[R]	20.000	6.553
22	13.097	uart_byte_tx/div_cnt_6_s0/Q	uart_byte_tx/div_cnt_10_s0/D	clk:[R]	clk:[R]	20.000	6.503
23	13.117	uart_byte_rx/bps_cnt_3_s1/Q	uart_byte_rx/data_byte_pre[1]_2_s0/D	clk:[R]	clk:[R]	20.000	6.483
24	13.137	uart_byte_rx/bps_cnt_5_s1/Q	uart_byte_rx/data_byte_pre[1]_2_s0/CE	clk:[R]	clk:[R]	20.000	6.820
25	13.137	uart_byte_rx/bps_cnt_5_s1/Q	uart_byte_rx/data_byte_pre[1]_1_s0/CE	clk:[R]	clk:[R]	20.000	6.820

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Data Delay
1	0.562	send_en_s0/Q	uart_byte_tx/data_byte_reg_2_s0/CE	clk:[R]	clk:[R]	0.574
2	0.708	uart_byte_rx/STOP_BIT_2_s0/Q	uart_byte_rx/STOP_BIT_2_s0/D	clk:[R]	clk:[R]	0.708
3	0.708	uart_byte_rx/data_byte_pre[0]_2_s0/Q	uart_byte_rx/data_byte_pre[0]_2_s0/D	clk:[R]	clk:[R]	0.708
4	0.708	uart_byte_rx/data_byte_pre[1]_0_s0/Q	uart_byte_rx/data_byte_pre[1]_0_s0/D	clk:[R]	clk:[R]	0.708
5	0.708	uart_byte_rx/data_byte_pre[1]_1_s0/Q	uart_byte_rx/data_byte_pre[1]_1_s0/D	clk:[R]	clk:[R]	0.708
6	0.708	uart_byte_rx/data_byte_pre[2]_1_s0/Q	uart_byte_rx/data_byte_pre[2]_1_s0/D	clk:[R]	clk:[R]	0.708
7	0.708	uart_byte_rx/data_byte_pre[3]_0_s0/Q	uart_byte_rx/data_byte_pre[3]_0_s0/D	clk:[R]	clk:[R]	0.708
8	0.708	uart_byte_rx/data_byte_pre[3]_1_s0/Q	uart_byte_rx/data_byte_pre[3]_1_s0/D	clk:[R]	clk:[R]	0.708
9	0.708	uart_byte_rx/data_byte_pre[4]_0_s0/Q	uart_byte_rx/data_byte_pre[4]_0_s0/D	clk:[R]	clk:[R]	0.708
10	0.708	uart_byte_rx/data_byte_pre[4]_1_s0/Q	uart_byte_rx/data_byte_pre[4]_1_s0/D	clk:[R]	clk:[R]	0.708
11	0.708	uart_byte_rx/data_byte_pre[5]_0_s0/Q	uart_byte_rx/data_byte_pre[5]_0_s0/D	clk:[R]	clk:[R]	0.708
12	0.708	uart_byte_rx/data_byte_pre[6]_2_s0/Q	uart_byte_rx/data_byte_pre[6]_2_s0/D	clk:[R]	clk:[R]	0.708
13	0.708	uart_byte_rx/div_cnt_9_s0/Q	uart_byte_rx/div_cnt_9_s0/D	clk:[R]	clk:[R]	0.708
14	0.708	uart_byte_rx/div_cnt_12_s0/Q	uart_byte_rx/div_cnt_12_s0/D	clk:[R]	clk:[R]	0.708
15	0.708	uart_byte_rx/div_cnt_13_s0/Q	uart_byte_rx/div_cnt_13_s0/D	clk:[R]	clk:[R]	0.708
16	0.709	uart_byte_rx/STOP_BIT_0_s0/Q	uart_byte_rx/STOP_BIT_0_s0/D	clk:[R]	clk:[R]	0.709
17	0.709	uart_byte_rx/data_byte_pre[7]_0_s0/Q	uart_byte_rx/data_byte_pre[7]_0_s0/D	clk:[R]	clk:[R]	0.709
18	0.709	uart_byte_rx/div_cnt_8_s0/Q	uart_byte_rx/div_cnt_8_s0/D	clk:[R]	clk:[R]	0.709
19	0.709	uart_byte_tx/bps_cnt_3_s1/Q	uart_byte_tx/bps_cnt_3_s1/D	clk:[R]	clk:[R]	0.709
20	0.709	uart_byte_tx/div_cnt_14_s0/Q	uart_byte_tx/div_cnt_14_s0/D	clk:[R]	clk:[R]	0.709
21	0.710	uart_byte_rx/bps_cnt_0_s1/Q	uart_byte_rx/bps_cnt_0_s1/D	clk:[R]	clk:[R]	0.710
22	0.710	uart_byte_rx/START_BIT_0_s0/Q	uart_byte_rx/START_BIT_0_s0/D	clk:[R]	clk:[R]	0.710
23	0.710	uart_byte_tx/div_cnt_8_s0/Q	uart_byte_tx/div_cnt_8_s0/D	clk:[R]	clk:[R]	0.710
24	0.711	uart_byte_rx/bps_cnt_7_s1/Q	uart_byte_rx/bps_cnt_7_s1/D	clk:[R]	clk:[R]	0.711
25	0.711	uart_byte_tx/bps_cnt_1_s3/Q	uart_byte_tx/bps_cnt_1_s3/D	clk:[R]	clk:[R]	0.711

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	6.521	7.771	1.250	High Pulse Width	clk	data_byte_tx_6_s0
2	6.521	7.771	1.250	High Pulse Width	clk	data_byte_tx_5_s0
3	6.521	7.771	1.250	High Pulse Width	clk	data_byte_tx_3_s0
4	6.521	7.771	1.250	High Pulse Width	clk	send_en_s0
5	6.521	7.771	1.250	High Pulse Width	clk	uart_byte_tx/data_byte_reg_1_s0
6	6.521	7.771	1.250	High Pulse Width	clk	uart_byte_tx/div_cnt_1_s0
7	6.521	7.771	1.250	High Pulse Width	clk	uart_byte_rx/START_BIT_0_s0
8	6.521	7.771	1.250	High Pulse Width	clk	uart_byte_rx/START_BIT_1_s0
9	6.521	7.771	1.250	High Pulse Width	clk	uart_byte_tx/div_cnt_2_s0
10	6.521	7.771	1.250	High Pulse Width	clk	uart_byte_rx/START_BIT_2_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	12.027
Data Arrival Time	13.164
Data Required Time	25.191
From	uart_byte_rx/bps_cnt_3_s1
To	uart_byte_rx/data_byte_pre[5]_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R11C12[1][A]	uart_byte_rx/bps_cnt_3_s1/CLK
6.049	0.458	tC2Q	RF	7	R11C12[1][A]	uart_byte_rx/bps_cnt_3_s1/Q
7.374	1.325	tNET	FF	1	R13C10[2][B]	uart_byte_rx/START_BIT_2_s5/I1
8.473	1.099	tINS	FF	9	R13C10[2][B]	uart_byte_rx/START_BIT_2_s5/F
9.310	0.837	tNET	FF	1	R12C11[3][B]	uart_byte_rx/data_byte_pre[5]_2_s3/I0
10.342	1.032	tINS	FF	4	R12C11[3][B]	uart_byte_rx/data_byte_pre[5]_2_s3/F
12.132	1.790	tNET	FF	1	R9C8[1][A]	uart_byte_rx/n541_s5/I2
13.164	1.032	tINS	FF	1	R9C8[1][A]	uart_byte_rx/n541_s5/F
13.164	0.000	tNET	FF	1	R9C8[1][A]	uart_byte_rx/data_byte_pre[5]_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R9C8[1][A]	uart_byte_rx/data_byte_pre[5]_0_s0/CLK
25.191	-0.400	tSu		1	R9C8[1][A]	uart_byte_rx/data_byte_pre[5]_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.163, 41.765%; route: 3.952, 52.183%; tC2Q: 0.458, 6.052%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path2

Path Summary:

Slack	12.232
Data Arrival Time	12.959
Data Required Time	25.191
From	uart_byte_rx/bps_cnt_3_s1
To	uart_byte_rx/data_byte_pre[5]_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R11C12[1][A]	uart_byte_rx/bps_cnt_3_s1/CLK
6.049	0.458	tC2Q	RF	7	R11C12[1][A]	uart_byte_rx/bps_cnt_3_s1/Q
7.374	1.325	tNET	FF	1	R13C10[2][B]	uart_byte_rx/START_BIT_2_s5/I1
8.473	1.099	tINS	FF	9	R13C10[2][B]	uart_byte_rx/START_BIT_2_s5/F
9.310	0.837	tNET	FF	1	R12C11[3][B]	uart_byte_rx/data_byte_pre[5]_2_s3/I0
10.342	1.032	tINS	FF	4	R12C11[3][B]	uart_byte_rx/data_byte_pre[5]_2_s3/F
12.137	1.795	tNET	FF	1	R9C8[1][B]	uart_byte_rx/n535_s5/I3
12.959	0.822	tINS	FF	1	R9C8[1][B]	uart_byte_rx/n535_s5/F
12.959	0.000	tNET	FF	1	R9C8[1][B]	uart_byte_rx/data_byte_pre[5]_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R9C8[1][B]	uart_byte_rx/data_byte_pre[5]_2_s0/CLK
25.191	-0.400	tSu		1	R9C8[1][B]	uart_byte_rx/data_byte_pre[5]_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 2.953, 40.079%; route: 3.957, 53.700%; tC2Q: 0.458, 6.221%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path3

Path Summary:

Slack	12.398
Data Arrival Time	13.150
Data Required Time	25.548
From	uart_byte_rx/bps_cnt_3_s1
To	uart_byte_rx/data_byte_pre[5]_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R11C12[1][A]	uart_byte_rx/bps_cnt_3_s1/CLK
6.049	0.458	tC2Q	RF	7	R11C12[1][A]	uart_byte_rx/bps_cnt_3_s1/Q
7.374	1.325	tNET	FF	1	R13C10[2][B]	uart_byte_rx/START_BIT_2_s5/I1
8.473	1.099	tINS	FF	9	R13C10[2][B]	uart_byte_rx/START_BIT_2_s5/F
9.310	0.837	tNET	FF	1	R12C11[3][B]	uart_byte_rx/data_byte_pre[5]_2_s3/I0
10.342	1.032	tINS	FF	4	R12C11[3][B]	uart_byte_rx/data_byte_pre[5]_2_s3/F
11.637	1.294	tNET	FF	1	R11C8[1][B]	uart_byte_rx/data_byte_pre[5]_2_s2/I0
12.439	0.802	tINS	FR	3	R11C8[1][B]	uart_byte_rx/data_byte_pre[5]_2_s2/F
13.150	0.711	tNET	RR	1	R9C8[1][A]	uart_byte_rx/data_byte_pre[5]_0_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R9C8[1][A]	uart_byte_rx/data_byte_pre[5]_0_s0/CLK
25.548	-0.043	tSu		1	R9C8[1][A]	uart_byte_rx/data_byte_pre[5]_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 2.933, 38.803%; route: 4.167, 55.133%; tC2Q: 0.458, 6.064%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path4

Path Summary:

Slack	12.398
Data Arrival Time	13.150
Data Required Time	25.548
From	uart_byte_rx/bps_cnt_3_s1
To	uart_byte_rx/data_byte_pre[5]_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R11C12[1][A]	uart_byte_rx/bps_cnt_3_s1/CLK
6.049	0.458	tC2Q	RF	7	R11C12[1][A]	uart_byte_rx/bps_cnt_3_s1/Q
7.374	1.325	tNET	FF	1	R13C10[2][B]	uart_byte_rx/START_BIT_2_s5/I1
8.473	1.099	tINS	FF	9	R13C10[2][B]	uart_byte_rx/START_BIT_2_s5/F
9.310	0.837	tNET	FF	1	R12C11[3][B]	uart_byte_rx/data_byte_pre[5]_2_s3/I0
10.342	1.032	tINS	FF	4	R12C11[3][B]	uart_byte_rx/data_byte_pre[5]_2_s3/F
11.637	1.294	tNET	FF	1	R11C8[1][B]	uart_byte_rx/data_byte_pre[5]_2_s2/I0
12.439	0.802	tINS	FR	3	R11C8[1][B]	uart_byte_rx/data_byte_pre[5]_2_s2/F
13.150	0.711	tNET	RR	1	R9C8[2][A]	uart_byte_rx/data_byte_pre[5]_1_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R9C8[2][A]	uart_byte_rx/data_byte_pre[5]_1_s0/CLK
25.548	-0.043	tSu		1	R9C8[2][A]	uart_byte_rx/data_byte_pre[5]_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 2.933, 38.803%; route: 4.167, 55.133%; tC2Q: 0.458, 6.064%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path5

Path Summary:

Slack	12.398
Data Arrival Time	13.150
Data Required Time	25.548
From	uart_byte_rx/bps_cnt_3_s1
To	uart_byte_rx/data_byte_pre[5]_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R11C12[1][A]	uart_byte_rx/bps_cnt_3_s1/CLK
6.049	0.458	tC2Q	RF	7	R11C12[1][A]	uart_byte_rx/bps_cnt_3_s1/Q
7.374	1.325	tNET	FF	1	R13C10[2][B]	uart_byte_rx/START_BIT_2_s5/I1
8.473	1.099	tINS	FF	9	R13C10[2][B]	uart_byte_rx/START_BIT_2_s5/F
9.310	0.837	tNET	FF	1	R12C11[3][B]	uart_byte_rx/data_byte_pre[5]_2_s3/I0
10.342	1.032	tINS	FF	4	R12C11[3][B]	uart_byte_rx/data_byte_pre[5]_2_s3/F
11.637	1.294	tNET	FF	1	R11C8[1][B]	uart_byte_rx/data_byte_pre[5]_2_s2/I0
12.439	0.802	tINS	FR	3	R11C8[1][B]	uart_byte_rx/data_byte_pre[5]_2_s2/F
13.150	0.711	tNET	RR	1	R9C8[1][B]	uart_byte_rx/data_byte_pre[5]_2_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R9C8[1][B]	uart_byte_rx/data_byte_pre[5]_2_s0/CLK
25.548	-0.043	tSu		1	R9C8[1][B]	uart_byte_rx/data_byte_pre[5]_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 2.933, 38.803%; route: 4.167, 55.133%; tC2Q: 0.458, 6.064%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path6

Path Summary:

Slack	12.428
Data Arrival Time	12.763
Data Required Time	25.191
From	uart_byte_rx/bps_cnt_3_s1
To	uart_byte_rx/data_byte_pre[5]_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R11C12[1][A]	uart_byte_rx/bps_cnt_3_s1/CLK
6.049	0.458	tC2Q	RF	7	R11C12[1][A]	uart_byte_rx/bps_cnt_3_s1/Q
7.374	1.325	tNET	FF	1	R13C10[2][B]	uart_byte_rx/START_BIT_2_s5/I1
8.473	1.099	tINS	FF	9	R13C10[2][B]	uart_byte_rx/START_BIT_2_s5/F
9.310	0.837	tNET	FF	1	R12C11[3][B]	uart_byte_rx/data_byte_pre[5]_2_s3/I0
10.342	1.032	tINS	FF	4	R12C11[3][B]	uart_byte_rx/data_byte_pre[5]_2_s3/F
12.137	1.795	tNET	FF	1	R9C8[2][A]	uart_byte_rx/n538_s6/I3
12.763	0.626	tINS	FF	1	R9C8[2][A]	uart_byte_rx/n538_s6/F
12.763	0.000	tNET	FF	1	R9C8[2][A]	uart_byte_rx/data_byte_pre[5]_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R9C8[2][A]	uart_byte_rx/data_byte_pre[5]_1_s0/CLK
25.191	-0.400	tSu		1	R9C8[2][A]	uart_byte_rx/data_byte_pre[5]_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 2.757, 38.442%; route: 3.957, 55.168%; tC2Q: 0.458, 6.391%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path7

Path Summary:

Slack	12.535
Data Arrival Time	13.013
Data Required Time	25.548
From	uart_byte_rx/bps_cnt_5_s1
To	uart_byte_rx/data_byte_pre[2]_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R12C11[2][A]	uart_byte_rx/bps_cnt_5_s1/CLK
6.049	0.458	tC2Q	RF	12	R12C11[2][A]	uart_byte_rx/bps_cnt_5_s1/Q
7.210	1.160	tNET	FF	1	R14C11[2][B]	uart_byte_rx/bps_cnt_7_s7/I3
8.309	1.099	tINS	FF	2	R14C11[2][B]	uart_byte_rx/bps_cnt_7_s7/F
8.320	0.011	tNET	FF	1	R14C11[1][A]	uart_byte_rx/START_BIT_2_s3/I3
9.352	1.032	tINS	FF	10	R14C11[1][A]	uart_byte_rx/START_BIT_2_s3/F
11.163	1.811	tNET	FF	1	R11C8[2][A]	uart_byte_rx/data_byte_pre[2]_2_s2/I1
12.224	1.061	tINS	FR	3	R11C8[2][A]	uart_byte_rx/data_byte_pre[2]_2_s2/F
13.013	0.788	tNET	RR	1	R9C7[2][B]	uart_byte_rx/data_byte_pre[2]_2_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R9C7[2][B]	uart_byte_rx/data_byte_pre[2]_2_s0/CLK
25.548	-0.043	tSu		1	R9C7[2][B]	uart_byte_rx/data_byte_pre[2]_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.192, 43.011%; route: 3.771, 50.814%; tC2Q: 0.458, 6.176%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path8

Path Summary:

Slack	12.535
Data Arrival Time	13.013
Data Required Time	25.548
From	uart_byte_rx/bps_cnt_5_s1
To	uart_byte_rx/data_byte_pre[2]_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R12C11[2][A]	uart_byte_rx/bps_cnt_5_s1/CLK
6.049	0.458	tC2Q	RF	12	R12C11[2][A]	uart_byte_rx/bps_cnt_5_s1/Q
7.210	1.160	tNET	FF	1	R14C11[2][B]	uart_byte_rx/bps_cnt_7_s7/I3
8.309	1.099	tINS	FF	2	R14C11[2][B]	uart_byte_rx/bps_cnt_7_s7/F
8.320	0.011	tNET	FF	1	R14C11[1][A]	uart_byte_rx/START_BIT_2_s3/I3
9.352	1.032	tINS	FF	10	R14C11[1][A]	uart_byte_rx/START_BIT_2_s3/F
11.163	1.811	tNET	FF	1	R11C8[2][A]	uart_byte_rx/data_byte_pre[2]_2_s2/I1
12.224	1.061	tINS	FR	3	R11C8[2][A]	uart_byte_rx/data_byte_pre[2]_2_s2/F
13.013	0.788	tNET	RR	1	R9C9[2][A]	uart_byte_rx/data_byte_pre[2]_0_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R9C9[2][A]	uart_byte_rx/data_byte_pre[2]_0_s0/CLK
25.548	-0.043	tSu		1	R9C9[2][A]	uart_byte_rx/data_byte_pre[2]_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.192, 43.011%; route: 3.771, 50.814%; tC2Q: 0.458, 6.176%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path9

Path Summary:

Slack	12.618
Data Arrival Time	12.930
Data Required Time	25.548
From	uart_byte_rx/bps_cnt_5_s1
To	uart_byte_rx/data_byte_pre[2]_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R12C11[2][A]	uart_byte_rx/bps_cnt_5_s1/CLK
6.049	0.458	tC2Q	RF	12	R12C11[2][A]	uart_byte_rx/bps_cnt_5_s1/Q
7.210	1.160	tNET	FF	1	R14C11[2][B]	uart_byte_rx/bps_cnt_7_s7/I3
8.309	1.099	tINS	FF	2	R14C11[2][B]	uart_byte_rx/bps_cnt_7_s7/F
8.320	0.011	tNET	FF	1	R14C11[1][A]	uart_byte_rx/START_BIT_2_s3/I3
9.352	1.032	tINS	FF	10	R14C11[1][A]	uart_byte_rx/START_BIT_2_s3/F
11.163	1.811	tNET	FF	1	R11C8[2][A]	uart_byte_rx/data_byte_pre[2]_2_s2/I1
12.224	1.061	tINS	FR	3	R11C8[2][A]	uart_byte_rx/data_byte_pre[2]_2_s2/F
12.930	0.706	tNET	RR	1	R9C8[0][A]	uart_byte_rx/data_byte_pre[2]_1_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R9C8[0][A]	uart_byte_rx/data_byte_pre[2]_1_s0/CLK
25.548	-0.043	tSu		1	R9C8[0][A]	uart_byte_rx/data_byte_pre[2]_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.192, 43.495%; route: 3.688, 50.260%; tC2Q: 0.458, 6.245%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path10

Path Summary:

Slack	12.627
Data Arrival Time	12.921
Data Required Time	25.548
From	uart_byte_rx/bps_cnt_3_s1
To	uart_byte_rx/data_byte_pre[6]_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R11C12[1][A]	uart_byte_rx/bps_cnt_3_s1/CLK
6.049	0.458	tC2Q	RF	7	R11C12[1][A]	uart_byte_rx/bps_cnt_3_s1/Q
7.374	1.325	tNET	FF	1	R13C10[2][B]	uart_byte_rx/START_BIT_2_s5/I1
8.473	1.099	tINS	FF	9	R13C10[2][B]	uart_byte_rx/START_BIT_2_s5/F
9.322	0.849	tNET	FF	1	R12C12[0][A]	uart_byte_rx/data_byte_pre[6]_2_s3/I1
9.947	0.625	tINS	FR	4	R12C12[0][A]	uart_byte_rx/data_byte_pre[6]_2_s3/F
10.371	0.425	tNET	RR	1	R13C12[2][A]	uart_byte_rx/data_byte_pre[6]_2_s2/I0
11.397	1.026	tINS	RR	3	R13C12[2][A]	uart_byte_rx/data_byte_pre[6]_2_s2/F
12.921	1.524	tNET	RR	1	R13C12[2][B]	uart_byte_rx/data_byte_pre[6]_0_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R13C12[2][B]	uart_byte_rx/data_byte_pre[6]_0_s0/CLK
25.548	-0.043	tSu		1	R13C12[2][B]	uart_byte_rx/data_byte_pre[6]_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 2.750, 37.518%; route: 4.121, 56.229%; tC2Q: 0.458, 6.253%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path11

Path Summary:

Slack	12.900
Data Arrival Time	12.291
Data Required Time	25.191
From	uart_byte_rx/bps_cnt_3_s1
To	uart_byte_rx/data_byte_pre[7]_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R11C12[1][A]	uart_byte_rx/bps_cnt_3_s1/CLK
6.049	0.458	tC2Q	RF	7	R11C12[1][A]	uart_byte_rx/bps_cnt_3_s1/Q
7.374	1.325	tNET	FF	1	R13C10[2][B]	uart_byte_rx/START_BIT_2_s5/I1
8.435	1.061	tINS	FR	9	R13C10[2][B]	uart_byte_rx/START_BIT_2_s5/F
8.865	0.431	tNET	RR	1	R13C11[2][A]	uart_byte_rx/data_byte_pre[7]_2_s3/I1
9.964	1.099	tINS	RF	4	R13C11[2][A]	uart_byte_rx/data_byte_pre[7]_2_s3/F
11.259	1.294	tNET	FF	1	R13C9[2][A]	uart_byte_rx/n520_s6/I3
12.291	1.032	tINS	FF	1	R13C9[2][A]	uart_byte_rx/n520_s6/F
12.291	0.000	tNET	FF	1	R13C9[2][A]	uart_byte_rx/data_byte_pre[7]_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R13C9[2][A]	uart_byte_rx/data_byte_pre[7]_1_s0/CLK
25.191	-0.400	tSu		1	R13C9[2][A]	uart_byte_rx/data_byte_pre[7]_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.192, 47.644%; route: 3.049, 45.515%; tC2Q: 0.458, 6.841%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path12

Path Summary:

Slack	12.921
Data Arrival Time	12.270
Data Required Time	25.191
From	uart_byte_rx/bps_cnt_3_s1
To	uart_byte_rx/data_byte_pre[1]_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R11C12[1][A]	uart_byte_rx/bps_cnt_3_s1/CLK
6.049	0.458	tC2Q	RF	7	R11C12[1][A]	uart_byte_rx/bps_cnt_3_s1/Q
7.374	1.325	tNET	FF	1	R13C10[2][B]	uart_byte_rx/START_BIT_2_s5/I1
8.473	1.099	tINS	FF	9	R13C10[2][B]	uart_byte_rx/START_BIT_2_s5/F
9.322	0.849	tNET	FF	1	R12C11[1][A]	uart_byte_rx/data_byte_pre[1]_2_s3/I1
10.144	0.822	tINS	FF	4	R12C11[1][A]	uart_byte_rx/data_byte_pre[1]_2_s3/F
11.448	1.305	tNET	FF	1	R9C9[0][A]	uart_byte_rx/n577_s5/I2
12.270	0.822	tINS	FF	1	R9C9[0][A]	uart_byte_rx/n577_s5/F
12.270	0.000	tNET	FF	1	R9C9[0][A]	uart_byte_rx/data_byte_pre[1]_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R9C9[0][A]	uart_byte_rx/data_byte_pre[1]_0_s0/CLK
25.191	-0.400	tSu		1	R9C9[0][A]	uart_byte_rx/data_byte_pre[1]_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 2.743, 41.068%; route: 3.478, 52.070%; tC2Q: 0.458, 6.862%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path13

Path Summary:

Slack	12.921
Data Arrival Time	12.270
Data Required Time	25.191
From	uart_byte_rx/bps_cnt_3_s1
To	uart_byte_rx/data_byte_pre[1]_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R11C12[1][A]	uart_byte_rx/bps_cnt_3_s1/CLK
6.049	0.458	tC2Q	RF	7	R11C12[1][A]	uart_byte_rx/bps_cnt_3_s1/Q
7.374	1.325	tNET	FF	1	R13C10[2][B]	uart_byte_rx/START_BIT_2_s5/I1
8.473	1.099	tINS	FF	9	R13C10[2][B]	uart_byte_rx/START_BIT_2_s5/F
9.322	0.849	tNET	FF	1	R12C11[1][A]	uart_byte_rx/data_byte_pre[1]_2_s3/I1
10.144	0.822	tINS	FF	4	R12C11[1][A]	uart_byte_rx/data_byte_pre[1]_2_s3/F
11.448	1.305	tNET	FF	1	R9C9[1][A]	uart_byte_rx/n574_s6/I3
12.270	0.822	tINS	FF	1	R9C9[1][A]	uart_byte_rx/n574_s6/F
12.270	0.000	tNET	FF	1	R9C9[1][A]	uart_byte_rx/data_byte_pre[1]_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R9C9[1][A]	uart_byte_rx/data_byte_pre[1]_1_s0/CLK
25.191	-0.400	tSu		1	R9C9[1][A]	uart_byte_rx/data_byte_pre[1]_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 2.743, 41.068%; route: 3.478, 52.070%; tC2Q: 0.458, 6.862%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path14

Path Summary:

Slack	12.944
Data Arrival Time	12.247
Data Required Time	25.191
From	uart_byte_rx/bps_cnt_6_s1
To	uart_byte_rx/data_byte_pre[2]_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R12C12[1][B]	uart_byte_rx/bps_cnt_6_s1/CLK
6.049	0.458	tC2Q	RF	11	R12C12[1][B]	uart_byte_rx/bps_cnt_6_s1/Q
6.885	0.835	tNET	FF	1	R13C11[1][B]	uart_byte_rx/bps_cnt_7_s6/I0
7.984	1.099	tINS	FF	5	R13C11[1][B]	uart_byte_rx/bps_cnt_7_s6/F
8.804	0.821	tNET	FF	1	R12C10[1][B]	uart_byte_rx/data_byte_pre[2]_2_s4/I1
9.836	1.032	tINS	FF	4	R12C10[1][B]	uart_byte_rx/data_byte_pre[2]_2_s4/F
11.621	1.784	tNET	FF	1	R9C7[2][B]	uart_byte_rx/n562_s5/I3
12.247	0.626	tINS	FF	1	R9C7[2][B]	uart_byte_rx/n562_s5/F
12.247	0.000	tNET	FF	1	R9C7[2][B]	uart_byte_rx/data_byte_pre[2]_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R9C7[2][B]	uart_byte_rx/data_byte_pre[2]_2_s0/CLK
25.191	-0.400	tSu		1	R9C7[2][B]	uart_byte_rx/data_byte_pre[2]_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 2.757, 41.423%; route: 3.440, 51.691%; tC2Q: 0.458, 6.886%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path15

Path Summary:

Slack	12.944
Data Arrival Time	12.247
Data Required Time	25.191
From	uart_byte_rx/bps_cnt_6_s1
To	uart_byte_rx/data_byte_pre[2]_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R12C12[1][B]	uart_byte_rx/bps_cnt_6_s1/CLK
6.049	0.458	tC2Q	RF	11	R12C12[1][B]	uart_byte_rx/bps_cnt_6_s1/Q
6.885	0.835	tNET	FF	1	R13C11[1][B]	uart_byte_rx/bps_cnt_7_s6/I0
7.984	1.099	tINS	FF	5	R13C11[1][B]	uart_byte_rx/bps_cnt_7_s6/F
8.804	0.821	tNET	FF	1	R12C10[1][B]	uart_byte_rx/data_byte_pre[2]_2_s4/I1
9.836	1.032	tINS	FF	4	R12C10[1][B]	uart_byte_rx/data_byte_pre[2]_2_s4/F
11.148	1.311	tNET	FF	1	R9C8[0][A]	uart_byte_rx/n565_s6/I3
12.247	1.099	tINS	FF	1	R9C8[0][A]	uart_byte_rx/n565_s6/F
12.247	0.000	tNET	FF	1	R9C8[0][A]	uart_byte_rx/data_byte_pre[2]_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R9C8[0][A]	uart_byte_rx/data_byte_pre[2]_1_s0/CLK
25.191	-0.400	tSu		1	R9C8[0][A]	uart_byte_rx/data_byte_pre[2]_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.230, 48.531%; route: 2.967, 44.583%; tC2Q: 0.458, 6.886%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path16

Path Summary:

Slack	13.022
Data Arrival Time	12.170
Data Required Time	25.191
From	uart_byte_tx/div_cnt_6_s0
To	uart_byte_tx/div_cnt_14_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R8C10[0][B]	uart_byte_tx/div_cnt_6_s0/CLK
6.049	0.458	tC2Q	RF	4	R8C10[0][B]	uart_byte_tx/div_cnt_6_s0/Q
7.345	1.296	tNET	FF	1	R7C7[3][A]	uart_byte_tx/n123_s5/I2
8.377	1.032	tINS	FF	5	R7C7[3][A]	uart_byte_tx/n123_s5/F
9.208	0.831	tNET	FF	1	R8C9[1][B]	uart_byte_tx/n117_s3/I0
10.307	1.099	tINS	FF	5	R8C9[1][B]	uart_byte_tx/n117_s3/F
11.138	0.830	tNET	FF	1	R7C8[1][A]	uart_byte_tx/n111_s2/I0
12.170	1.032	tINS	FF	1	R7C8[1][A]	uart_byte_tx/n111_s2/F
12.170	0.000	tNET	FF	1	R7C8[1][A]	uart_byte_tx/div_cnt_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R7C8[1][A]	uart_byte_tx/div_cnt_14_s0/CLK
25.191	-0.400	tSu		1	R7C8[1][A]	uart_byte_tx/div_cnt_14_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.163, 48.081%; route: 2.957, 44.952%; tC2Q: 0.458, 6.967%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path17

Path Summary:

Slack	13.022
Data Arrival Time	12.170
Data Required Time	25.191
From	uart_byte_tx/div_cnt_6_s0
To	uart_byte_tx/div_cnt_12_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R8C10[0][B]	uart_byte_tx/div_cnt_6_s0/CLK
6.049	0.458	tC2Q	RF	4	R8C10[0][B]	uart_byte_tx/div_cnt_6_s0/Q
7.345	1.296	tNET	FF	1	R7C7[3][A]	uart_byte_tx/n123_s5/I2
8.377	1.032	tINS	FF	5	R7C7[3][A]	uart_byte_tx/n123_s5/F
9.208	0.831	tNET	FF	1	R8C9[1][B]	uart_byte_tx/n117_s3/I0
10.307	1.099	tINS	FF	5	R8C9[1][B]	uart_byte_tx/n117_s3/F
11.138	0.830	tNET	FF	1	R7C8[1][B]	uart_byte_tx/n113_s2/I0
12.170	1.032	tINS	FF	1	R7C8[1][B]	uart_byte_tx/n113_s2/F
12.170	0.000	tNET	FF	1	R7C8[1][B]	uart_byte_tx/div_cnt_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R7C8[1][B]	uart_byte_tx/div_cnt_12_s0/CLK
25.191	-0.400	tSu		1	R7C8[1][B]	uart_byte_tx/div_cnt_12_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.163, 48.081%; route: 2.957, 44.952%; tC2Q: 0.458, 6.967%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path18

Path Summary:

Slack	13.023
Data Arrival Time	12.168
Data Required Time	25.191
From	uart_byte_rx/bps_cnt_6_s1
To	uart_byte_rx/data_byte_pre[2]_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R12C12[1][B]	uart_byte_rx/bps_cnt_6_s1/CLK
6.049	0.458	tC2Q	RF	11	R12C12[1][B]	uart_byte_rx/bps_cnt_6_s1/Q
6.885	0.835	tNET	FF	1	R13C11[1][B]	uart_byte_rx/bps_cnt_7_s6/I0
7.984	1.099	tINS	FF	5	R13C11[1][B]	uart_byte_rx/bps_cnt_7_s6/F
8.804	0.821	tNET	FF	1	R12C10[1][B]	uart_byte_rx/data_byte_pre[2]_2_s4/I1
9.836	1.032	tINS	FF	4	R12C10[1][B]	uart_byte_rx/data_byte_pre[2]_2_s4/F
11.136	1.300	tNET	FF	1	R9C9[2][A]	uart_byte_rx/n568_s5/I2
12.168	1.032	tINS	FF	1	R9C9[2][A]	uart_byte_rx/n568_s5/F
12.168	0.000	tNET	FF	1	R9C9[2][A]	uart_byte_rx/data_byte_pre[2]_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R9C9[2][A]	uart_byte_rx/data_byte_pre[2]_0_s0/CLK
25.191	-0.400	tSu		1	R9C9[2][A]	uart_byte_rx/data_byte_pre[2]_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.163, 48.090%; route: 2.956, 44.941%; tC2Q: 0.458, 6.968%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path19

Path Summary:

Slack	13.028
Data Arrival Time	12.520
Data Required Time	25.548
From	uart_byte_rx/bps_cnt_3_s1
To	uart_byte_rx/data_byte_pre[6]_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R11C12[1][A]	uart_byte_rx/bps_cnt_3_s1/CLK
6.049	0.458	tC2Q	RF	7	R11C12[1][A]	uart_byte_rx/bps_cnt_3_s1/Q
7.374	1.325	tNET	FF	1	R13C10[2][B]	uart_byte_rx/START_BIT_2_s5/I1
8.473	1.099	tINS	FF	9	R13C10[2][B]	uart_byte_rx/START_BIT_2_s5/F
9.322	0.849	tNET	FF	1	R12C12[0][A]	uart_byte_rx/data_byte_pre[6]_2_s3/I1
9.947	0.625	tINS	FR	4	R12C12[0][A]	uart_byte_rx/data_byte_pre[6]_2_s3/F
10.371	0.425	tNET	RR	1	R13C12[2][A]	uart_byte_rx/data_byte_pre[6]_2_s2/I0
11.397	1.026	tINS	RR	3	R13C12[2][A]	uart_byte_rx/data_byte_pre[6]_2_s2/F
12.520	1.123	tNET	RR	1	R14C12[0][B]	uart_byte_rx/data_byte_pre[6]_1_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R14C12[0][B]	uart_byte_rx/data_byte_pre[6]_1_s0/CLK
25.548	-0.043	tSu		1	R14C12[0][B]	uart_byte_rx/data_byte_pre[6]_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 2.750, 39.689%; route: 3.721, 53.697%; tC2Q: 0.458, 6.615%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path20

Path Summary:

Slack	13.028
Data Arrival Time	12.520
Data Required Time	25.548
From	uart_byte_rx/bps_cnt_3_s1
To	uart_byte_rx/data_byte_pre[6]_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R11C12[1][A]	uart_byte_rx/bps_cnt_3_s1/CLK
6.049	0.458	tC2Q	RF	7	R11C12[1][A]	uart_byte_rx/bps_cnt_3_s1/Q
7.374	1.325	tNET	FF	1	R13C10[2][B]	uart_byte_rx/START_BIT_2_s5/I1
8.473	1.099	tINS	FF	9	R13C10[2][B]	uart_byte_rx/START_BIT_2_s5/F
9.322	0.849	tNET	FF	1	R12C12[0][A]	uart_byte_rx/data_byte_pre[6]_2_s3/I1
9.947	0.625	tINS	FR	4	R12C12[0][A]	uart_byte_rx/data_byte_pre[6]_2_s3/F
10.371	0.425	tNET	RR	1	R13C12[2][A]	uart_byte_rx/data_byte_pre[6]_2_s2/I0
11.397	1.026	tINS	RR	3	R13C12[2][A]	uart_byte_rx/data_byte_pre[6]_2_s2/F
12.520	1.123	tNET	RR	1	R14C12[0][A]	uart_byte_rx/data_byte_pre[6]_2_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R14C12[0][A]	uart_byte_rx/data_byte_pre[6]_2_s0/CLK
25.548	-0.043	tSu		1	R14C12[0][A]	uart_byte_rx/data_byte_pre[6]_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 2.750, 39.689%; route: 3.721, 53.697%; tC2Q: 0.458, 6.615%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path21

Path Summary:

Slack	13.047
Data Arrival Time	12.145
Data Required Time	25.191
From	uart_byte_tx/data_byte_reg_4_s0
To	uart_byte_tx/uart_tx_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R8C9[1][A]	uart_byte_tx/data_byte_reg_4_s0/CLK
6.049	0.458	tC2Q	RR	1	R8C9[1][A]	uart_byte_tx/data_byte_reg_4_s0/Q
6.468	0.419	tNET	RR	1	R8C8[3][B]	uart_byte_tx/n177_s34/I0
7.529	1.061	tINS	RR	1	R8C8[3][B]	uart_byte_tx/n177_s34/F
7.529	0.000	tNET	RR	1	R8C8[3][A]	uart_byte_tx/n177_s22/I1
7.679	0.150	tINS	RR	1	R8C8[3][A]	uart_byte_tx/n177_s22/O
8.105	0.426	tNET	RR	1	R8C9[3][A]	uart_byte_tx/n177_s35/I0
9.204	1.099	tINS	RF	1	R8C9[3][A]	uart_byte_tx/n177_s35/F
9.204	0.000	tNET	FF	1	R8C9[3][A]	uart_byte_tx/n177_s26/I0
9.353	0.149	tINS	FF	1	R8C9[3][A]	uart_byte_tx/n177_s26/O
9.853	0.500	tNET	FF	1	R8C11[3][A]	uart_byte_tx/n177_s28/I2
10.675	0.822	tINS	FF	1	R8C11[3][A]	uart_byte_tx/n177_s28/F
12.145	1.470	tNET	FF	1	IOT13[B]	uart_byte_tx/uart_tx_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	IOT13[B]	uart_byte_tx/uart_tx_s0/CLK
25.191	-0.400	tSu		1	IOT13[B]	uart_byte_tx/uart_tx_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.281, 50.066%; route: 2.814, 42.940%; tC2Q: 0.458, 6.994%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path22

Path Summary:

Slack	13.097
Data Arrival Time	12.094
Data Required Time	25.191
From	uart_byte_tx/div_cnt_6_s0
To	uart_byte_tx/div_cnt_10_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R8C10[0][B]	uart_byte_tx/div_cnt_6_s0/CLK
6.049	0.458	tC2Q	RF	4	R8C10[0][B]	uart_byte_tx/div_cnt_6_s0/Q
7.345	1.296	tNET	FF	1	R7C7[3][A]	uart_byte_tx/n123_s5/I2
8.377	1.032	tINS	FF	5	R7C7[3][A]	uart_byte_tx/n123_s5/F
9.208	0.831	tNET	FF	1	R8C9[1][B]	uart_byte_tx/n117_s3/I0
10.307	1.099	tINS	FF	5	R8C9[1][B]	uart_byte_tx/n117_s3/F
11.468	1.161	tNET	FF	1	R7C8[2][A]	uart_byte_tx/n115_s2/I0
12.094	0.626	tINS	FF	1	R7C8[2][A]	uart_byte_tx/n115_s2/F
12.094	0.000	tNET	FF	1	R7C8[2][A]	uart_byte_tx/div_cnt_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R7C8[2][A]	uart_byte_tx/div_cnt_10_s0/CLK
25.191	-0.400	tSu		1	R7C8[2][A]	uart_byte_tx/div_cnt_10_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 2.757, 42.394%; route: 3.288, 50.558%; tC2Q: 0.458, 7.048%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path23

Path Summary:

Slack	13.117
Data Arrival Time	12.074
Data Required Time	25.191
From	uart_byte_rx/bps_cnt_3_s1
To	uart_byte_rx/data_byte_pre[1]_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R11C12[1][A]	uart_byte_rx/bps_cnt_3_s1/CLK
6.049	0.458	tC2Q	RF	7	R11C12[1][A]	uart_byte_rx/bps_cnt_3_s1/Q
7.374	1.325	tNET	FF	1	R13C10[2][B]	uart_byte_rx/START_BIT_2_s5/I1
8.473	1.099	tINS	FF	9	R13C10[2][B]	uart_byte_rx/START_BIT_2_s5/F
9.322	0.849	tNET	FF	1	R12C11[1][A]	uart_byte_rx/data_byte_pre[1]_2_s3/I1
10.144	0.822	tINS	FF	4	R12C11[1][A]	uart_byte_rx/data_byte_pre[1]_2_s3/F
11.448	1.305	tNET	FF	1	R9C9[0][B]	uart_byte_rx/n571_s5/I3
12.074	0.626	tINS	FF	1	R9C9[0][B]	uart_byte_rx/n571_s5/F
12.074	0.000	tNET	FF	1	R9C9[0][B]	uart_byte_rx/data_byte_pre[1]_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R9C9[0][B]	uart_byte_rx/data_byte_pre[1]_2_s0/CLK
25.191	-0.400	tSu		1	R9C9[0][B]	uart_byte_rx/data_byte_pre[1]_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 2.547, 39.286%; route: 3.478, 53.644%; tC2Q: 0.458, 7.070%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path24

Path Summary:

Slack	13.137
Data Arrival Time	12.411
Data Required Time	25.548
From	uart_byte_rx/bps_cnt_5_s1
To	uart_byte_rx/data_byte_pre[1]_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R12C11[2][A]	uart_byte_rx/bps_cnt_5_s1/CLK
6.049	0.458	tC2Q	RF	12	R12C11[2][A]	uart_byte_rx/bps_cnt_5_s1/Q
7.210	1.160	tNET	FF	1	R14C11[2][B]	uart_byte_rx/bps_cnt_7_s7/I3
8.309	1.099	tINS	FF	2	R14C11[2][B]	uart_byte_rx/bps_cnt_7_s7/F
8.320	0.011	tNET	FF	1	R14C11[1][A]	uart_byte_rx/START_BIT_2_s3/I3
9.352	1.032	tINS	FF	10	R14C11[1][A]	uart_byte_rx/START_BIT_2_s3/F
10.674	1.322	tNET	FF	1	R11C9[3][B]	uart_byte_rx/data_byte_pre[1]_2_s2/I1
11.700	1.026	tINS	FR	3	R11C9[3][B]	uart_byte_rx/data_byte_pre[1]_2_s2/F
12.411	0.711	tNET	RR	1	R9C9[0][B]	uart_byte_rx/data_byte_pre[1]_2_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R9C9[0][B]	uart_byte_rx/data_byte_pre[1]_2_s0/CLK
25.548	-0.043	tSu		1	R9C9[0][B]	uart_byte_rx/data_byte_pre[1]_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.157, 46.290%; route: 3.205, 46.990%; tC2Q: 0.458, 6.720%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path25

Path Summary:

Slack	13.137
Data Arrival Time	12.411
Data Required Time	25.548
From	uart_byte_rx/bps_cnt_5_s1
To	uart_byte_rx/data_byte_pre[1]_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R12C11[2][A]	uart_byte_rx/bps_cnt_5_s1/CLK
6.049	0.458	tC2Q	RF	12	R12C11[2][A]	uart_byte_rx/bps_cnt_5_s1/Q
7.210	1.160	tNET	FF	1	R14C11[2][B]	uart_byte_rx/bps_cnt_7_s7/I3
8.309	1.099	tINS	FF	2	R14C11[2][B]	uart_byte_rx/bps_cnt_7_s7/F
8.320	0.011	tNET	FF	1	R14C11[1][A]	uart_byte_rx/START_BIT_2_s3/I3
9.352	1.032	tINS	FF	10	R14C11[1][A]	uart_byte_rx/START_BIT_2_s3/F
10.674	1.322	tNET	FF	1	R11C9[3][B]	uart_byte_rx/data_byte_pre[1]_2_s2/I1
11.700	1.026	tINS	FR	3	R11C9[3][B]	uart_byte_rx/data_byte_pre[1]_2_s2/F
12.411	0.711	tNET	RR	1	R9C9[1][A]	uart_byte_rx/data_byte_pre[1]_1_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R9C9[1][A]	uart_byte_rx/data_byte_pre[1]_1_s0/CLK
25.548	-0.043	tSu		1	R9C9[1][A]	uart_byte_rx/data_byte_pre[1]_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.157, 46.290%; route: 3.205, 46.990%; tC2Q: 0.458, 6.720%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.562
Data Arrival Time	4.667
Data Required Time	4.105
From	send_en_s0
To	uart_byte_tx/data_byte_reg_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C7[0][A]	send_en_s0/CLK
4.426	0.333	tC2Q	RR	10	R8C7[0][A]	send_en_s0/Q
4.667	0.241	tNET	RR	1	R8C7[2][A]	uart_byte_tx/data_byte_reg_2_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C7[2][A]	uart_byte_tx/data_byte_reg_2_s0/CLK
4.105	0.012	tHld		1	R8C7[2][A]	uart_byte_tx/data_byte_reg_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.241, 41.973%; tC2Q: 0.333, 58.027%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path2

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	uart_byte_rx/STOP_BIT_2_s0
To	uart_byte_rx/STOP_BIT_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R11C10[0][A]	uart_byte_rx/STOP_BIT_2_s0/CLK
4.426	0.333	tC2Q	RR	2	R11C10[0][A]	uart_byte_rx/STOP_BIT_2_s0/Q
4.428	0.002	tNET	RR	1	R11C10[0][A]	uart_byte_rx/n589_s5/I2
4.800	0.372	tINS	RF	1	R11C10[0][A]	uart_byte_rx/n589_s5/F
4.800	0.000	tNET	FF	1	R11C10[0][A]	uart_byte_rx/STOP_BIT_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R11C10[0][A]	uart_byte_rx/STOP_BIT_2_s0/CLK
4.093	0.000	tHld		1	R11C10[0][A]	uart_byte_rx/STOP_BIT_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path3

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	uart_byte_rx/data_byte_pre[0]_2_s0
To	uart_byte_rx/data_byte_pre[0]_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R13C9[0][A]	uart_byte_rx/data_byte_pre[0]_2_s0/CLK
4.426	0.333	tC2Q	RR	2	R13C9[0][A]	uart_byte_rx/data_byte_pre[0]_2_s0/Q
4.428	0.002	tNET	RR	1	R13C9[0][A]	uart_byte_rx/n580_s5/I2
4.800	0.372	tINS	RF	1	R13C9[0][A]	uart_byte_rx/n580_s5/F
4.800	0.000	tNET	FF	1	R13C9[0][A]	uart_byte_rx/data_byte_pre[0]_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R13C9[0][A]	uart_byte_rx/data_byte_pre[0]_2_s0/CLK
4.093	0.000	tHld		1	R13C9[0][A]	uart_byte_rx/data_byte_pre[0]_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path4

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	uart_byte_rx/data_byte_pre[1]_0_s0
To	uart_byte_rx/data_byte_pre[1]_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R9C9[0][A]	uart_byte_rx/data_byte_pre[1]_0_s0/CLK
4.426	0.333	tC2Q	RR	3	R9C9[0][A]	uart_byte_rx/data_byte_pre[1]_0_s0/Q
4.428	0.002	tNET	RR	1	R9C9[0][A]	uart_byte_rx/n577_s5/I1
4.800	0.372	tINS	RF	1	R9C9[0][A]	uart_byte_rx/n577_s5/F
4.800	0.000	tNET	FF	1	R9C9[0][A]	uart_byte_rx/data_byte_pre[1]_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R9C9[0][A]	uart_byte_rx/data_byte_pre[1]_0_s0/CLK
4.093	0.000	tHld		1	R9C9[0][A]	uart_byte_rx/data_byte_pre[1]_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path5

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	uart_byte_rx/data_byte_pre[1]_1_s0
To	uart_byte_rx/data_byte_pre[1]_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R9C9[1][A]	uart_byte_rx/data_byte_pre[1]_1_s0/CLK
4.426	0.333	tC2Q	RR	2	R9C9[1][A]	uart_byte_rx/data_byte_pre[1]_1_s0/Q
4.428	0.002	tNET	RR	1	R9C9[1][A]	uart_byte_rx/n574_s6/I0
4.800	0.372	tINS	RF	1	R9C9[1][A]	uart_byte_rx/n574_s6/F
4.800	0.000	tNET	FF	1	R9C9[1][A]	uart_byte_rx/data_byte_pre[1]_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R9C9[1][A]	uart_byte_rx/data_byte_pre[1]_1_s0/CLK
4.093	0.000	tHld		1	R9C9[1][A]	uart_byte_rx/data_byte_pre[1]_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path6

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	uart_byte_rx/data_byte_pre[2]_1_s0
To	uart_byte_rx/data_byte_pre[2]_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R9C8[0][A]	uart_byte_rx/data_byte_pre[2]_1_s0/CLK
4.426	0.333	tC2Q	RR	2	R9C8[0][A]	uart_byte_rx/data_byte_pre[2]_1_s0/Q
4.428	0.002	tNET	RR	1	R9C8[0][A]	uart_byte_rx/n565_s6/I0
4.800	0.372	tINS	RF	1	R9C8[0][A]	uart_byte_rx/n565_s6/F
4.800	0.000	tNET	FF	1	R9C8[0][A]	uart_byte_rx/data_byte_pre[2]_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R9C8[0][A]	uart_byte_rx/data_byte_pre[2]_1_s0/CLK
4.093	0.000	tHld		1	R9C8[0][A]	uart_byte_rx/data_byte_pre[2]_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path7

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	uart_byte_rx/data_byte_pre[3]_0_s0
To	uart_byte_rx/data_byte_pre[3]_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R13C12[0][A]	uart_byte_rx/data_byte_pre[3]_0_s0/CLK
4.426	0.333	tC2Q	RR	3	R13C12[0][A]	uart_byte_rx/data_byte_pre[3]_0_s0/Q
4.428	0.002	tNET	RR	1	R13C12[0][A]	uart_byte_rx/n559_s5/I1
4.800	0.372	tINS	RF	1	R13C12[0][A]	uart_byte_rx/n559_s5/F
4.800	0.000	tNET	FF	1	R13C12[0][A]	uart_byte_rx/data_byte_pre[3]_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R13C12[0][A]	uart_byte_rx/data_byte_pre[3]_0_s0/CLK
4.093	0.000	tHld		1	R13C12[0][A]	uart_byte_rx/data_byte_pre[3]_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path8

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	uart_byte_rx/data_byte_pre[3]_1_s0
To	uart_byte_rx/data_byte_pre[3]_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R13C12[1][A]	uart_byte_rx/data_byte_pre[3]_1_s0/CLK
4.426	0.333	tC2Q	RR	2	R13C12[1][A]	uart_byte_rx/data_byte_pre[3]_1_s0/Q
4.428	0.002	tNET	RR	1	R13C12[1][A]	uart_byte_rx/n556_s6/I0
4.800	0.372	tINS	RF	1	R13C12[1][A]	uart_byte_rx/n556_s6/F
4.800	0.000	tNET	FF	1	R13C12[1][A]	uart_byte_rx/data_byte_pre[3]_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R13C12[1][A]	uart_byte_rx/data_byte_pre[3]_1_s0/CLK
4.093	0.000	tHld		1	R13C12[1][A]	uart_byte_rx/data_byte_pre[3]_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path9

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	uart_byte_rx/data_byte_pre[4]_0_s0
To	uart_byte_rx/data_byte_pre[4]_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R14C10[0][A]	uart_byte_rx/data_byte_pre[4]_0_s0/CLK
4.426	0.333	tC2Q	RR	3	R14C10[0][A]	uart_byte_rx/data_byte_pre[4]_0_s0/Q
4.428	0.002	tNET	RR	1	R14C10[0][A]	uart_byte_rx/n550_s5/I1
4.800	0.372	tINS	RF	1	R14C10[0][A]	uart_byte_rx/n550_s5/F
4.800	0.000	tNET	FF	1	R14C10[0][A]	uart_byte_rx/data_byte_pre[4]_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R14C10[0][A]	uart_byte_rx/data_byte_pre[4]_0_s0/CLK
4.093	0.000	tHld		1	R14C10[0][A]	uart_byte_rx/data_byte_pre[4]_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path10

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	uart_byte_rx/data_byte_pre[4]_1_s0
To	uart_byte_rx/data_byte_pre[4]_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R14C10[1][A]	uart_byte_rx/data_byte_pre[4]_1_s0/CLK
4.426	0.333	tC2Q	RR	2	R14C10[1][A]	uart_byte_rx/data_byte_pre[4]_1_s0/Q
4.428	0.002	tNET	RR	1	R14C10[1][A]	uart_byte_rx/n547_s6/I0
4.800	0.372	tINS	RF	1	R14C10[1][A]	uart_byte_rx/n547_s6/F
4.800	0.000	tNET	FF	1	R14C10[1][A]	uart_byte_rx/data_byte_pre[4]_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R14C10[1][A]	uart_byte_rx/data_byte_pre[4]_1_s0/CLK
4.093	0.000	tHld		1	R14C10[1][A]	uart_byte_rx/data_byte_pre[4]_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path11

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	uart_byte_rx/data_byte_pre[5]_0_s0
To	uart_byte_rx/data_byte_pre[5]_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R9C8[1][A]	uart_byte_rx/data_byte_pre[5]_0_s0/CLK
4.426	0.333	tC2Q	RR	3	R9C8[1][A]	uart_byte_rx/data_byte_pre[5]_0_s0/Q
4.428	0.002	tNET	RR	1	R9C8[1][A]	uart_byte_rx/n541_s5/I1
4.800	0.372	tINS	RF	1	R9C8[1][A]	uart_byte_rx/n541_s5/F
4.800	0.000	tNET	FF	1	R9C8[1][A]	uart_byte_rx/data_byte_pre[5]_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R9C8[1][A]	uart_byte_rx/data_byte_pre[5]_0_s0/CLK
4.093	0.000	tHld		1	R9C8[1][A]	uart_byte_rx/data_byte_pre[5]_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path12

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	uart_byte_rx/data_byte_pre[6]_2_s0
To	uart_byte_rx/data_byte_pre[6]_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R14C12[0][A]	uart_byte_rx/data_byte_pre[6]_2_s0/CLK
4.426	0.333	tC2Q	RR	2	R14C12[0][A]	uart_byte_rx/data_byte_pre[6]_2_s0/Q
4.428	0.002	tNET	RR	1	R14C12[0][A]	uart_byte_rx/n526_s5/I2
4.800	0.372	tINS	RF	1	R14C12[0][A]	uart_byte_rx/n526_s5/F
4.800	0.000	tNET	FF	1	R14C12[0][A]	uart_byte_rx/data_byte_pre[6]_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R14C12[0][A]	uart_byte_rx/data_byte_pre[6]_2_s0/CLK
4.093	0.000	tHld		1	R14C12[0][A]	uart_byte_rx/data_byte_pre[6]_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path13

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	uart_byte_rx/div_cnt_9_s0
To	uart_byte_rx/div_cnt_9_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R11C9[0][A]	uart_byte_rx/div_cnt_9_s0/CLK
4.426	0.333	tC2Q	RR	3	R11C9[0][A]	uart_byte_rx/div_cnt_9_s0/Q
4.428	0.002	tNET	RR	1	R11C9[0][A]	uart_byte_rx/n95_s2/I2
4.800	0.372	tINS	RF	1	R11C9[0][A]	uart_byte_rx/n95_s2/F
4.800	0.000	tNET	FF	1	R11C9[0][A]	uart_byte_rx/div_cnt_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R11C9[0][A]	uart_byte_rx/div_cnt_9_s0/CLK
4.093	0.000	tHld		1	R11C9[0][A]	uart_byte_rx/div_cnt_9_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path14

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	uart_byte_rx/div_cnt_12_s0
To	uart_byte_rx/div_cnt_12_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R11C8[1][A]	uart_byte_rx/div_cnt_12_s0/CLK
4.426	0.333	tC2Q	RR	5	R11C8[1][A]	uart_byte_rx/div_cnt_12_s0/Q
4.428	0.002	tNET	RR	1	R11C8[1][A]	uart_byte_rx/n92_s2/I2
4.800	0.372	tINS	RF	1	R11C8[1][A]	uart_byte_rx/n92_s2/F
4.800	0.000	tNET	FF	1	R11C8[1][A]	uart_byte_rx/div_cnt_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R11C8[1][A]	uart_byte_rx/div_cnt_12_s0/CLK
4.093	0.000	tHld		1	R11C8[1][A]	uart_byte_rx/div_cnt_12_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path15

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	uart_byte_rx/div_cnt_13_s0
To	uart_byte_rx/div_cnt_13_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R12C8[0][A]	uart_byte_rx/div_cnt_13_s0/CLK
4.426	0.333	tC2Q	RR	4	R12C8[0][A]	uart_byte_rx/div_cnt_13_s0/Q
4.428	0.002	tNET	RR	1	R12C8[0][A]	uart_byte_rx/n91_s2/I2
4.800	0.372	tINS	RF	1	R12C8[0][A]	uart_byte_rx/n91_s2/F
4.800	0.000	tNET	FF	1	R12C8[0][A]	uart_byte_rx/div_cnt_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R12C8[0][A]	uart_byte_rx/div_cnt_13_s0/CLK
4.093	0.000	tHld		1	R12C8[0][A]	uart_byte_rx/div_cnt_13_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path16

Path Summary:

Slack	0.709
Data Arrival Time	4.802
Data Required Time	4.093
From	uart_byte_rx/STOP_BIT_0_s0
To	uart_byte_rx/STOP_BIT_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R11C10[1][A]	uart_byte_rx/STOP_BIT_0_s0/CLK
4.426	0.333	tC2Q	RR	3	R11C10[1][A]	uart_byte_rx/STOP_BIT_0_s0/Q
4.430	0.004	tNET	RR	1	R11C10[1][A]	uart_byte_rx/n595_s5/I1
4.802	0.372	tINS	RF	1	R11C10[1][A]	uart_byte_rx/n595_s5/F
4.802	0.000	tNET	FF	1	R11C10[1][A]	uart_byte_rx/STOP_BIT_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R11C10[1][A]	uart_byte_rx/STOP_BIT_0_s0/CLK
4.093	0.000	tHld		1	R11C10[1][A]	uart_byte_rx/STOP_BIT_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path17

Path Summary:

Slack	0.709
Data Arrival Time	4.802
Data Required Time	4.093
From	uart_byte_rx/data_byte_pre[7]_0_s0
To	uart_byte_rx/data_byte_pre[7]_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R13C9[1][A]	uart_byte_rx/data_byte_pre[7]_0_s0/CLK
4.426	0.333	tC2Q	RR	3	R13C9[1][A]	uart_byte_rx/data_byte_pre[7]_0_s0/Q
4.430	0.004	tNET	RR	1	R13C9[1][A]	uart_byte_rx/n523_s5/I1
4.802	0.372	tINS	RF	1	R13C9[1][A]	uart_byte_rx/n523_s5/F
4.802	0.000	tNET	FF	1	R13C9[1][A]	uart_byte_rx/data_byte_pre[7]_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R13C9[1][A]	uart_byte_rx/data_byte_pre[7]_0_s0/CLK
4.093	0.000	tHld		1	R13C9[1][A]	uart_byte_rx/data_byte_pre[7]_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path18

Path Summary:

Slack	0.709
Data Arrival Time	4.802
Data Required Time	4.093
From	uart_byte_rx/div_cnt_8_s0
To	uart_byte_rx/div_cnt_8_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R11C8[0][A]	uart_byte_rx/div_cnt_8_s0/CLK
4.426	0.333	tC2Q	RR	4	R11C8[0][A]	uart_byte_rx/div_cnt_8_s0/Q
4.430	0.004	tNET	RR	1	R11C8[0][A]	uart_byte_rx/n96_s5/I0
4.802	0.372	tINS	RF	1	R11C8[0][A]	uart_byte_rx/n96_s5/F
4.802	0.000	tNET	FF	1	R11C8[0][A]	uart_byte_rx/div_cnt_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R11C8[0][A]	uart_byte_rx/div_cnt_8_s0/CLK
4.093	0.000	tHld		1	R11C8[0][A]	uart_byte_rx/div_cnt_8_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path19

Path Summary:

Slack	0.709
Data Arrival Time	4.802
Data Required Time	4.093
From	uart_byte_tx/bps_cnt_3_s1
To	uart_byte_tx/bps_cnt_3_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C11[0][A]	uart_byte_tx/bps_cnt_3_s1/CLK
4.426	0.333	tC2Q	RR	4	R8C11[0][A]	uart_byte_tx/bps_cnt_3_s1/Q
4.430	0.004	tNET	RR	1	R8C11[0][A]	uart_byte_tx/n157_s2/I3
4.802	0.372	tINS	RF	1	R8C11[0][A]	uart_byte_tx/n157_s2/F
4.802	0.000	tNET	FF	1	R8C11[0][A]	uart_byte_tx/bps_cnt_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C11[0][A]	uart_byte_tx/bps_cnt_3_s1/CLK
4.093	0.000	tHld		1	R8C11[0][A]	uart_byte_tx/bps_cnt_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path20

Path Summary:

Slack	0.709
Data Arrival Time	4.802
Data Required Time	4.093
From	uart_byte_tx/div_cnt_14_s0
To	uart_byte_tx/div_cnt_14_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R7C8[1][A]	uart_byte_tx/div_cnt_14_s0/CLK
4.426	0.333	tC2Q	RR	3	R7C8[1][A]	uart_byte_tx/div_cnt_14_s0/Q
4.430	0.004	tNET	RR	1	R7C8[1][A]	uart_byte_tx/n111_s2/I2
4.802	0.372	tINS	RF	1	R7C8[1][A]	uart_byte_tx/n111_s2/F
4.802	0.000	tNET	FF	1	R7C8[1][A]	uart_byte_tx/div_cnt_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R7C8[1][A]	uart_byte_tx/div_cnt_14_s0/CLK
4.093	0.000	tHld		1	R7C8[1][A]	uart_byte_tx/div_cnt_14_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path21

Path Summary:

Slack	0.710
Data Arrival Time	4.803
Data Required Time	4.093
From	uart_byte_rx/bps_cnt_0_s1
To	uart_byte_rx/bps_cnt_0_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R14C11[0][A]	uart_byte_rx/bps_cnt_0_s1/CLK
4.426	0.333	tC2Q	RR	6	R14C11[0][A]	uart_byte_rx/bps_cnt_0_s1/Q
4.431	0.005	tNET	RR	1	R14C11[0][A]	uart_byte_rx/n156_s3/I0
4.803	0.372	tINS	RF	1	R14C11[0][A]	uart_byte_rx/n156_s3/F
4.803	0.000	tNET	FF	1	R14C11[0][A]	uart_byte_rx/bps_cnt_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R14C11[0][A]	uart_byte_rx/bps_cnt_0_s1/CLK
4.093	0.000	tHld		1	R14C11[0][A]	uart_byte_rx/bps_cnt_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path22

Path Summary:

Slack	0.710
Data Arrival Time	4.803
Data Required Time	4.093
From	uart_byte_rx/START_BIT_0_s0
To	uart_byte_rx/START_BIT_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R14C12[1][A]	uart_byte_rx/START_BIT_0_s0/CLK
4.426	0.333	tC2Q	RR	4	R14C12[1][A]	uart_byte_rx/START_BIT_0_s0/Q
4.431	0.005	tNET	RR	1	R14C12[1][A]	uart_byte_rx/n514_s5/I0
4.803	0.372	tINS	RF	1	R14C12[1][A]	uart_byte_rx/n514_s5/F
4.803	0.000	tNET	FF	1	R14C12[1][A]	uart_byte_rx/START_BIT_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R14C12[1][A]	uart_byte_rx/START_BIT_0_s0/CLK
4.093	0.000	tHld		1	R14C12[1][A]	uart_byte_rx/START_BIT_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path23

Path Summary:

Slack	0.710
Data Arrival Time	4.803
Data Required Time	4.093
From	uart_byte_tx/div_cnt_8_s0
To	uart_byte_tx/div_cnt_8_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C9[0][A]	uart_byte_tx/div_cnt_8_s0/CLK
4.426	0.333	tC2Q	RR	6	R8C9[0][A]	uart_byte_tx/div_cnt_8_s0/Q
4.431	0.005	tNET	RR	1	R8C9[0][A]	uart_byte_tx/n117_s4/I0
4.803	0.372	tINS	RF	1	R8C9[0][A]	uart_byte_tx/n117_s4/F
4.803	0.000	tNET	FF	1	R8C9[0][A]	uart_byte_tx/div_cnt_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C9[0][A]	uart_byte_tx/div_cnt_8_s0/CLK
4.093	0.000	tHld		1	R8C9[0][A]	uart_byte_tx/div_cnt_8_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path24

Path Summary:

Slack	0.711
Data Arrival Time	4.804
Data Required Time	4.093
From	uart_byte_rx/bps_cnt_7_s1
To	uart_byte_rx/bps_cnt_7_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R12C11[0][A]	uart_byte_rx/bps_cnt_7_s1/CLK
4.426	0.333	tC2Q	RR	9	R12C11[0][A]	uart_byte_rx/bps_cnt_7_s1/Q
4.432	0.006	tNET	RR	1	R12C11[0][A]	uart_byte_rx/n149_s2/I3
4.804	0.372	tINS	RF	1	R12C11[0][A]	uart_byte_rx/n149_s2/F
4.804	0.000	tNET	FF	1	R12C11[0][A]	uart_byte_rx/bps_cnt_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R12C11[0][A]	uart_byte_rx/bps_cnt_7_s1/CLK
4.093	0.000	tHld		1	R12C11[0][A]	uart_byte_rx/bps_cnt_7_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path25

Path Summary:

Slack	0.711
Data Arrival Time	4.804
Data Required Time	4.093
From	uart_byte_tx/bps_cnt_1_s3
To	uart_byte_tx/bps_cnt_1_s3
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C10[0][A]	uart_byte_tx/bps_cnt_1_s3/CLK
4.426	0.333	tC2Q	RR	7	R8C10[0][A]	uart_byte_tx/bps_cnt_1_s3/Q
4.432	0.006	tNET	RR	1	R8C10[0][A]	uart_byte_tx/n159_s4/I3
4.804	0.372	tINS	RF	1	R8C10[0][A]	uart_byte_tx/n159_s4/F
4.804	0.000	tNET	FF	1	R8C10[0][A]	uart_byte_tx/bps_cnt_1_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C10[0][A]	uart_byte_tx/bps_cnt_1_s3/CLK
4.093	0.000	tHld		1	R8C10[0][A]	uart_byte_tx/bps_cnt_1_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	clk
Objects:	data_byte_tx_6_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
5.591	1.361	tNET	RR	data_byte_tx_6_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
13.362	1.222	tNET	FF	data_byte_tx_6_s0/CLK

MPW2

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	clk
Objects:	data_byte_tx_5_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
5.591	1.361	tNET	RR	data_byte_tx_5_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
13.362	1.222	tNET	FF	data_byte_tx_5_s0/CLK

MPW3

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	clk
Objects:	data_byte_tx_3_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
5.591	1.361	tNET	RR	data_byte_tx_3_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
13.362	1.222	tNET	FF	data_byte_tx_3_s0/CLK

MPW4

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	clk
Objects:	send_en_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
5.591	1.361	tNET	RR	send_en_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
13.362	1.222	tNET	FF	send_en_s0/CLK

MPW5

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	clk
Objects:	uart_byte_tx/data_byte_reg_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
5.591	1.361	tNET	RR	uart_byte_tx/data_byte_reg_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
13.362	1.222	tNET	FF	uart_byte_tx/data_byte_reg_1_s0/CLK

MPW6

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	clk
Objects:	uart_byte_tx/div_cnt_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
5.591	1.361	tNET	RR	uart_byte_tx/div_cnt_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
13.362	1.222	tNET	FF	uart_byte_tx/div_cnt_1_s0/CLK

MPW7

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	clk
Objects:	uart_byte_rx/START_BIT_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
5.591	1.361	tNET	RR	uart_byte_rx/START_BIT_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
13.362	1.222	tNET	FF	uart_byte_rx/START_BIT_0_s0/CLK

MPW8

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	clk
Objects:	uart_byte_rx/START_BIT_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
5.591	1.361	tNET	RR	uart_byte_rx/START_BIT_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
13.362	1.222	tNET	FF	uart_byte_rx/START_BIT_1_s0/CLK

MPW9

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	clk
Objects:	uart_byte_tx/div_cnt_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
5.591	1.361	tNET	RR	uart_byte_tx/div_cnt_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
13.362	1.222	tNET	FF	uart_byte_tx/div_cnt_2_s0/CLK

MPW10

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	clk
Objects:	uart_byte_rx/START_BIT_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
5.591	1.361	tNET	RR	uart_byte_rx/START_BIT_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
13.362	1.222	tNET	FF	uart_byte_rx/START_BIT_2_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
109	clk_d	12.027	1.727
31	uart_rx_sync2	15.197	2.276
16	uart_state	16.306	1.804
16	uart_state	16.712	1.333
12	bps_cnt[4]	13.313	0.864
12	bps_cnt[5]	12.535	1.162
11	bps_clk	16.351	1.485
11	bps_cnt[6]	12.691	0.858
10	bps_cnt[0]	13.295	0.842
10	send_en	17.517	1.625

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R9C10	76.39%
R8C10	75.00%
R14C12	70.83%
R13C9	70.83%
R8C8	70.83%
R9C7	68.06%
R7C9	68.06%
R8C7	66.67%
R13C12	65.28%
R12C8	65.28%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command