PnR Messages

Report Title PnR Report
Design File /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/UART_RX_1BYTE/impl/gwsynthesis/uart_rx.vg
Physical Constraints File /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/UART_RX_1BYTE/src/uart_rx.cst
Timing Constraints File ---
Tool Version V1.9.11
Part Number GW1NSR-LV4CQN48PC6/I5
Device GW1NSR-4C
Created Time Tue Apr 22 18:29:38 2025
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

PnR Details

Place & Route Process Running placement: Placement Phase 0: CPU time = 0h 0m 0.036s, Elapsed time = 0h 0m 0.033s Placement Phase 1: CPU time = 0h 0m 0.18s, Elapsed time = 0h 0m 0.178s Placement Phase 2: CPU time = 0h 0m 0.036s, Elapsed time = 0h 0m 0.033s Placement Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s Total Placement: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s Running routing: Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Routing Phase 1: CPU time = 0h 0m 0.111s, Elapsed time = 0h 0m 0.107s Routing Phase 2: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.335s Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Total Routing: CPU time = 0h 0m 0.454s, Elapsed time = 0h 0m 0.442s Generate output files: CPU time = 0h 0m 0.445s, Elapsed time = 0h 0m 0.437s
Total Time and Memory Usage CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 334MB

Resource

Resource Usage Summary:

Resource Usage Utilization
Logic 182/4608 4%
    --LUT,ALU,ROM16 182(182 LUT, 0 ALU, 0 ROM16) -
    --SSRAM(RAM16) 0 -
Register 109/3573 4%
    --Logic Register as Latch 0/3456 0%
    --Logic Register as FF 107/3456 4%
    --I/O Register as Latch 0/117 0%
    --I/O Register as FF 2/117 2%
CLS 118/2304 6%
I/O Port 4/39 11%
I/O Buf 4 -
    --Input Buf 3 -
    --Output Buf 1 -
    --Inout Buf 0 -

I/O Bank Usage Summary:

I/O Bank UsageUtilization
bank 0 0/90%
bank 1 3/1030%
bank 2 0/90%
bank 3 1/1110%

Clock Resource Usage Summary:

Clock Resource Usage Utilization
PRIMARY 1/8 13%
LW 1/8 13%
GCLK_PIN 0/5 0%

Global Clock Signals:

Signal Global Clock Location
clk_d PRIMARY LEFT
reset_n_d LW -

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site CFG IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor BankVccio
clk - 45/1 Y in IOT13[A] LPLL_T_in LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
reset_n - 14/3 Y in IOB4[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
uart_rx - 44/1 Y in IOT17[B] GCLKC_0 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
uart_tx - 46/1 Y out IOT13[B] LPLL_C_in LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8

All Package Pins:

Loc./Bank Signal Dir. Site CFG IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor Bank Vccio
3/0 - in IOT2[A] TDI LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
4/0 - out IOT2[B] TDO LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
6/0 - in IOT3[A] TMS LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
7/0 - in IOT3[B] TCK LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
8/0 - in IOT4[B] JTAGSEL_N LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
9/0 - in IOT5[B] DONE LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
10/0 - in IOT7[A] MODE1 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
1/0 - in IOT10[A] MCLK/D4 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
2/0 - in IOT10[B] MCS_N/D5 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
48/1 - in IOT11[A] MO/D6 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
47/1 - in IOT11[B] MI/D7 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
45/1 clk in IOT13[A] LPLL_T_in LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
46/1 uart_tx out IOT13[B] LPLL_C_in LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
43/1 - in IOT17[A] GCLKT_0 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
44/1 uart_rx in IOT17[B] GCLKC_0 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
41/1 - in IOT20[A] GCLKT_1 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
42/1 - in IOT20[B] GCLKC_1 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
39/1 - in IOT26[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
40/1 - in IOT26[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
13/3 - in IOB4[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
14/3 reset_n in IOB4[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
15/3 - in IOB5[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
p1-22/3 - in IOB5[B] - LVCMOS18 - UP - - - - - - -
16/3 - in IOB6[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
17/3 - in IOB6[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
p1-19/3 - in IOB7[A] - LVCMOS18 - UP - - - - - - -
p1-18/3 - in IOB7[B] - LVCMOS18 - UP - - - - - - -
18/3 - in IOB13[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
19/3 - in IOB13[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
p1-17/3 - in IOB14[A] - LVCMOS18 - UP - - - - - - -
p1-16/3 - in IOB14[B] - LVCMOS18 - UP - - - - - - -
p1-15/3 - in IOB15[A] - LVCMOS18 - UP - - - - - - -
p1-14/3 - in IOB15[B] - LVCMOS18 - UP - - - - - - -
20/3 - in IOB16[A] GCLKT_5 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
21/3 - in IOB16[B] GCLKC_5 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
22/3 - in IOB22[A] GCLKT_4 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
23/3 - in IOB22[B] GCLKC_4 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
p1-13/3 - in IOB23[A] - LVCMOS18 - UP - - - - - - -
p1-10/3 - in IOB24[B] - LVCMOS18 - UP - - - - - - -
p1-9/3 - in IOB25[A] - LVCMOS18 - UP - - - - - - -
p1-8/3 - in IOB25[B] - LVCMOS18 - UP - - - - - - -
p1-7/3 - in IOB29[A] - LVCMOS18 - UP - - - - - - -
p1-6/3 - in IOB29[B] - LVCMOS18 - UP - - - - - - -
35/2 - in IOR2[A] RPLL_T_in LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
34/2 - in IOR2[B] RPLL_C_in LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
33/2 - in IOR9[B] GCLKC_2 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
32/2 - in IOR11[A] GCLKT_3 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
31/2 - in IOR11[B] GCLKC_3 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
30/2 - in IOR15[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
29/2 - in IOR15[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
28/2 - in IOR17[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
27/2 - in IOR17[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8