Synthesis Messages

Report Title GowinSynthesis Report
Design File /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/UART_RX_1BYTE/src/uart_byte_rx.v
/home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/UART_RX_1BYTE/src/uart_byte_tx.v
/home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/UART_RX_1BYTE/src/uart_rx_test.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11
Part Number GW1NSR-LV4CQN48PC6/I5
Device GW1NSR-4C
Created Time Tue Apr 22 18:29:33 2025
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module uart_rx_test
Synthesis Process Running parser:
    CPU time = 0h 0m 0.057s, Elapsed time = 0h 0m 0.049s, Peak memory usage = 334.961MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.007s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 334.961MB
    Optimizing Phase 1: CPU time = 0h 0m 0.005s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 334.961MB
    Optimizing Phase 2: CPU time = 0h 0m 0.005s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 334.961MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0s, Peak memory usage = 334.961MB
    Inferring Phase 1: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0s, Peak memory usage = 334.961MB
    Inferring Phase 2: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0s, Peak memory usage = 334.961MB
    Inferring Phase 3: CPU time = 0h 0m 0.003s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 334.961MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.008s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 334.961MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.002s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 334.961MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.002s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 334.961MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.535s, Elapsed time = 0h 0m 0.527s, Peak memory usage = 334.961MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.035s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 334.961MB
Generate output files:
    CPU time = 0h 0m 0.038s, Elapsed time = 0h 0m 0.036s, Peak memory usage = 334.961MB
Total Time and Memory Usage CPU time = 0h 0m 0.7s, Elapsed time = 0h 0m 0.669s, Peak memory usage = 334.961MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 4
I/O Buf 4
    IBUF 3
    OBUF 1
Register 109
    DFFP 1
    DFFC 42
    DFFCE 66
LUT 182
    LUT2 37
    LUT3 44
    LUT4 101
INV 1
    INV 1

Resource Utilization Summary

Resource Usage Utilization
Logic 183(183 LUT, 0 ALU) / 4608 4%
Register 109 / 3573 4%
  --Register as Latch 0 / 3573 0%
  --Register as FF 109 / 3573 4%
BSRAM 0 / 10 0%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk Base 20.000 50.000 0.000 10.000 clk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 50.000(MHz) 101.324(MHz) 4 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 10.131
Data Arrival Time 10.195
Data Required Time 20.326
From uart_byte_tx/data_byte_reg_5_s0
To uart_byte_tx/uart_tx_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 109 clk_ibuf/O
0.726 0.726 tNET RR 1 uart_byte_tx/data_byte_reg_5_s0/CLK
1.184 0.458 tC2Q RF 1 uart_byte_tx/data_byte_reg_5_s0/Q
2.144 0.960 tNET FF 1 uart_byte_tx/n177_s34/I1
3.243 1.099 tINS FF 1 uart_byte_tx/n177_s34/F
4.203 0.960 tNET FF 1 uart_byte_tx/n177_s22/I1
4.352 0.149 tINS FF 1 uart_byte_tx/n177_s22/O
5.312 0.960 tNET FF 1 uart_byte_tx/n177_s35/I0
6.344 1.032 tINS FF 1 uart_byte_tx/n177_s35/F
7.304 0.960 tNET FF 1 uart_byte_tx/n177_s26/I0
7.453 0.149 tINS FF 1 uart_byte_tx/n177_s26/O
8.413 0.960 tNET FF 1 uart_byte_tx/n177_s28/I2
9.235 0.822 tINS FF 1 uart_byte_tx/n177_s28/F
10.195 0.960 tNET FF 1 uart_byte_tx/uart_tx_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 109 clk_ibuf/O
20.726 0.726 tNET RR 1 uart_byte_tx/uart_tx_s0/CLK
20.326 -0.400 tSu 1 uart_byte_tx/uart_tx_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 3.251, 34.332%; route: 5.760, 60.828%; tC2Q: 0.458, 4.840%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 2

Path Summary:
Slack 12.005
Data Arrival Time 8.321
Data Required Time 20.326
From uart_byte_rx/bps_cnt_7_s1
To uart_byte_rx/bps_cnt_0_s1
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 109 clk_ibuf/O
0.726 0.726 tNET RR 1 uart_byte_rx/bps_cnt_7_s1/CLK
1.184 0.458 tC2Q RF 9 uart_byte_rx/bps_cnt_7_s1/Q
2.144 0.960 tNET FF 1 uart_byte_rx/bps_cnt_7_s6/I1
3.243 1.099 tINS FF 5 uart_byte_rx/bps_cnt_7_s6/F
4.203 0.960 tNET FF 1 uart_byte_rx/bps_cnt_7_s4/I1
5.302 1.099 tINS FF 5 uart_byte_rx/bps_cnt_7_s4/F
6.262 0.960 tNET FF 1 uart_byte_rx/n156_s3/I1
7.361 1.099 tINS FF 1 uart_byte_rx/n156_s3/F
8.321 0.960 tNET FF 1 uart_byte_rx/bps_cnt_0_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 109 clk_ibuf/O
20.726 0.726 tNET RR 1 uart_byte_rx/bps_cnt_0_s1/CLK
20.326 -0.400 tSu 1 uart_byte_rx/bps_cnt_0_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 3.297, 43.408%; route: 3.840, 50.558%; tC2Q: 0.458, 6.034%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 3

Path Summary:
Slack 12.005
Data Arrival Time 8.321
Data Required Time 20.326
From uart_byte_rx/div_cnt_5_s0
To uart_byte_rx/div_cnt_9_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 109 clk_ibuf/O
0.726 0.726 tNET RR 1 uart_byte_rx/div_cnt_5_s0/CLK
1.184 0.458 tC2Q RF 5 uart_byte_rx/div_cnt_5_s0/Q
2.144 0.960 tNET FF 1 uart_byte_rx/n96_s4/I1
3.243 1.099 tINS FF 3 uart_byte_rx/n96_s4/F
4.203 0.960 tNET FF 1 uart_byte_rx/n96_s3/I1
5.302 1.099 tINS FF 2 uart_byte_rx/n96_s3/F
6.262 0.960 tNET FF 1 uart_byte_rx/n95_s2/I1
7.361 1.099 tINS FF 1 uart_byte_rx/n95_s2/F
8.321 0.960 tNET FF 1 uart_byte_rx/div_cnt_9_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 109 clk_ibuf/O
20.726 0.726 tNET RR 1 uart_byte_rx/div_cnt_9_s0/CLK
20.326 -0.400 tSu 1 uart_byte_rx/div_cnt_9_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 3.297, 43.408%; route: 3.840, 50.558%; tC2Q: 0.458, 6.034%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 4

Path Summary:
Slack 12.005
Data Arrival Time 8.321
Data Required Time 20.326
From uart_byte_rx/div_cnt_1_s0
To uart_byte_rx/div_cnt_11_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 109 clk_ibuf/O
0.726 0.726 tNET RR 1 uart_byte_rx/div_cnt_1_s0/CLK
1.184 0.458 tC2Q RF 6 uart_byte_rx/div_cnt_1_s0/Q
2.144 0.960 tNET FF 1 uart_byte_rx/n100_s3/I1
3.243 1.099 tINS FF 7 uart_byte_rx/n100_s3/F
4.203 0.960 tNET FF 1 uart_byte_rx/n93_s3/I1
5.302 1.099 tINS FF 5 uart_byte_rx/n93_s3/F
6.262 0.960 tNET FF 1 uart_byte_rx/n93_s2/I1
7.361 1.099 tINS FF 1 uart_byte_rx/n93_s2/F
8.321 0.960 tNET FF 1 uart_byte_rx/div_cnt_11_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 109 clk_ibuf/O
20.726 0.726 tNET RR 1 uart_byte_rx/div_cnt_11_s0/CLK
20.326 -0.400 tSu 1 uart_byte_rx/div_cnt_11_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 3.297, 43.408%; route: 3.840, 50.558%; tC2Q: 0.458, 6.034%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 5

Path Summary:
Slack 12.005
Data Arrival Time 8.321
Data Required Time 20.326
From uart_byte_rx/div_cnt_1_s0
To uart_byte_rx/div_cnt_12_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 109 clk_ibuf/O
0.726 0.726 tNET RR 1 uart_byte_rx/div_cnt_1_s0/CLK
1.184 0.458 tC2Q RF 6 uart_byte_rx/div_cnt_1_s0/Q
2.144 0.960 tNET FF 1 uart_byte_rx/n100_s3/I1
3.243 1.099 tINS FF 7 uart_byte_rx/n100_s3/F
4.203 0.960 tNET FF 1 uart_byte_rx/n93_s3/I1
5.302 1.099 tINS FF 5 uart_byte_rx/n93_s3/F
6.262 0.960 tNET FF 1 uart_byte_rx/n92_s2/I1
7.361 1.099 tINS FF 1 uart_byte_rx/n92_s2/F
8.321 0.960 tNET FF 1 uart_byte_rx/div_cnt_12_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 109 clk_ibuf/O
20.726 0.726 tNET RR 1 uart_byte_rx/div_cnt_12_s0/CLK
20.326 -0.400 tSu 1 uart_byte_rx/div_cnt_12_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 3.297, 43.408%; route: 3.840, 50.558%; tC2Q: 0.458, 6.034%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%