Timing Messages
| Report Title | Timing Analysis Report |
| Design File | /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/Button_filtering_counterl_Led/impl/gwsynthesis/key_led.vg |
| Physical Constraints File | /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/Button_filtering_counterl_Led/src/key_led.cst |
| Timing Constraint File | --- |
| Tool Version | V1.9.11 |
| Part Number | GW1NSR-LV4CQN48PC6/I5 |
| Device | GW1NSR-4C |
| Created Time | Sun Apr 6 23:40:17 2025 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
| Setup Delay Model | Slow 1.14V 85C C6/I5 |
| Hold Delay Model | Fast 1.26V 0C C6/I5 |
| Numbers of Paths Analyzed | 142 |
| Numbers of Endpoints Analyzed | 142 |
| Numbers of Falling Endpoints | 0 |
| Numbers of Setup Violated Endpoints | 0 |
| Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
|---|---|---|---|---|---|---|---|---|---|
| 1 | Clk | Base | 20.000 | 50.000 | 0.000 | 10.000 | Clk_ibuf/I |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | Clk | 50.000(MHz) | 164.268(MHz) | 4 | TOP |
Total Negative Slack Summary:
| Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
|---|---|---|---|
| Clk | Setup | 0.000 | 0 |
| Clk | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 13.912 | key_filter0/cnt_3_s0/Q | key_filter0/cnt_19_s0/D | Clk:[R] | Clk:[R] | 20.000 | 0.000 | 5.688 |
| 2 | 14.100 | key_filter0/cnt_3_s0/Q | key_filter0/cnt_15_s0/D | Clk:[R] | Clk:[R] | 20.000 | 0.000 | 5.500 |
| 3 | 14.137 | key_filter0/cnt_6_s0/Q | key_filter0/cnt_11_s0/D | Clk:[R] | Clk:[R] | 20.000 | 0.000 | 5.463 |
| 4 | 14.155 | key_filter0/cnt_3_s0/Q | key_filter0/cnt_16_s0/D | Clk:[R] | Clk:[R] | 20.000 | 0.000 | 5.445 |
| 5 | 14.155 | key_filter0/cnt_3_s0/Q | key_filter0/cnt_17_s0/D | Clk:[R] | Clk:[R] | 20.000 | 0.000 | 5.445 |
| 6 | 14.290 | key_filter0/cnt_3_s0/Q | key_filter0/cnt_6_s0/D | Clk:[R] | Clk:[R] | 20.000 | 0.000 | 5.310 |
| 7 | 14.290 | key_filter0/cnt_3_s0/Q | key_filter0/cnt_7_s0/D | Clk:[R] | Clk:[R] | 20.000 | 0.000 | 5.310 |
| 8 | 14.307 | key_filter0/cnt_3_s0/Q | key_filter0/cnt_13_s0/D | Clk:[R] | Clk:[R] | 20.000 | 0.000 | 5.293 |
| 9 | 14.318 | key_filter0/cnt_3_s0/Q | key_filter0/cnt_14_s0/D | Clk:[R] | Clk:[R] | 20.000 | 0.000 | 5.282 |
| 10 | 14.517 | key_filter0/cnt_3_s0/Q | key_filter0/cnt_18_s0/D | Clk:[R] | Clk:[R] | 20.000 | 0.000 | 5.083 |
| 11 | 14.555 | key_filter1/cnt_4_s0/Q | key_filter1/cnt_13_s0/D | Clk:[R] | Clk:[R] | 20.000 | 0.000 | 5.045 |
| 12 | 14.555 | key_filter1/cnt_4_s0/Q | key_filter1/cnt_18_s0/D | Clk:[R] | Clk:[R] | 20.000 | 0.000 | 5.045 |
| 13 | 14.701 | key_filter0/cnt_3_s0/Q | key_filter0/cnt_full_s0/D | Clk:[R] | Clk:[R] | 20.000 | 0.000 | 4.899 |
| 14 | 14.746 | key_filter1/cnt_4_s0/Q | key_filter1/cnt_9_s0/D | Clk:[R] | Clk:[R] | 20.000 | 0.000 | 4.854 |
| 15 | 14.871 | key_filter0/cnt_3_s0/Q | key_filter0/cnt_12_s0/D | Clk:[R] | Clk:[R] | 20.000 | 0.000 | 4.729 |
| 16 | 14.936 | key_filter0/cnt_6_s0/Q | key_filter0/cnt_10_s0/D | Clk:[R] | Clk:[R] | 20.000 | 0.000 | 4.664 |
| 17 | 14.936 | key_filter0/cnt_6_s0/Q | key_filter0/cnt_9_s0/D | Clk:[R] | Clk:[R] | 20.000 | 0.000 | 4.664 |
| 18 | 14.964 | key_filter1/cnt_4_s0/Q | key_filter1/cnt_15_s0/D | Clk:[R] | Clk:[R] | 20.000 | 0.000 | 4.636 |
| 19 | 14.968 | key_filter1/cnt_4_s0/Q | key_filter1/cnt_16_s0/D | Clk:[R] | Clk:[R] | 20.000 | 0.000 | 4.632 |
| 20 | 14.976 | key_filter0/cnt_full_s0/Q | key_filter0/en_cnt_s2/CE | Clk:[R] | Clk:[R] | 20.000 | 0.000 | 4.981 |
| 21 | 15.008 | key_filter1/cnt_3_s0/Q | key_filter1/cnt_11_s0/D | Clk:[R] | Clk:[R] | 20.000 | 0.000 | 4.592 |
| 22 | 15.008 | key_filter1/cnt_3_s0/Q | key_filter1/cnt_10_s0/D | Clk:[R] | Clk:[R] | 20.000 | 0.000 | 4.592 |
| 23 | 15.088 | key_filter1/cnt_4_s0/Q | key_filter1/cnt_12_s0/D | Clk:[R] | Clk:[R] | 20.000 | 0.000 | 4.512 |
| 24 | 15.147 | key_filter1/cnt_13_s0/Q | key_filter1/cnt_19_s0/D | Clk:[R] | Clk:[R] | 20.000 | 0.000 | 4.453 |
| 25 | 15.174 | key_filter1/cnt_4_s0/Q | key_filter1/cnt_17_s0/D | Clk:[R] | Clk:[R] | 20.000 | 0.000 | 4.426 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 0.708 | key_filter1/key_flag_s5/Q | key_filter1/key_flag_s5/D | Clk:[R] | Clk:[R] | 0.000 | 0.000 | 0.708 |
| 2 | 0.708 | key_filter0/key_state_s5/Q | key_filter0/key_state_s5/D | Clk:[R] | Clk:[R] | 0.000 | 0.000 | 0.708 |
| 3 | 0.708 | key_filter0/cnt_0_s0/Q | key_filter0/cnt_0_s0/D | Clk:[R] | Clk:[R] | 0.000 | 0.000 | 0.708 |
| 4 | 0.708 | key_filter0/cnt_3_s0/Q | key_filter0/cnt_3_s0/D | Clk:[R] | Clk:[R] | 0.000 | 0.000 | 0.708 |
| 5 | 0.709 | led_ctrl0/led_r_0_s1/Q | led_ctrl0/led_r_0_s1/D | Clk:[R] | Clk:[R] | 0.000 | 0.000 | 0.709 |
| 6 | 0.709 | key_filter1/cnt_2_s0/Q | key_filter1/cnt_2_s0/D | Clk:[R] | Clk:[R] | 0.000 | 0.000 | 0.709 |
| 7 | 0.709 | key_filter1/cnt_4_s0/Q | key_filter1/cnt_4_s0/D | Clk:[R] | Clk:[R] | 0.000 | 0.000 | 0.709 |
| 8 | 0.709 | key_filter1/cnt_7_s0/Q | key_filter1/cnt_7_s0/D | Clk:[R] | Clk:[R] | 0.000 | 0.000 | 0.709 |
| 9 | 0.709 | key_filter1/cnt_11_s0/Q | key_filter1/cnt_11_s0/D | Clk:[R] | Clk:[R] | 0.000 | 0.000 | 0.709 |
| 10 | 0.709 | key_filter1/cnt_14_s0/Q | key_filter1/cnt_14_s0/D | Clk:[R] | Clk:[R] | 0.000 | 0.000 | 0.709 |
| 11 | 0.709 | key_filter1/cnt_17_s0/Q | key_filter1/cnt_17_s0/D | Clk:[R] | Clk:[R] | 0.000 | 0.000 | 0.709 |
| 12 | 0.709 | key_filter1/cnt_18_s0/Q | key_filter1/cnt_18_s0/D | Clk:[R] | Clk:[R] | 0.000 | 0.000 | 0.709 |
| 13 | 0.709 | key_filter0/cnt_5_s0/Q | key_filter0/cnt_5_s0/D | Clk:[R] | Clk:[R] | 0.000 | 0.000 | 0.709 |
| 14 | 0.709 | key_filter0/cnt_12_s0/Q | key_filter0/cnt_12_s0/D | Clk:[R] | Clk:[R] | 0.000 | 0.000 | 0.709 |
| 15 | 0.709 | key_filter0/cnt_16_s0/Q | key_filter0/cnt_16_s0/D | Clk:[R] | Clk:[R] | 0.000 | 0.000 | 0.709 |
| 16 | 0.709 | key_filter0/cnt_17_s0/Q | key_filter0/cnt_17_s0/D | Clk:[R] | Clk:[R] | 0.000 | 0.000 | 0.709 |
| 17 | 0.710 | key_filter1/state.IDEL_s0/Q | key_filter1/state.IDEL_s0/D | Clk:[R] | Clk:[R] | 0.000 | 0.000 | 0.710 |
| 18 | 0.710 | key_filter0/cnt_6_s0/Q | key_filter0/cnt_6_s0/D | Clk:[R] | Clk:[R] | 0.000 | 0.000 | 0.710 |
| 19 | 0.711 | key_filter1/cnt_8_s0/Q | key_filter1/cnt_8_s0/D | Clk:[R] | Clk:[R] | 0.000 | 0.000 | 0.711 |
| 20 | 0.711 | key_filter0/state.DOWN_s0/Q | key_filter0/state.DOWN_s0/D | Clk:[R] | Clk:[R] | 0.000 | 0.000 | 0.711 |
| 21 | 0.892 | key_filter1/cnt_15_s0/Q | key_filter1/cnt_15_s0/D | Clk:[R] | Clk:[R] | 0.000 | 0.000 | 0.892 |
| 22 | 0.893 | key_filter1/cnt_5_s0/Q | key_filter1/cnt_5_s0/D | Clk:[R] | Clk:[R] | 0.000 | 0.000 | 0.893 |
| 23 | 0.895 | key_filter0/cnt_13_s0/Q | key_filter0/cnt_13_s0/D | Clk:[R] | Clk:[R] | 0.000 | 0.000 | 0.895 |
| 24 | 0.895 | key_filter1/state.DOWN_s0/Q | key_filter1/state.DOWN_s0/D | Clk:[R] | Clk:[R] | 0.000 | 0.000 | 0.895 |
| 25 | 0.946 | key_filter0/cnt_6_s0/Q | key_filter0/cnt_7_s0/D | Clk:[R] | Clk:[R] | 0.000 | 0.000 | 0.946 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Nothing to report!
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Nothing to report!
Minimum Pulse Width Table:
| Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
|---|---|---|---|---|---|---|
| 1 | 6.521 | 7.771 | 1.250 | High Pulse Width | Clk | key_filter0/key_in_sb_s0 |
| 2 | 6.521 | 7.771 | 1.250 | High Pulse Width | Clk | key_filter0/key_tmpa_s0 |
| 3 | 6.521 | 7.771 | 1.250 | High Pulse Width | Clk | key_filter0/state.DOWN_s0 |
| 4 | 6.521 | 7.771 | 1.250 | High Pulse Width | Clk | key_filter0/cnt_16_s0 |
| 5 | 6.521 | 7.771 | 1.250 | High Pulse Width | Clk | key_filter0/cnt_8_s0 |
| 6 | 6.521 | 7.771 | 1.250 | High Pulse Width | Clk | key_filter0/key_state_s5 |
| 7 | 6.521 | 7.771 | 1.250 | High Pulse Width | Clk | key_filter1/key_state_s5 |
| 8 | 6.521 | 7.771 | 1.250 | High Pulse Width | Clk | key_filter1/key_flag_s5 |
| 9 | 6.521 | 7.771 | 1.250 | High Pulse Width | Clk | key_filter0/key_flag_s5 |
| 10 | 6.521 | 7.771 | 1.250 | High Pulse Width | Clk | key_filter1/state.FILTER1_s1 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 13.912 |
| Data Arrival Time | 11.279 |
| Data Required Time | 25.191 |
| From | key_filter0/cnt_3_s0 |
| To | key_filter0/cnt_19_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 4.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 5.591 | 1.361 | tNET | RR | 1 | R12C7[0][A] | key_filter0/cnt_3_s0/CLK |
| 6.049 | 0.458 | tC2Q | RR | 2 | R12C7[0][A] | key_filter0/cnt_3_s0/Q |
| 6.470 | 0.420 | tNET | RR | 1 | R12C7[3][B] | key_filter0/n106_s2/I3 |
| 7.569 | 1.099 | tINS | RF | 7 | R12C7[3][B] | key_filter0/n106_s2/F |
| 8.394 | 0.825 | tNET | FF | 1 | R14C8[1][B] | key_filter0/n92_s2/I1 |
| 9.426 | 1.032 | tINS | FF | 7 | R14C8[1][B] | key_filter0/n92_s2/F |
| 10.247 | 0.821 | tNET | FF | 1 | R13C7[1][B] | key_filter0/n92_s1/I0 |
| 11.279 | 1.032 | tINS | FF | 1 | R13C7[1][B] | key_filter0/n92_s1/F |
| 11.279 | 0.000 | tNET | FF | 1 | R13C7[1][B] | key_filter0/cnt_19_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | Clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 24.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 25.591 | 1.361 | tNET | RR | 1 | R13C7[1][B] | key_filter0/cnt_19_s0/CLK |
| 25.191 | -0.400 | tSu | 1 | R13C7[1][B] | key_filter0/cnt_19_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 20.000 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
| Arrival Data Path Delay | cell: 3.163, 55.612%; route: 2.066, 36.329%; tC2Q: 0.458, 8.058% |
| Required Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
Path2
Path Summary:
| Slack | 14.100 |
| Data Arrival Time | 11.091 |
| Data Required Time | 25.191 |
| From | key_filter0/cnt_3_s0 |
| To | key_filter0/cnt_15_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 4.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 5.591 | 1.361 | tNET | RR | 1 | R12C7[0][A] | key_filter0/cnt_3_s0/CLK |
| 6.049 | 0.458 | tC2Q | RR | 2 | R12C7[0][A] | key_filter0/cnt_3_s0/Q |
| 6.470 | 0.420 | tNET | RR | 1 | R12C7[3][B] | key_filter0/n106_s2/I3 |
| 7.569 | 1.099 | tINS | RF | 7 | R12C7[3][B] | key_filter0/n106_s2/F |
| 8.394 | 0.825 | tNET | FF | 1 | R14C8[1][B] | key_filter0/n92_s2/I1 |
| 9.426 | 1.032 | tINS | FF | 7 | R14C8[1][B] | key_filter0/n92_s2/F |
| 10.269 | 0.843 | tNET | FF | 1 | R13C6[0][B] | key_filter0/n96_s1/I0 |
| 11.091 | 0.822 | tINS | FF | 1 | R13C6[0][B] | key_filter0/n96_s1/F |
| 11.091 | 0.000 | tNET | FF | 1 | R13C6[0][B] | key_filter0/cnt_15_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | Clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 24.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 25.591 | 1.361 | tNET | RR | 1 | R13C6[0][B] | key_filter0/cnt_15_s0/CLK |
| 25.191 | -0.400 | tSu | 1 | R13C6[0][B] | key_filter0/cnt_15_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 20.000 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
| Arrival Data Path Delay | cell: 2.953, 53.689%; route: 2.089, 37.978%; tC2Q: 0.458, 8.333% |
| Required Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
Path3
Path Summary:
| Slack | 14.137 |
| Data Arrival Time | 11.054 |
| Data Required Time | 25.191 |
| From | key_filter0/cnt_6_s0 |
| To | key_filter0/cnt_11_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 4.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 5.591 | 1.361 | tNET | RR | 1 | R13C6[0][A] | key_filter0/cnt_6_s0/CLK |
| 6.049 | 0.458 | tC2Q | RF | 4 | R13C6[0][A] | key_filter0/cnt_6_s0/Q |
| 6.865 | 0.815 | tNET | FF | 1 | R13C8[3][A] | key_filter0/n92_s5/I2 |
| 7.891 | 1.026 | tINS | FR | 4 | R13C8[3][A] | key_filter0/n92_s5/F |
| 8.317 | 0.427 | tNET | RR | 1 | R13C9[2][A] | key_filter0/n100_s3/I1 |
| 9.416 | 1.099 | tINS | RF | 3 | R13C9[2][A] | key_filter0/n100_s3/F |
| 10.232 | 0.815 | tNET | FF | 1 | R14C8[0][B] | key_filter0/n100_s1/I1 |
| 11.054 | 0.822 | tINS | FF | 1 | R14C8[0][B] | key_filter0/n100_s1/F |
| 11.054 | 0.000 | tNET | FF | 1 | R14C8[0][B] | key_filter0/cnt_11_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | Clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 24.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 25.591 | 1.361 | tNET | RR | 1 | R14C8[0][B] | key_filter0/cnt_11_s0/CLK |
| 25.191 | -0.400 | tSu | 1 | R14C8[0][B] | key_filter0/cnt_11_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 20.000 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
| Arrival Data Path Delay | cell: 2.947, 53.948%; route: 2.057, 37.661%; tC2Q: 0.458, 8.390% |
| Required Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
Path4
Path Summary:
| Slack | 14.155 |
| Data Arrival Time | 11.036 |
| Data Required Time | 25.191 |
| From | key_filter0/cnt_3_s0 |
| To | key_filter0/cnt_16_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 4.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 5.591 | 1.361 | tNET | RR | 1 | R12C7[0][A] | key_filter0/cnt_3_s0/CLK |
| 6.049 | 0.458 | tC2Q | RR | 2 | R12C7[0][A] | key_filter0/cnt_3_s0/Q |
| 6.470 | 0.420 | tNET | RR | 1 | R12C7[3][B] | key_filter0/n106_s2/I3 |
| 7.569 | 1.099 | tINS | RF | 7 | R12C7[3][B] | key_filter0/n106_s2/F |
| 8.394 | 0.825 | tNET | FF | 1 | R14C8[1][B] | key_filter0/n92_s2/I1 |
| 9.426 | 1.032 | tINS | FF | 7 | R14C8[1][B] | key_filter0/n92_s2/F |
| 9.937 | 0.511 | tNET | FF | 1 | R13C8[1][A] | key_filter0/n95_s1/I0 |
| 11.036 | 1.099 | tINS | FF | 1 | R13C8[1][A] | key_filter0/n95_s1/F |
| 11.036 | 0.000 | tNET | FF | 1 | R13C8[1][A] | key_filter0/cnt_16_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | Clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 24.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 25.591 | 1.361 | tNET | RR | 1 | R13C8[1][A] | key_filter0/cnt_16_s0/CLK |
| 25.191 | -0.400 | tSu | 1 | R13C8[1][A] | key_filter0/cnt_16_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 20.000 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
| Arrival Data Path Delay | cell: 3.230, 59.322%; route: 1.756, 32.260%; tC2Q: 0.458, 8.418% |
| Required Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
Path5
Path Summary:
| Slack | 14.155 |
| Data Arrival Time | 11.036 |
| Data Required Time | 25.191 |
| From | key_filter0/cnt_3_s0 |
| To | key_filter0/cnt_17_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 4.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 5.591 | 1.361 | tNET | RR | 1 | R12C7[0][A] | key_filter0/cnt_3_s0/CLK |
| 6.049 | 0.458 | tC2Q | RR | 2 | R12C7[0][A] | key_filter0/cnt_3_s0/Q |
| 6.470 | 0.420 | tNET | RR | 1 | R12C7[3][B] | key_filter0/n106_s2/I3 |
| 7.569 | 1.099 | tINS | RF | 7 | R12C7[3][B] | key_filter0/n106_s2/F |
| 8.394 | 0.825 | tNET | FF | 1 | R14C8[1][B] | key_filter0/n92_s2/I1 |
| 9.426 | 1.032 | tINS | FF | 7 | R14C8[1][B] | key_filter0/n92_s2/F |
| 9.937 | 0.511 | tNET | FF | 1 | R13C8[0][A] | key_filter0/n94_s1/I0 |
| 11.036 | 1.099 | tINS | FF | 1 | R13C8[0][A] | key_filter0/n94_s1/F |
| 11.036 | 0.000 | tNET | FF | 1 | R13C8[0][A] | key_filter0/cnt_17_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | Clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 24.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 25.591 | 1.361 | tNET | RR | 1 | R13C8[0][A] | key_filter0/cnt_17_s0/CLK |
| 25.191 | -0.400 | tSu | 1 | R13C8[0][A] | key_filter0/cnt_17_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 20.000 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
| Arrival Data Path Delay | cell: 3.230, 59.322%; route: 1.756, 32.260%; tC2Q: 0.458, 8.418% |
| Required Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
Path6
Path Summary:
| Slack | 14.290 |
| Data Arrival Time | 10.901 |
| Data Required Time | 25.191 |
| From | key_filter0/cnt_3_s0 |
| To | key_filter0/cnt_6_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 4.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 5.591 | 1.361 | tNET | RR | 1 | R12C7[0][A] | key_filter0/cnt_3_s0/CLK |
| 6.049 | 0.458 | tC2Q | RR | 2 | R12C7[0][A] | key_filter0/cnt_3_s0/Q |
| 6.470 | 0.420 | tNET | RR | 1 | R12C7[3][B] | key_filter0/n106_s2/I3 |
| 7.531 | 1.061 | tINS | RR | 7 | R12C7[3][B] | key_filter0/n106_s2/F |
| 7.955 | 0.425 | tNET | RR | 1 | R12C8[1][B] | key_filter0/n148_s3/I2 |
| 9.054 | 1.099 | tINS | RF | 3 | R12C8[1][B] | key_filter0/n148_s3/F |
| 9.869 | 0.814 | tNET | FF | 1 | R13C6[0][A] | key_filter0/n105_s1/I1 |
| 10.901 | 1.032 | tINS | FF | 1 | R13C6[0][A] | key_filter0/n105_s1/F |
| 10.901 | 0.000 | tNET | FF | 1 | R13C6[0][A] | key_filter0/cnt_6_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | Clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 24.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 25.591 | 1.361 | tNET | RR | 1 | R13C6[0][A] | key_filter0/cnt_6_s0/CLK |
| 25.191 | -0.400 | tSu | 1 | R13C6[0][A] | key_filter0/cnt_6_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 20.000 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
| Arrival Data Path Delay | cell: 3.192, 60.119%; route: 1.659, 31.249%; tC2Q: 0.458, 8.632% |
| Required Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
Path7
Path Summary:
| Slack | 14.290 |
| Data Arrival Time | 10.901 |
| Data Required Time | 25.191 |
| From | key_filter0/cnt_3_s0 |
| To | key_filter0/cnt_7_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 4.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 5.591 | 1.361 | tNET | RR | 1 | R12C7[0][A] | key_filter0/cnt_3_s0/CLK |
| 6.049 | 0.458 | tC2Q | RR | 2 | R12C7[0][A] | key_filter0/cnt_3_s0/Q |
| 6.470 | 0.420 | tNET | RR | 1 | R12C7[3][B] | key_filter0/n106_s2/I3 |
| 7.531 | 1.061 | tINS | RR | 7 | R12C7[3][B] | key_filter0/n106_s2/F |
| 7.955 | 0.425 | tNET | RR | 1 | R12C8[1][B] | key_filter0/n148_s3/I2 |
| 9.054 | 1.099 | tINS | RF | 3 | R12C8[1][B] | key_filter0/n148_s3/F |
| 9.869 | 0.814 | tNET | FF | 1 | R13C6[1][B] | key_filter0/n104_s1/I1 |
| 10.901 | 1.032 | tINS | FF | 1 | R13C6[1][B] | key_filter0/n104_s1/F |
| 10.901 | 0.000 | tNET | FF | 1 | R13C6[1][B] | key_filter0/cnt_7_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | Clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 24.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 25.591 | 1.361 | tNET | RR | 1 | R13C6[1][B] | key_filter0/cnt_7_s0/CLK |
| 25.191 | -0.400 | tSu | 1 | R13C6[1][B] | key_filter0/cnt_7_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 20.000 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
| Arrival Data Path Delay | cell: 3.192, 60.119%; route: 1.659, 31.249%; tC2Q: 0.458, 8.632% |
| Required Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
Path8
Path Summary:
| Slack | 14.307 |
| Data Arrival Time | 10.885 |
| Data Required Time | 25.191 |
| From | key_filter0/cnt_3_s0 |
| To | key_filter0/cnt_13_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 4.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 5.591 | 1.361 | tNET | RR | 1 | R12C7[0][A] | key_filter0/cnt_3_s0/CLK |
| 6.049 | 0.458 | tC2Q | RR | 2 | R12C7[0][A] | key_filter0/cnt_3_s0/Q |
| 6.470 | 0.420 | tNET | RR | 1 | R12C7[3][B] | key_filter0/n106_s2/I3 |
| 7.569 | 1.099 | tINS | RF | 7 | R12C7[3][B] | key_filter0/n106_s2/F |
| 8.394 | 0.825 | tNET | FF | 1 | R14C8[1][B] | key_filter0/n92_s2/I1 |
| 9.420 | 1.026 | tINS | FR | 7 | R14C8[1][B] | key_filter0/n92_s2/F |
| 9.853 | 0.433 | tNET | RR | 1 | R13C8[2][A] | key_filter0/n98_s1/I1 |
| 10.885 | 1.032 | tINS | RF | 1 | R13C8[2][A] | key_filter0/n98_s1/F |
| 10.885 | 0.000 | tNET | FF | 1 | R13C8[2][A] | key_filter0/cnt_13_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | Clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 24.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 25.591 | 1.361 | tNET | RR | 1 | R13C8[2][A] | key_filter0/cnt_13_s0/CLK |
| 25.191 | -0.400 | tSu | 1 | R13C8[2][A] | key_filter0/cnt_13_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 20.000 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
| Arrival Data Path Delay | cell: 3.157, 59.640%; route: 1.678, 31.701%; tC2Q: 0.458, 8.659% |
| Required Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
Path9
Path Summary:
| Slack | 14.318 |
| Data Arrival Time | 10.873 |
| Data Required Time | 25.191 |
| From | key_filter0/cnt_3_s0 |
| To | key_filter0/cnt_14_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 4.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 5.591 | 1.361 | tNET | RR | 1 | R12C7[0][A] | key_filter0/cnt_3_s0/CLK |
| 6.049 | 0.458 | tC2Q | RR | 2 | R12C7[0][A] | key_filter0/cnt_3_s0/Q |
| 6.470 | 0.420 | tNET | RR | 1 | R12C7[3][B] | key_filter0/n106_s2/I3 |
| 7.569 | 1.099 | tINS | RF | 7 | R12C7[3][B] | key_filter0/n106_s2/F |
| 8.394 | 0.825 | tNET | FF | 1 | R14C8[1][B] | key_filter0/n92_s2/I1 |
| 9.426 | 1.032 | tINS | FF | 7 | R14C8[1][B] | key_filter0/n92_s2/F |
| 10.247 | 0.821 | tNET | FF | 1 | R13C8[2][B] | key_filter0/n97_s1/I1 |
| 10.873 | 0.626 | tINS | FF | 1 | R13C8[2][B] | key_filter0/n97_s1/F |
| 10.873 | 0.000 | tNET | FF | 1 | R13C8[2][B] | key_filter0/cnt_14_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | Clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 24.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 25.591 | 1.361 | tNET | RR | 1 | R13C8[2][B] | key_filter0/cnt_14_s0/CLK |
| 25.191 | -0.400 | tSu | 1 | R13C8[2][B] | key_filter0/cnt_14_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 20.000 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
| Arrival Data Path Delay | cell: 2.757, 52.200%; route: 2.066, 39.122%; tC2Q: 0.458, 8.678% |
| Required Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
Path10
Path Summary:
| Slack | 14.517 |
| Data Arrival Time | 10.675 |
| Data Required Time | 25.191 |
| From | key_filter0/cnt_3_s0 |
| To | key_filter0/cnt_18_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 4.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 5.591 | 1.361 | tNET | RR | 1 | R12C7[0][A] | key_filter0/cnt_3_s0/CLK |
| 6.049 | 0.458 | tC2Q | RR | 2 | R12C7[0][A] | key_filter0/cnt_3_s0/Q |
| 6.470 | 0.420 | tNET | RR | 1 | R12C7[3][B] | key_filter0/n106_s2/I3 |
| 7.569 | 1.099 | tINS | RF | 7 | R12C7[3][B] | key_filter0/n106_s2/F |
| 8.394 | 0.825 | tNET | FF | 1 | R14C8[1][B] | key_filter0/n92_s2/I1 |
| 9.420 | 1.026 | tINS | FR | 7 | R14C8[1][B] | key_filter0/n92_s2/F |
| 9.853 | 0.433 | tNET | RR | 1 | R13C8[0][B] | key_filter0/n93_s1/I0 |
| 10.675 | 0.822 | tINS | RF | 1 | R13C8[0][B] | key_filter0/n93_s1/F |
| 10.675 | 0.000 | tNET | FF | 1 | R13C8[0][B] | key_filter0/cnt_18_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | Clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 24.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 25.591 | 1.361 | tNET | RR | 1 | R13C8[0][B] | key_filter0/cnt_18_s0/CLK |
| 25.191 | -0.400 | tSu | 1 | R13C8[0][B] | key_filter0/cnt_18_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 20.000 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
| Arrival Data Path Delay | cell: 2.947, 57.973%; route: 1.678, 33.011%; tC2Q: 0.458, 9.016% |
| Required Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
Path11
Path Summary:
| Slack | 14.555 |
| Data Arrival Time | 10.636 |
| Data Required Time | 25.191 |
| From | key_filter1/cnt_4_s0 |
| To | key_filter1/cnt_13_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 4.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 5.591 | 1.361 | tNET | RR | 1 | R7C9[0][A] | key_filter1/cnt_4_s0/CLK |
| 6.049 | 0.458 | tC2Q | RR | 4 | R7C9[0][A] | key_filter1/cnt_4_s0/Q |
| 6.475 | 0.426 | tNET | RR | 1 | R7C8[0][B] | key_filter1/n103_s3/I0 |
| 7.536 | 1.061 | tINS | RR | 4 | R7C8[0][B] | key_filter1/n103_s3/F |
| 7.961 | 0.425 | tNET | RR | 1 | R8C8[3][A] | key_filter1/n98_s2/I2 |
| 8.783 | 0.822 | tINS | RF | 7 | R8C8[3][A] | key_filter1/n98_s2/F |
| 9.604 | 0.821 | tNET | FF | 1 | R9C9[0][B] | key_filter1/n98_s1/I1 |
| 10.636 | 1.032 | tINS | FF | 1 | R9C9[0][B] | key_filter1/n98_s1/F |
| 10.636 | 0.000 | tNET | FF | 1 | R9C9[0][B] | key_filter1/cnt_13_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | Clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 24.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 25.591 | 1.361 | tNET | RR | 1 | R9C9[0][B] | key_filter1/cnt_13_s0/CLK |
| 25.191 | -0.400 | tSu | 1 | R9C9[0][B] | key_filter1/cnt_13_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 20.000 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
| Arrival Data Path Delay | cell: 2.915, 57.785%; route: 1.671, 33.129%; tC2Q: 0.458, 9.086% |
| Required Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
Path12
Path Summary:
| Slack | 14.555 |
| Data Arrival Time | 10.636 |
| Data Required Time | 25.191 |
| From | key_filter1/cnt_4_s0 |
| To | key_filter1/cnt_18_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 4.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 5.591 | 1.361 | tNET | RR | 1 | R7C9[0][A] | key_filter1/cnt_4_s0/CLK |
| 6.049 | 0.458 | tC2Q | RR | 4 | R7C9[0][A] | key_filter1/cnt_4_s0/Q |
| 6.475 | 0.426 | tNET | RR | 1 | R7C8[0][B] | key_filter1/n103_s3/I0 |
| 7.536 | 1.061 | tINS | RR | 4 | R7C8[0][B] | key_filter1/n103_s3/F |
| 7.961 | 0.425 | tNET | RR | 1 | R8C8[3][A] | key_filter1/n98_s2/I2 |
| 8.783 | 0.822 | tINS | RF | 7 | R8C8[3][A] | key_filter1/n98_s2/F |
| 9.604 | 0.821 | tNET | FF | 1 | R8C7[1][A] | key_filter1/n93_s1/I0 |
| 10.636 | 1.032 | tINS | FF | 1 | R8C7[1][A] | key_filter1/n93_s1/F |
| 10.636 | 0.000 | tNET | FF | 1 | R8C7[1][A] | key_filter1/cnt_18_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | Clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 24.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 25.591 | 1.361 | tNET | RR | 1 | R8C7[1][A] | key_filter1/cnt_18_s0/CLK |
| 25.191 | -0.400 | tSu | 1 | R8C7[1][A] | key_filter1/cnt_18_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 20.000 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
| Arrival Data Path Delay | cell: 2.915, 57.785%; route: 1.671, 33.129%; tC2Q: 0.458, 9.086% |
| Required Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
Path13
Path Summary:
| Slack | 14.701 |
| Data Arrival Time | 10.490 |
| Data Required Time | 25.191 |
| From | key_filter0/cnt_3_s0 |
| To | key_filter0/cnt_full_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 4.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 5.591 | 1.361 | tNET | RR | 1 | R12C7[0][A] | key_filter0/cnt_3_s0/CLK |
| 6.049 | 0.458 | tC2Q | RR | 2 | R12C7[0][A] | key_filter0/cnt_3_s0/Q |
| 6.470 | 0.420 | tNET | RR | 1 | R12C7[3][B] | key_filter0/n106_s2/I3 |
| 7.531 | 1.061 | tINS | RR | 7 | R12C7[3][B] | key_filter0/n106_s2/F |
| 7.955 | 0.425 | tNET | RR | 1 | R12C8[1][B] | key_filter0/n148_s3/I2 |
| 9.054 | 1.099 | tINS | RF | 3 | R12C8[1][B] | key_filter0/n148_s3/F |
| 9.864 | 0.810 | tNET | FF | 1 | R13C7[0][B] | key_filter0/n148_s1/I2 |
| 10.490 | 0.626 | tINS | FF | 1 | R13C7[0][B] | key_filter0/n148_s1/F |
| 10.490 | 0.000 | tNET | FF | 1 | R13C7[0][B] | key_filter0/cnt_full_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | Clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 24.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 25.591 | 1.361 | tNET | RR | 1 | R13C7[0][B] | key_filter0/cnt_full_s0/CLK |
| 25.191 | -0.400 | tSu | 1 | R13C7[0][B] | key_filter0/cnt_full_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 20.000 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
| Arrival Data Path Delay | cell: 2.786, 56.869%; route: 1.655, 33.775%; tC2Q: 0.458, 9.356% |
| Required Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
Path14
Path Summary:
| Slack | 14.746 |
| Data Arrival Time | 10.445 |
| Data Required Time | 25.191 |
| From | key_filter1/cnt_4_s0 |
| To | key_filter1/cnt_9_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 4.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 5.591 | 1.361 | tNET | RR | 1 | R7C9[0][A] | key_filter1/cnt_4_s0/CLK |
| 6.049 | 0.458 | tC2Q | RR | 4 | R7C9[0][A] | key_filter1/cnt_4_s0/Q |
| 6.475 | 0.426 | tNET | RR | 1 | R7C8[0][B] | key_filter1/n103_s3/I0 |
| 7.536 | 1.061 | tINS | RR | 4 | R7C8[0][B] | key_filter1/n103_s3/F |
| 7.961 | 0.425 | tNET | RR | 1 | R8C8[1][B] | key_filter1/n103_s2/I1 |
| 8.993 | 1.032 | tINS | RF | 2 | R8C8[1][B] | key_filter1/n103_s2/F |
| 9.819 | 0.826 | tNET | FF | 1 | R8C9[1][B] | key_filter1/n102_s1/I1 |
| 10.445 | 0.626 | tINS | FF | 1 | R8C9[1][B] | key_filter1/n102_s1/F |
| 10.445 | 0.000 | tNET | FF | 1 | R8C9[1][B] | key_filter1/cnt_9_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | Clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 24.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 25.591 | 1.361 | tNET | RR | 1 | R8C9[1][B] | key_filter1/cnt_9_s0/CLK |
| 25.191 | -0.400 | tSu | 1 | R8C9[1][B] | key_filter1/cnt_9_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 20.000 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
| Arrival Data Path Delay | cell: 2.719, 56.015%; route: 1.677, 34.543%; tC2Q: 0.458, 9.442% |
| Required Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
Path15
Path Summary:
| Slack | 14.871 |
| Data Arrival Time | 10.320 |
| Data Required Time | 25.191 |
| From | key_filter0/cnt_3_s0 |
| To | key_filter0/cnt_12_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 4.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 5.591 | 1.361 | tNET | RR | 1 | R12C7[0][A] | key_filter0/cnt_3_s0/CLK |
| 6.049 | 0.458 | tC2Q | RR | 2 | R12C7[0][A] | key_filter0/cnt_3_s0/Q |
| 6.470 | 0.420 | tNET | RR | 1 | R12C7[3][B] | key_filter0/n106_s2/I3 |
| 7.569 | 1.099 | tINS | RF | 7 | R12C7[3][B] | key_filter0/n106_s2/F |
| 8.394 | 0.825 | tNET | FF | 1 | R14C8[2][A] | key_filter0/n99_s2/I1 |
| 9.493 | 1.099 | tINS | FF | 1 | R14C8[2][A] | key_filter0/n99_s2/F |
| 9.498 | 0.005 | tNET | FF | 1 | R14C8[0][A] | key_filter0/n99_s1/I0 |
| 10.320 | 0.822 | tINS | FF | 1 | R14C8[0][A] | key_filter0/n99_s1/F |
| 10.320 | 0.000 | tNET | FF | 1 | R14C8[0][A] | key_filter0/cnt_12_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | Clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 24.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 25.591 | 1.361 | tNET | RR | 1 | R14C8[0][A] | key_filter0/cnt_12_s0/CLK |
| 25.191 | -0.400 | tSu | 1 | R14C8[0][A] | key_filter0/cnt_12_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 20.000 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
| Arrival Data Path Delay | cell: 3.020, 63.858%; route: 1.251, 26.451%; tC2Q: 0.458, 9.691% |
| Required Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
Path16
Path Summary:
| Slack | 14.936 |
| Data Arrival Time | 10.255 |
| Data Required Time | 25.191 |
| From | key_filter0/cnt_6_s0 |
| To | key_filter0/cnt_10_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 4.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 5.591 | 1.361 | tNET | RR | 1 | R13C6[0][A] | key_filter0/cnt_6_s0/CLK |
| 6.049 | 0.458 | tC2Q | RF | 4 | R13C6[0][A] | key_filter0/cnt_6_s0/Q |
| 6.865 | 0.815 | tNET | FF | 1 | R13C8[3][A] | key_filter0/n92_s5/I2 |
| 7.891 | 1.026 | tINS | FR | 4 | R13C8[3][A] | key_filter0/n92_s5/F |
| 8.317 | 0.427 | tNET | RR | 1 | R13C9[2][A] | key_filter0/n100_s3/I1 |
| 9.416 | 1.099 | tINS | RF | 3 | R13C9[2][A] | key_filter0/n100_s3/F |
| 9.433 | 0.016 | tNET | FF | 1 | R13C9[0][A] | key_filter0/n101_s1/I1 |
| 10.255 | 0.822 | tINS | FF | 1 | R13C9[0][A] | key_filter0/n101_s1/F |
| 10.255 | 0.000 | tNET | FF | 1 | R13C9[0][A] | key_filter0/cnt_10_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | Clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 24.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 25.591 | 1.361 | tNET | RR | 1 | R13C9[0][A] | key_filter0/cnt_10_s0/CLK |
| 25.191 | -0.400 | tSu | 1 | R13C9[0][A] | key_filter0/cnt_10_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 20.000 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
| Arrival Data Path Delay | cell: 2.947, 63.189%; route: 1.258, 26.983%; tC2Q: 0.458, 9.828% |
| Required Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
Path17
Path Summary:
| Slack | 14.936 |
| Data Arrival Time | 10.255 |
| Data Required Time | 25.191 |
| From | key_filter0/cnt_6_s0 |
| To | key_filter0/cnt_9_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 4.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 5.591 | 1.361 | tNET | RR | 1 | R13C6[0][A] | key_filter0/cnt_6_s0/CLK |
| 6.049 | 0.458 | tC2Q | RF | 4 | R13C6[0][A] | key_filter0/cnt_6_s0/Q |
| 6.865 | 0.815 | tNET | FF | 1 | R13C8[3][A] | key_filter0/n92_s5/I2 |
| 7.891 | 1.026 | tINS | FR | 4 | R13C8[3][A] | key_filter0/n92_s5/F |
| 8.317 | 0.427 | tNET | RR | 1 | R13C9[2][A] | key_filter0/n100_s3/I1 |
| 9.416 | 1.099 | tINS | RF | 3 | R13C9[2][A] | key_filter0/n100_s3/F |
| 9.433 | 0.016 | tNET | FF | 1 | R13C9[0][B] | key_filter0/n102_s1/I1 |
| 10.255 | 0.822 | tINS | FF | 1 | R13C9[0][B] | key_filter0/n102_s1/F |
| 10.255 | 0.000 | tNET | FF | 1 | R13C9[0][B] | key_filter0/cnt_9_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | Clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 24.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 25.591 | 1.361 | tNET | RR | 1 | R13C9[0][B] | key_filter0/cnt_9_s0/CLK |
| 25.191 | -0.400 | tSu | 1 | R13C9[0][B] | key_filter0/cnt_9_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 20.000 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
| Arrival Data Path Delay | cell: 2.947, 63.189%; route: 1.258, 26.983%; tC2Q: 0.458, 9.828% |
| Required Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
Path18
Path Summary:
| Slack | 14.964 |
| Data Arrival Time | 10.227 |
| Data Required Time | 25.191 |
| From | key_filter1/cnt_4_s0 |
| To | key_filter1/cnt_15_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 4.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 5.591 | 1.361 | tNET | RR | 1 | R7C9[0][A] | key_filter1/cnt_4_s0/CLK |
| 6.049 | 0.458 | tC2Q | RR | 4 | R7C9[0][A] | key_filter1/cnt_4_s0/Q |
| 6.475 | 0.426 | tNET | RR | 1 | R7C8[0][B] | key_filter1/n103_s3/I0 |
| 7.536 | 1.061 | tINS | RR | 4 | R7C8[0][B] | key_filter1/n103_s3/F |
| 7.961 | 0.425 | tNET | RR | 1 | R8C8[3][A] | key_filter1/n98_s2/I2 |
| 8.763 | 0.802 | tINS | RR | 7 | R8C8[3][A] | key_filter1/n98_s2/F |
| 9.195 | 0.433 | tNET | RR | 1 | R9C8[2][A] | key_filter1/n96_s1/I0 |
| 10.227 | 1.032 | tINS | RF | 1 | R9C8[2][A] | key_filter1/n96_s1/F |
| 10.227 | 0.000 | tNET | FF | 1 | R9C8[2][A] | key_filter1/cnt_15_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | Clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 24.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 25.591 | 1.361 | tNET | RR | 1 | R9C8[2][A] | key_filter1/cnt_15_s0/CLK |
| 25.191 | -0.400 | tSu | 1 | R9C8[2][A] | key_filter1/cnt_15_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 20.000 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
| Arrival Data Path Delay | cell: 2.895, 62.441%; route: 1.283, 27.673%; tC2Q: 0.458, 9.886% |
| Required Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
Path19
Path Summary:
| Slack | 14.968 |
| Data Arrival Time | 10.224 |
| Data Required Time | 25.191 |
| From | key_filter1/cnt_4_s0 |
| To | key_filter1/cnt_16_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 4.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 5.591 | 1.361 | tNET | RR | 1 | R7C9[0][A] | key_filter1/cnt_4_s0/CLK |
| 6.049 | 0.458 | tC2Q | RR | 4 | R7C9[0][A] | key_filter1/cnt_4_s0/Q |
| 6.475 | 0.426 | tNET | RR | 1 | R7C8[0][B] | key_filter1/n103_s3/I0 |
| 7.536 | 1.061 | tINS | RR | 4 | R7C8[0][B] | key_filter1/n103_s3/F |
| 7.961 | 0.425 | tNET | RR | 1 | R8C8[3][A] | key_filter1/n98_s2/I2 |
| 8.763 | 0.802 | tINS | RR | 7 | R8C8[3][A] | key_filter1/n98_s2/F |
| 9.192 | 0.429 | tNET | RR | 1 | R9C8[0][B] | key_filter1/n95_s1/I0 |
| 10.224 | 1.032 | tINS | RF | 1 | R9C8[0][B] | key_filter1/n95_s1/F |
| 10.224 | 0.000 | tNET | FF | 1 | R9C8[0][B] | key_filter1/cnt_16_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | Clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 24.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 25.591 | 1.361 | tNET | RR | 1 | R9C8[0][B] | key_filter1/cnt_16_s0/CLK |
| 25.191 | -0.400 | tSu | 1 | R9C8[0][B] | key_filter1/cnt_16_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 20.000 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
| Arrival Data Path Delay | cell: 2.895, 62.495%; route: 1.279, 27.611%; tC2Q: 0.458, 9.894% |
| Required Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
Path20
Path Summary:
| Slack | 14.976 |
| Data Arrival Time | 10.572 |
| Data Required Time | 25.548 |
| From | key_filter0/cnt_full_s0 |
| To | key_filter0/en_cnt_s2 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 4.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 5.591 | 1.361 | tNET | RR | 1 | R13C7[0][B] | key_filter0/cnt_full_s0/CLK |
| 6.049 | 0.458 | tC2Q | RF | 8 | R13C7[0][B] | key_filter0/cnt_full_s0/Q |
| 6.885 | 0.835 | tNET | FF | 1 | R12C8[0][B] | key_filter0/en_cnt_s6/I1 |
| 7.984 | 1.099 | tINS | FF | 1 | R12C8[0][B] | key_filter0/en_cnt_s6/F |
| 7.989 | 0.005 | tNET | FF | 1 | R12C8[2][B] | key_filter0/en_cnt_s4/I2 |
| 9.050 | 1.061 | tINS | FR | 1 | R12C8[2][B] | key_filter0/en_cnt_s4/F |
| 10.572 | 1.522 | tNET | RR | 1 | R12C8[1][A] | key_filter0/en_cnt_s2/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | Clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 24.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 25.591 | 1.361 | tNET | RR | 1 | R12C8[1][A] | key_filter0/en_cnt_s2/CLK |
| 25.548 | -0.043 | tSu | 1 | R12C8[1][A] | key_filter0/en_cnt_s2 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 20.000 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
| Arrival Data Path Delay | cell: 2.160, 43.368%; route: 2.362, 47.430%; tC2Q: 0.458, 9.202% |
| Required Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
Path21
Path Summary:
| Slack | 15.008 |
| Data Arrival Time | 10.184 |
| Data Required Time | 25.191 |
| From | key_filter1/cnt_3_s0 |
| To | key_filter1/cnt_11_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 4.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 5.591 | 1.361 | tNET | RR | 1 | R6C8[2][B] | key_filter1/cnt_3_s0/CLK |
| 6.049 | 0.458 | tC2Q | RF | 2 | R6C8[2][B] | key_filter1/cnt_3_s0/Q |
| 6.388 | 0.339 | tNET | FF | 1 | R6C8[3][A] | key_filter1/n107_s2/I3 |
| 7.487 | 1.099 | tINS | FF | 7 | R6C8[3][A] | key_filter1/n107_s2/F |
| 8.319 | 0.831 | tNET | FF | 1 | R8C9[2][A] | key_filter1/n101_s2/I2 |
| 9.351 | 1.032 | tINS | FF | 2 | R8C9[2][A] | key_filter1/n101_s2/F |
| 9.362 | 0.011 | tNET | FF | 1 | R8C9[1][A] | key_filter1/n100_s1/I1 |
| 10.184 | 0.822 | tINS | FF | 1 | R8C9[1][A] | key_filter1/n100_s1/F |
| 10.184 | 0.000 | tNET | FF | 1 | R8C9[1][A] | key_filter1/cnt_11_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | Clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 24.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 25.591 | 1.361 | tNET | RR | 1 | R8C9[1][A] | key_filter1/cnt_11_s0/CLK |
| 25.191 | -0.400 | tSu | 1 | R8C9[1][A] | key_filter1/cnt_11_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 20.000 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
| Arrival Data Path Delay | cell: 2.953, 64.301%; route: 1.181, 25.719%; tC2Q: 0.458, 9.980% |
| Required Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
Path22
Path Summary:
| Slack | 15.008 |
| Data Arrival Time | 10.184 |
| Data Required Time | 25.191 |
| From | key_filter1/cnt_3_s0 |
| To | key_filter1/cnt_10_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 4.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 5.591 | 1.361 | tNET | RR | 1 | R6C8[2][B] | key_filter1/cnt_3_s0/CLK |
| 6.049 | 0.458 | tC2Q | RF | 2 | R6C8[2][B] | key_filter1/cnt_3_s0/Q |
| 6.388 | 0.339 | tNET | FF | 1 | R6C8[3][A] | key_filter1/n107_s2/I3 |
| 7.487 | 1.099 | tINS | FF | 7 | R6C8[3][A] | key_filter1/n107_s2/F |
| 8.319 | 0.831 | tNET | FF | 1 | R8C9[2][A] | key_filter1/n101_s2/I2 |
| 9.351 | 1.032 | tINS | FF | 2 | R8C9[2][A] | key_filter1/n101_s2/F |
| 9.362 | 0.011 | tNET | FF | 1 | R8C9[0][B] | key_filter1/n101_s1/I1 |
| 10.184 | 0.822 | tINS | FF | 1 | R8C9[0][B] | key_filter1/n101_s1/F |
| 10.184 | 0.000 | tNET | FF | 1 | R8C9[0][B] | key_filter1/cnt_10_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | Clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 24.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 25.591 | 1.361 | tNET | RR | 1 | R8C9[0][B] | key_filter1/cnt_10_s0/CLK |
| 25.191 | -0.400 | tSu | 1 | R8C9[0][B] | key_filter1/cnt_10_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 20.000 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
| Arrival Data Path Delay | cell: 2.953, 64.301%; route: 1.181, 25.719%; tC2Q: 0.458, 9.980% |
| Required Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
Path23
Path Summary:
| Slack | 15.088 |
| Data Arrival Time | 10.103 |
| Data Required Time | 25.191 |
| From | key_filter1/cnt_4_s0 |
| To | key_filter1/cnt_12_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 4.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 5.591 | 1.361 | tNET | RR | 1 | R7C9[0][A] | key_filter1/cnt_4_s0/CLK |
| 6.049 | 0.458 | tC2Q | RR | 4 | R7C9[0][A] | key_filter1/cnt_4_s0/Q |
| 6.475 | 0.426 | tNET | RR | 1 | R7C8[0][B] | key_filter1/n103_s3/I0 |
| 7.536 | 1.061 | tINS | RR | 4 | R7C8[0][B] | key_filter1/n103_s3/F |
| 7.961 | 0.425 | tNET | RR | 1 | R8C8[1][B] | key_filter1/n103_s2/I1 |
| 8.993 | 1.032 | tINS | RF | 2 | R8C8[1][B] | key_filter1/n103_s2/F |
| 9.004 | 0.011 | tNET | FF | 1 | R8C8[0][B] | key_filter1/n99_s1/I0 |
| 10.103 | 1.099 | tINS | FF | 1 | R8C8[0][B] | key_filter1/n99_s1/F |
| 10.103 | 0.000 | tNET | FF | 1 | R8C8[0][B] | key_filter1/cnt_12_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | Clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 24.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 25.591 | 1.361 | tNET | RR | 1 | R8C8[0][B] | key_filter1/cnt_12_s0/CLK |
| 25.191 | -0.400 | tSu | 1 | R8C8[0][B] | key_filter1/cnt_12_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 20.000 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
| Arrival Data Path Delay | cell: 3.192, 70.749%; route: 0.861, 19.092%; tC2Q: 0.458, 10.159% |
| Required Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
Path24
Path Summary:
| Slack | 15.147 |
| Data Arrival Time | 10.044 |
| Data Required Time | 25.191 |
| From | key_filter1/cnt_13_s0 |
| To | key_filter1/cnt_19_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 4.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 5.591 | 1.361 | tNET | RR | 1 | R9C9[0][B] | key_filter1/cnt_13_s0/CLK |
| 6.049 | 0.458 | tC2Q | RF | 6 | R9C9[0][B] | key_filter1/cnt_13_s0/Q |
| 6.895 | 0.846 | tNET | FF | 1 | R8C8[2][A] | key_filter1/n94_s2/I0 |
| 7.956 | 1.061 | tINS | FR | 3 | R8C8[2][A] | key_filter1/n94_s2/F |
| 8.381 | 0.425 | tNET | RR | 1 | R9C8[2][B] | key_filter1/n92_s2/I2 |
| 9.007 | 0.626 | tINS | RF | 1 | R9C8[2][B] | key_filter1/n92_s2/F |
| 9.012 | 0.005 | tNET | FF | 1 | R9C8[1][B] | key_filter1/n92_s1/I1 |
| 10.044 | 1.032 | tINS | FF | 1 | R9C8[1][B] | key_filter1/n92_s1/F |
| 10.044 | 0.000 | tNET | FF | 1 | R9C8[1][B] | key_filter1/cnt_19_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | Clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 24.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 25.591 | 1.361 | tNET | RR | 1 | R9C8[1][B] | key_filter1/cnt_19_s0/CLK |
| 25.191 | -0.400 | tSu | 1 | R9C8[1][B] | key_filter1/cnt_19_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 20.000 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
| Arrival Data Path Delay | cell: 2.719, 61.058%; route: 1.276, 28.650%; tC2Q: 0.458, 10.292% |
| Required Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
Path25
Path Summary:
| Slack | 15.174 |
| Data Arrival Time | 10.017 |
| Data Required Time | 25.191 |
| From | key_filter1/cnt_4_s0 |
| To | key_filter1/cnt_17_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 4.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 5.591 | 1.361 | tNET | RR | 1 | R7C9[0][A] | key_filter1/cnt_4_s0/CLK |
| 6.049 | 0.458 | tC2Q | RR | 4 | R7C9[0][A] | key_filter1/cnt_4_s0/Q |
| 6.475 | 0.426 | tNET | RR | 1 | R7C8[0][B] | key_filter1/n103_s3/I0 |
| 7.536 | 1.061 | tINS | RR | 4 | R7C8[0][B] | key_filter1/n103_s3/F |
| 7.961 | 0.425 | tNET | RR | 1 | R8C8[3][A] | key_filter1/n98_s2/I2 |
| 8.763 | 0.802 | tINS | RR | 7 | R8C8[3][A] | key_filter1/n98_s2/F |
| 9.195 | 0.433 | tNET | RR | 1 | R9C8[1][A] | key_filter1/n94_s1/I0 |
| 10.017 | 0.822 | tINS | RF | 1 | R9C8[1][A] | key_filter1/n94_s1/F |
| 10.017 | 0.000 | tNET | FF | 1 | R9C8[1][A] | key_filter1/cnt_17_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 20.000 | 20.000 | active clock edge time | ||||
| 20.000 | 0.000 | Clk | ||||
| 20.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 24.230 | 4.230 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 25.591 | 1.361 | tNET | RR | 1 | R9C8[1][A] | key_filter1/cnt_17_s0/CLK |
| 25.191 | -0.400 | tSu | 1 | R9C8[1][A] | key_filter1/cnt_17_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 20.000 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
| Arrival Data Path Delay | cell: 2.685, 60.660%; route: 1.283, 28.986%; tC2Q: 0.458, 10.355% |
| Required Clock Path Delay | cell: 4.230, 75.653%; route: 1.361, 24.347% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 0.708 |
| Data Arrival Time | 4.800 |
| Data Required Time | 4.093 |
| From | key_filter1/key_flag_s5 |
| To | key_filter1/key_flag_s5 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R8C7[0][A] | key_filter1/key_flag_s5/CLK |
| 4.426 | 0.333 | tC2Q | RR | 2 | R8C7[0][A] | key_filter1/key_flag_s5/Q |
| 4.428 | 0.002 | tNET | RR | 1 | R8C7[0][A] | key_filter1/n27_s4/I1 |
| 4.800 | 0.372 | tINS | RF | 1 | R8C7[0][A] | key_filter1/n27_s4/F |
| 4.800 | 0.000 | tNET | FF | 1 | R8C7[0][A] | key_filter1/key_flag_s5/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R8C7[0][A] | key_filter1/key_flag_s5/CLK |
| 4.093 | 0.000 | tHld | 1 | R8C7[0][A] | key_filter1/key_flag_s5 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
| Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101% |
| Required Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
Path2
Path Summary:
| Slack | 0.708 |
| Data Arrival Time | 4.800 |
| Data Required Time | 4.093 |
| From | key_filter0/key_state_s5 |
| To | key_filter0/key_state_s5 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R12C6[0][A] | key_filter0/key_state_s5/CLK |
| 4.426 | 0.333 | tC2Q | RR | 3 | R12C6[0][A] | key_filter0/key_state_s5/Q |
| 4.428 | 0.002 | tNET | RR | 1 | R12C6[0][A] | key_filter0/n52_s9/I3 |
| 4.800 | 0.372 | tINS | RF | 1 | R12C6[0][A] | key_filter0/n52_s9/F |
| 4.800 | 0.000 | tNET | FF | 1 | R12C6[0][A] | key_filter0/key_state_s5/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R12C6[0][A] | key_filter0/key_state_s5/CLK |
| 4.093 | 0.000 | tHld | 1 | R12C6[0][A] | key_filter0/key_state_s5 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
| Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101% |
| Required Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
Path3
Path Summary:
| Slack | 0.708 |
| Data Arrival Time | 4.800 |
| Data Required Time | 4.093 |
| From | key_filter0/cnt_0_s0 |
| To | key_filter0/cnt_0_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R12C7[1][A] | key_filter0/cnt_0_s0/CLK |
| 4.426 | 0.333 | tC2Q | RR | 5 | R12C7[1][A] | key_filter0/cnt_0_s0/Q |
| 4.428 | 0.002 | tNET | RR | 1 | R12C7[1][A] | key_filter0/n111_s2/I0 |
| 4.800 | 0.372 | tINS | RF | 1 | R12C7[1][A] | key_filter0/n111_s2/F |
| 4.800 | 0.000 | tNET | FF | 1 | R12C7[1][A] | key_filter0/cnt_0_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R12C7[1][A] | key_filter0/cnt_0_s0/CLK |
| 4.093 | 0.000 | tHld | 1 | R12C7[1][A] | key_filter0/cnt_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
| Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101% |
| Required Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
Path4
Path Summary:
| Slack | 0.708 |
| Data Arrival Time | 4.800 |
| Data Required Time | 4.093 |
| From | key_filter0/cnt_3_s0 |
| To | key_filter0/cnt_3_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R12C7[0][A] | key_filter0/cnt_3_s0/CLK |
| 4.426 | 0.333 | tC2Q | RR | 2 | R12C7[0][A] | key_filter0/cnt_3_s0/Q |
| 4.428 | 0.002 | tNET | RR | 1 | R12C7[0][A] | key_filter0/n108_s1/I1 |
| 4.800 | 0.372 | tINS | RF | 1 | R12C7[0][A] | key_filter0/n108_s1/F |
| 4.800 | 0.000 | tNET | FF | 1 | R12C7[0][A] | key_filter0/cnt_3_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R12C7[0][A] | key_filter0/cnt_3_s0/CLK |
| 4.093 | 0.000 | tHld | 1 | R12C7[0][A] | key_filter0/cnt_3_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
| Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101% |
| Required Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
Path5
Path Summary:
| Slack | 0.709 |
| Data Arrival Time | 4.802 |
| Data Required Time | 4.093 |
| From | led_ctrl0/led_r_0_s1 |
| To | led_ctrl0/led_r_0_s1 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R8C6[0][A] | led_ctrl0/led_r_0_s1/CLK |
| 4.426 | 0.333 | tC2Q | RR | 3 | R8C6[0][A] | led_ctrl0/led_r_0_s1/Q |
| 4.430 | 0.004 | tNET | RR | 1 | R8C6[0][A] | led_ctrl0/n18_s1/I0 |
| 4.802 | 0.372 | tINS | RF | 1 | R8C6[0][A] | led_ctrl0/n18_s1/F |
| 4.802 | 0.000 | tNET | FF | 1 | R8C6[0][A] | led_ctrl0/led_r_0_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R8C6[0][A] | led_ctrl0/led_r_0_s1/CLK |
| 4.093 | 0.000 | tHld | 1 | R8C6[0][A] | led_ctrl0/led_r_0_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
| Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
| Required Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
Path6
Path Summary:
| Slack | 0.709 |
| Data Arrival Time | 4.802 |
| Data Required Time | 4.093 |
| From | key_filter1/cnt_2_s0 |
| To | key_filter1/cnt_2_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R6C8[1][A] | key_filter1/cnt_2_s0/CLK |
| 4.426 | 0.333 | tC2Q | RR | 3 | R6C8[1][A] | key_filter1/cnt_2_s0/Q |
| 4.430 | 0.004 | tNET | RR | 1 | R6C8[1][A] | key_filter1/n109_s1/I2 |
| 4.802 | 0.372 | tINS | RF | 1 | R6C8[1][A] | key_filter1/n109_s1/F |
| 4.802 | 0.000 | tNET | FF | 1 | R6C8[1][A] | key_filter1/cnt_2_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R6C8[1][A] | key_filter1/cnt_2_s0/CLK |
| 4.093 | 0.000 | tHld | 1 | R6C8[1][A] | key_filter1/cnt_2_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
| Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
| Required Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
Path7
Path Summary:
| Slack | 0.709 |
| Data Arrival Time | 4.802 |
| Data Required Time | 4.093 |
| From | key_filter1/cnt_4_s0 |
| To | key_filter1/cnt_4_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R7C9[0][A] | key_filter1/cnt_4_s0/CLK |
| 4.426 | 0.333 | tC2Q | RR | 4 | R7C9[0][A] | key_filter1/cnt_4_s0/Q |
| 4.430 | 0.004 | tNET | RR | 1 | R7C9[0][A] | key_filter1/n107_s1/I0 |
| 4.802 | 0.372 | tINS | RF | 1 | R7C9[0][A] | key_filter1/n107_s1/F |
| 4.802 | 0.000 | tNET | FF | 1 | R7C9[0][A] | key_filter1/cnt_4_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R7C9[0][A] | key_filter1/cnt_4_s0/CLK |
| 4.093 | 0.000 | tHld | 1 | R7C9[0][A] | key_filter1/cnt_4_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
| Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
| Required Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
Path8
Path Summary:
| Slack | 0.709 |
| Data Arrival Time | 4.802 |
| Data Required Time | 4.093 |
| From | key_filter1/cnt_7_s0 |
| To | key_filter1/cnt_7_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R7C8[1][A] | key_filter1/cnt_7_s0/CLK |
| 4.426 | 0.333 | tC2Q | RR | 3 | R7C8[1][A] | key_filter1/cnt_7_s0/Q |
| 4.430 | 0.004 | tNET | RR | 1 | R7C8[1][A] | key_filter1/n104_s1/I2 |
| 4.802 | 0.372 | tINS | RF | 1 | R7C8[1][A] | key_filter1/n104_s1/F |
| 4.802 | 0.000 | tNET | FF | 1 | R7C8[1][A] | key_filter1/cnt_7_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R7C8[1][A] | key_filter1/cnt_7_s0/CLK |
| 4.093 | 0.000 | tHld | 1 | R7C8[1][A] | key_filter1/cnt_7_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
| Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
| Required Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
Path9
Path Summary:
| Slack | 0.709 |
| Data Arrival Time | 4.802 |
| Data Required Time | 4.093 |
| From | key_filter1/cnt_11_s0 |
| To | key_filter1/cnt_11_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R8C9[1][A] | key_filter1/cnt_11_s0/CLK |
| 4.426 | 0.333 | tC2Q | RR | 3 | R8C9[1][A] | key_filter1/cnt_11_s0/Q |
| 4.430 | 0.004 | tNET | RR | 1 | R8C9[1][A] | key_filter1/n100_s1/I2 |
| 4.802 | 0.372 | tINS | RF | 1 | R8C9[1][A] | key_filter1/n100_s1/F |
| 4.802 | 0.000 | tNET | FF | 1 | R8C9[1][A] | key_filter1/cnt_11_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R8C9[1][A] | key_filter1/cnt_11_s0/CLK |
| 4.093 | 0.000 | tHld | 1 | R8C9[1][A] | key_filter1/cnt_11_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
| Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
| Required Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
Path10
Path Summary:
| Slack | 0.709 |
| Data Arrival Time | 4.802 |
| Data Required Time | 4.093 |
| From | key_filter1/cnt_14_s0 |
| To | key_filter1/cnt_14_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R8C8[1][A] | key_filter1/cnt_14_s0/CLK |
| 4.426 | 0.333 | tC2Q | RR | 5 | R8C8[1][A] | key_filter1/cnt_14_s0/Q |
| 4.430 | 0.004 | tNET | RR | 1 | R8C8[1][A] | key_filter1/n97_s1/I2 |
| 4.802 | 0.372 | tINS | RF | 1 | R8C8[1][A] | key_filter1/n97_s1/F |
| 4.802 | 0.000 | tNET | FF | 1 | R8C8[1][A] | key_filter1/cnt_14_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R8C8[1][A] | key_filter1/cnt_14_s0/CLK |
| 4.093 | 0.000 | tHld | 1 | R8C8[1][A] | key_filter1/cnt_14_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
| Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
| Required Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
Path11
Path Summary:
| Slack | 0.709 |
| Data Arrival Time | 4.802 |
| Data Required Time | 4.093 |
| From | key_filter1/cnt_17_s0 |
| To | key_filter1/cnt_17_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R9C8[1][A] | key_filter1/cnt_17_s0/CLK |
| 4.426 | 0.333 | tC2Q | RR | 4 | R9C8[1][A] | key_filter1/cnt_17_s0/Q |
| 4.430 | 0.004 | tNET | RR | 1 | R9C8[1][A] | key_filter1/n94_s1/I2 |
| 4.802 | 0.372 | tINS | RF | 1 | R9C8[1][A] | key_filter1/n94_s1/F |
| 4.802 | 0.000 | tNET | FF | 1 | R9C8[1][A] | key_filter1/cnt_17_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R9C8[1][A] | key_filter1/cnt_17_s0/CLK |
| 4.093 | 0.000 | tHld | 1 | R9C8[1][A] | key_filter1/cnt_17_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
| Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
| Required Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
Path12
Path Summary:
| Slack | 0.709 |
| Data Arrival Time | 4.802 |
| Data Required Time | 4.093 |
| From | key_filter1/cnt_18_s0 |
| To | key_filter1/cnt_18_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R8C7[1][A] | key_filter1/cnt_18_s0/CLK |
| 4.426 | 0.333 | tC2Q | RR | 3 | R8C7[1][A] | key_filter1/cnt_18_s0/Q |
| 4.430 | 0.004 | tNET | RR | 1 | R8C7[1][A] | key_filter1/n93_s1/I2 |
| 4.802 | 0.372 | tINS | RF | 1 | R8C7[1][A] | key_filter1/n93_s1/F |
| 4.802 | 0.000 | tNET | FF | 1 | R8C7[1][A] | key_filter1/cnt_18_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R8C7[1][A] | key_filter1/cnt_18_s0/CLK |
| 4.093 | 0.000 | tHld | 1 | R8C7[1][A] | key_filter1/cnt_18_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
| Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
| Required Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
Path13
Path Summary:
| Slack | 0.709 |
| Data Arrival Time | 4.802 |
| Data Required Time | 4.093 |
| From | key_filter0/cnt_5_s0 |
| To | key_filter0/cnt_5_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R12C9[0][A] | key_filter0/cnt_5_s0/CLK |
| 4.426 | 0.333 | tC2Q | RR | 3 | R12C9[0][A] | key_filter0/cnt_5_s0/Q |
| 4.430 | 0.004 | tNET | RR | 1 | R12C9[0][A] | key_filter0/n106_s1/I2 |
| 4.802 | 0.372 | tINS | RF | 1 | R12C9[0][A] | key_filter0/n106_s1/F |
| 4.802 | 0.000 | tNET | FF | 1 | R12C9[0][A] | key_filter0/cnt_5_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R12C9[0][A] | key_filter0/cnt_5_s0/CLK |
| 4.093 | 0.000 | tHld | 1 | R12C9[0][A] | key_filter0/cnt_5_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
| Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
| Required Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
Path14
Path Summary:
| Slack | 0.709 |
| Data Arrival Time | 4.802 |
| Data Required Time | 4.093 |
| From | key_filter0/cnt_12_s0 |
| To | key_filter0/cnt_12_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R14C8[0][A] | key_filter0/cnt_12_s0/CLK |
| 4.426 | 0.333 | tC2Q | RR | 3 | R14C8[0][A] | key_filter0/cnt_12_s0/Q |
| 4.430 | 0.004 | tNET | RR | 1 | R14C8[0][A] | key_filter0/n99_s1/I1 |
| 4.802 | 0.372 | tINS | RF | 1 | R14C8[0][A] | key_filter0/n99_s1/F |
| 4.802 | 0.000 | tNET | FF | 1 | R14C8[0][A] | key_filter0/cnt_12_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R14C8[0][A] | key_filter0/cnt_12_s0/CLK |
| 4.093 | 0.000 | tHld | 1 | R14C8[0][A] | key_filter0/cnt_12_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
| Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
| Required Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
Path15
Path Summary:
| Slack | 0.709 |
| Data Arrival Time | 4.802 |
| Data Required Time | 4.093 |
| From | key_filter0/cnt_16_s0 |
| To | key_filter0/cnt_16_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R13C8[1][A] | key_filter0/cnt_16_s0/CLK |
| 4.426 | 0.333 | tC2Q | RR | 3 | R13C8[1][A] | key_filter0/cnt_16_s0/Q |
| 4.430 | 0.004 | tNET | RR | 1 | R13C8[1][A] | key_filter0/n95_s1/I2 |
| 4.802 | 0.372 | tINS | RF | 1 | R13C8[1][A] | key_filter0/n95_s1/F |
| 4.802 | 0.000 | tNET | FF | 1 | R13C8[1][A] | key_filter0/cnt_16_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R13C8[1][A] | key_filter0/cnt_16_s0/CLK |
| 4.093 | 0.000 | tHld | 1 | R13C8[1][A] | key_filter0/cnt_16_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
| Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
| Required Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
Path16
Path Summary:
| Slack | 0.709 |
| Data Arrival Time | 4.802 |
| Data Required Time | 4.093 |
| From | key_filter0/cnt_17_s0 |
| To | key_filter0/cnt_17_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R13C8[0][A] | key_filter0/cnt_17_s0/CLK |
| 4.426 | 0.333 | tC2Q | RR | 4 | R13C8[0][A] | key_filter0/cnt_17_s0/Q |
| 4.430 | 0.004 | tNET | RR | 1 | R13C8[0][A] | key_filter0/n94_s1/I2 |
| 4.802 | 0.372 | tINS | RF | 1 | R13C8[0][A] | key_filter0/n94_s1/F |
| 4.802 | 0.000 | tNET | FF | 1 | R13C8[0][A] | key_filter0/cnt_17_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R13C8[0][A] | key_filter0/cnt_17_s0/CLK |
| 4.093 | 0.000 | tHld | 1 | R13C8[0][A] | key_filter0/cnt_17_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
| Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
| Required Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
Path17
Path Summary:
| Slack | 0.710 |
| Data Arrival Time | 4.803 |
| Data Required Time | 4.093 |
| From | key_filter1/state.IDEL_s0 |
| To | key_filter1/state.IDEL_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R6C7[0][A] | key_filter1/state.IDEL_s0/CLK |
| 4.426 | 0.333 | tC2Q | RR | 7 | R6C7[0][A] | key_filter1/state.IDEL_s0/Q |
| 4.431 | 0.005 | tNET | RR | 1 | R6C7[0][A] | key_filter1/n52_s6/I1 |
| 4.803 | 0.372 | tINS | RF | 1 | R6C7[0][A] | key_filter1/n52_s6/F |
| 4.803 | 0.000 | tNET | FF | 1 | R6C7[0][A] | key_filter1/state.IDEL_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R6C7[0][A] | key_filter1/state.IDEL_s0/CLK |
| 4.093 | 0.000 | tHld | 1 | R6C7[0][A] | key_filter1/state.IDEL_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
| Arrival Data Path Delay | cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945% |
| Required Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
Path18
Path Summary:
| Slack | 0.710 |
| Data Arrival Time | 4.803 |
| Data Required Time | 4.093 |
| From | key_filter0/cnt_6_s0 |
| To | key_filter0/cnt_6_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R13C6[0][A] | key_filter0/cnt_6_s0/CLK |
| 4.426 | 0.333 | tC2Q | RR | 4 | R13C6[0][A] | key_filter0/cnt_6_s0/Q |
| 4.431 | 0.005 | tNET | RR | 1 | R13C6[0][A] | key_filter0/n105_s1/I0 |
| 4.803 | 0.372 | tINS | RF | 1 | R13C6[0][A] | key_filter0/n105_s1/F |
| 4.803 | 0.000 | tNET | FF | 1 | R13C6[0][A] | key_filter0/cnt_6_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R13C6[0][A] | key_filter0/cnt_6_s0/CLK |
| 4.093 | 0.000 | tHld | 1 | R13C6[0][A] | key_filter0/cnt_6_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
| Arrival Data Path Delay | cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945% |
| Required Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
Path19
Path Summary:
| Slack | 0.711 |
| Data Arrival Time | 4.804 |
| Data Required Time | 4.093 |
| From | key_filter1/cnt_8_s0 |
| To | key_filter1/cnt_8_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R8C9[0][A] | key_filter1/cnt_8_s0/CLK |
| 4.426 | 0.333 | tC2Q | RR | 5 | R8C9[0][A] | key_filter1/cnt_8_s0/Q |
| 4.432 | 0.006 | tNET | RR | 1 | R8C9[0][A] | key_filter1/n103_s4/I0 |
| 4.804 | 0.372 | tINS | RF | 1 | R8C9[0][A] | key_filter1/n103_s4/F |
| 4.804 | 0.000 | tNET | FF | 1 | R8C9[0][A] | key_filter1/cnt_8_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R8C9[0][A] | key_filter1/cnt_8_s0/CLK |
| 4.093 | 0.000 | tHld | 1 | R8C9[0][A] | key_filter1/cnt_8_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
| Arrival Data Path Delay | cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867% |
| Required Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
Path20
Path Summary:
| Slack | 0.711 |
| Data Arrival Time | 4.804 |
| Data Required Time | 4.093 |
| From | key_filter0/state.DOWN_s0 |
| To | key_filter0/state.DOWN_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R11C7[0][A] | key_filter0/state.DOWN_s0/CLK |
| 4.426 | 0.333 | tC2Q | RR | 6 | R11C7[0][A] | key_filter0/state.DOWN_s0/Q |
| 4.432 | 0.006 | tNET | RR | 1 | R11C7[0][A] | key_filter0/n55_s5/I1 |
| 4.804 | 0.372 | tINS | RF | 1 | R11C7[0][A] | key_filter0/n55_s5/F |
| 4.804 | 0.000 | tNET | FF | 1 | R11C7[0][A] | key_filter0/state.DOWN_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R11C7[0][A] | key_filter0/state.DOWN_s0/CLK |
| 4.093 | 0.000 | tHld | 1 | R11C7[0][A] | key_filter0/state.DOWN_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
| Arrival Data Path Delay | cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867% |
| Required Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
Path21
Path Summary:
| Slack | 0.892 |
| Data Arrival Time | 4.984 |
| Data Required Time | 4.093 |
| From | key_filter1/cnt_15_s0 |
| To | key_filter1/cnt_15_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R9C8[2][A] | key_filter1/cnt_15_s0/CLK |
| 4.426 | 0.333 | tC2Q | RR | 4 | R9C8[2][A] | key_filter1/cnt_15_s0/Q |
| 4.428 | 0.002 | tNET | RR | 1 | R9C8[2][A] | key_filter1/n96_s1/I2 |
| 4.984 | 0.556 | tINS | RR | 1 | R9C8[2][A] | key_filter1/n96_s1/F |
| 4.984 | 0.000 | tNET | RR | 1 | R9C8[2][A] | key_filter1/cnt_15_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R9C8[2][A] | key_filter1/cnt_15_s0/CLK |
| 4.093 | 0.000 | tHld | 1 | R9C8[2][A] | key_filter1/cnt_15_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
| Arrival Data Path Delay | cell: 0.556, 62.353%; route: 0.002, 0.265%; tC2Q: 0.333, 37.382% |
| Required Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
Path22
Path Summary:
| Slack | 0.893 |
| Data Arrival Time | 4.986 |
| Data Required Time | 4.093 |
| From | key_filter1/cnt_5_s0 |
| To | key_filter1/cnt_5_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R7C8[2][A] | key_filter1/cnt_5_s0/CLK |
| 4.426 | 0.333 | tC2Q | RR | 3 | R7C8[2][A] | key_filter1/cnt_5_s0/Q |
| 4.430 | 0.004 | tNET | RR | 1 | R7C8[2][A] | key_filter1/n106_s1/I2 |
| 4.986 | 0.556 | tINS | RR | 1 | R7C8[2][A] | key_filter1/n106_s1/F |
| 4.986 | 0.000 | tNET | RR | 1 | R7C8[2][A] | key_filter1/cnt_5_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R7C8[2][A] | key_filter1/cnt_5_s0/CLK |
| 4.093 | 0.000 | tHld | 1 | R7C8[2][A] | key_filter1/cnt_5_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
| Arrival Data Path Delay | cell: 0.556, 62.271%; route: 0.004, 0.397%; tC2Q: 0.333, 37.333% |
| Required Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
Path23
Path Summary:
| Slack | 0.895 |
| Data Arrival Time | 4.988 |
| Data Required Time | 4.093 |
| From | key_filter0/cnt_13_s0 |
| To | key_filter0/cnt_13_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R13C8[2][A] | key_filter0/cnt_13_s0/CLK |
| 4.426 | 0.333 | tC2Q | RR | 6 | R13C8[2][A] | key_filter0/cnt_13_s0/Q |
| 4.432 | 0.006 | tNET | RR | 1 | R13C8[2][A] | key_filter0/n98_s1/I0 |
| 4.988 | 0.556 | tINS | RR | 1 | R13C8[2][A] | key_filter0/n98_s1/F |
| 4.988 | 0.000 | tNET | RR | 1 | R13C8[2][A] | key_filter0/cnt_13_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R13C8[2][A] | key_filter0/cnt_13_s0/CLK |
| 4.093 | 0.000 | tHld | 1 | R13C8[2][A] | key_filter0/cnt_13_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
| Arrival Data Path Delay | cell: 0.556, 62.107%; route: 0.006, 0.659%; tC2Q: 0.333, 37.234% |
| Required Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
Path24
Path Summary:
| Slack | 0.895 |
| Data Arrival Time | 4.988 |
| Data Required Time | 4.093 |
| From | key_filter1/state.DOWN_s0 |
| To | key_filter1/state.DOWN_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R8C7[2][A] | key_filter1/state.DOWN_s0/CLK |
| 4.426 | 0.333 | tC2Q | RR | 6 | R8C7[2][A] | key_filter1/state.DOWN_s0/Q |
| 4.432 | 0.006 | tNET | RR | 1 | R8C7[2][A] | key_filter1/n55_s5/I1 |
| 4.988 | 0.556 | tINS | RR | 1 | R8C7[2][A] | key_filter1/n55_s5/F |
| 4.988 | 0.000 | tNET | RR | 1 | R8C7[2][A] | key_filter1/state.DOWN_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R8C7[2][A] | key_filter1/state.DOWN_s0/CLK |
| 4.093 | 0.000 | tHld | 1 | R8C7[2][A] | key_filter1/state.DOWN_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
| Arrival Data Path Delay | cell: 0.556, 62.107%; route: 0.006, 0.659%; tC2Q: 0.333, 37.234% |
| Required Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
Path25
Path Summary:
| Slack | 0.946 |
| Data Arrival Time | 5.039 |
| Data Required Time | 4.093 |
| From | key_filter0/cnt_6_s0 |
| To | key_filter0/cnt_7_s0 |
| Launch Clk | Clk:[R] |
| Latch Clk | Clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R13C6[0][A] | key_filter0/cnt_6_s0/CLK |
| 4.426 | 0.333 | tC2Q | RF | 4 | R13C6[0][A] | key_filter0/cnt_6_s0/Q |
| 4.667 | 0.241 | tNET | FF | 1 | R13C6[1][B] | key_filter0/n104_s1/I0 |
| 5.039 | 0.372 | tINS | FF | 1 | R13C6[1][B] | key_filter0/n104_s1/F |
| 5.039 | 0.000 | tNET | FF | 1 | R13C6[1][B] | key_filter0/cnt_7_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | Clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOT13[A] | Clk_ibuf/I |
| 3.126 | 3.126 | tINS | RR | 66 | IOT13[A] | Clk_ibuf/O |
| 4.093 | 0.966 | tNET | RR | 1 | R13C6[1][B] | key_filter0/cnt_7_s0/CLK |
| 4.093 | 0.000 | tHld | 1 | R13C6[1][B] | key_filter0/cnt_7_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
| Arrival Data Path Delay | cell: 0.372, 39.312%; route: 0.241, 25.462%; tC2Q: 0.333, 35.226% |
| Required Clock Path Delay | cell: 3.126, 76.388%; route: 0.966, 23.612% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
No recovery paths to report!
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
No removal paths to report!
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
| Slack: | 6.521 |
| Actual Width: | 7.771 |
| Required Width: | 1.250 |
| Type: | High Pulse Width |
| Clock: | Clk |
| Objects: | key_filter0/key_in_sb_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||
| 0.000 | 0.000 | Clk | ||
| 0.000 | 0.000 | tCL | RR | Clk_ibuf/I |
| 4.230 | 4.230 | tINS | RR | Clk_ibuf/O |
| 5.591 | 1.361 | tNET | RR | key_filter0/key_in_sb_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | Clk | ||
| 10.000 | 0.000 | tCL | FF | Clk_ibuf/I |
| 12.140 | 2.140 | tINS | FF | Clk_ibuf/O |
| 13.362 | 1.222 | tNET | FF | key_filter0/key_in_sb_s0/CLK |
MPW2
MPW Summary:
| Slack: | 6.521 |
| Actual Width: | 7.771 |
| Required Width: | 1.250 |
| Type: | High Pulse Width |
| Clock: | Clk |
| Objects: | key_filter0/key_tmpa_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||
| 0.000 | 0.000 | Clk | ||
| 0.000 | 0.000 | tCL | RR | Clk_ibuf/I |
| 4.230 | 4.230 | tINS | RR | Clk_ibuf/O |
| 5.591 | 1.361 | tNET | RR | key_filter0/key_tmpa_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | Clk | ||
| 10.000 | 0.000 | tCL | FF | Clk_ibuf/I |
| 12.140 | 2.140 | tINS | FF | Clk_ibuf/O |
| 13.362 | 1.222 | tNET | FF | key_filter0/key_tmpa_s0/CLK |
MPW3
MPW Summary:
| Slack: | 6.521 |
| Actual Width: | 7.771 |
| Required Width: | 1.250 |
| Type: | High Pulse Width |
| Clock: | Clk |
| Objects: | key_filter0/state.DOWN_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||
| 0.000 | 0.000 | Clk | ||
| 0.000 | 0.000 | tCL | RR | Clk_ibuf/I |
| 4.230 | 4.230 | tINS | RR | Clk_ibuf/O |
| 5.591 | 1.361 | tNET | RR | key_filter0/state.DOWN_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | Clk | ||
| 10.000 | 0.000 | tCL | FF | Clk_ibuf/I |
| 12.140 | 2.140 | tINS | FF | Clk_ibuf/O |
| 13.362 | 1.222 | tNET | FF | key_filter0/state.DOWN_s0/CLK |
MPW4
MPW Summary:
| Slack: | 6.521 |
| Actual Width: | 7.771 |
| Required Width: | 1.250 |
| Type: | High Pulse Width |
| Clock: | Clk |
| Objects: | key_filter0/cnt_16_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||
| 0.000 | 0.000 | Clk | ||
| 0.000 | 0.000 | tCL | RR | Clk_ibuf/I |
| 4.230 | 4.230 | tINS | RR | Clk_ibuf/O |
| 5.591 | 1.361 | tNET | RR | key_filter0/cnt_16_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | Clk | ||
| 10.000 | 0.000 | tCL | FF | Clk_ibuf/I |
| 12.140 | 2.140 | tINS | FF | Clk_ibuf/O |
| 13.362 | 1.222 | tNET | FF | key_filter0/cnt_16_s0/CLK |
MPW5
MPW Summary:
| Slack: | 6.521 |
| Actual Width: | 7.771 |
| Required Width: | 1.250 |
| Type: | High Pulse Width |
| Clock: | Clk |
| Objects: | key_filter0/cnt_8_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||
| 0.000 | 0.000 | Clk | ||
| 0.000 | 0.000 | tCL | RR | Clk_ibuf/I |
| 4.230 | 4.230 | tINS | RR | Clk_ibuf/O |
| 5.591 | 1.361 | tNET | RR | key_filter0/cnt_8_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | Clk | ||
| 10.000 | 0.000 | tCL | FF | Clk_ibuf/I |
| 12.140 | 2.140 | tINS | FF | Clk_ibuf/O |
| 13.362 | 1.222 | tNET | FF | key_filter0/cnt_8_s0/CLK |
MPW6
MPW Summary:
| Slack: | 6.521 |
| Actual Width: | 7.771 |
| Required Width: | 1.250 |
| Type: | High Pulse Width |
| Clock: | Clk |
| Objects: | key_filter0/key_state_s5 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||
| 0.000 | 0.000 | Clk | ||
| 0.000 | 0.000 | tCL | RR | Clk_ibuf/I |
| 4.230 | 4.230 | tINS | RR | Clk_ibuf/O |
| 5.591 | 1.361 | tNET | RR | key_filter0/key_state_s5/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | Clk | ||
| 10.000 | 0.000 | tCL | FF | Clk_ibuf/I |
| 12.140 | 2.140 | tINS | FF | Clk_ibuf/O |
| 13.362 | 1.222 | tNET | FF | key_filter0/key_state_s5/CLK |
MPW7
MPW Summary:
| Slack: | 6.521 |
| Actual Width: | 7.771 |
| Required Width: | 1.250 |
| Type: | High Pulse Width |
| Clock: | Clk |
| Objects: | key_filter1/key_state_s5 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||
| 0.000 | 0.000 | Clk | ||
| 0.000 | 0.000 | tCL | RR | Clk_ibuf/I |
| 4.230 | 4.230 | tINS | RR | Clk_ibuf/O |
| 5.591 | 1.361 | tNET | RR | key_filter1/key_state_s5/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | Clk | ||
| 10.000 | 0.000 | tCL | FF | Clk_ibuf/I |
| 12.140 | 2.140 | tINS | FF | Clk_ibuf/O |
| 13.362 | 1.222 | tNET | FF | key_filter1/key_state_s5/CLK |
MPW8
MPW Summary:
| Slack: | 6.521 |
| Actual Width: | 7.771 |
| Required Width: | 1.250 |
| Type: | High Pulse Width |
| Clock: | Clk |
| Objects: | key_filter1/key_flag_s5 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||
| 0.000 | 0.000 | Clk | ||
| 0.000 | 0.000 | tCL | RR | Clk_ibuf/I |
| 4.230 | 4.230 | tINS | RR | Clk_ibuf/O |
| 5.591 | 1.361 | tNET | RR | key_filter1/key_flag_s5/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | Clk | ||
| 10.000 | 0.000 | tCL | FF | Clk_ibuf/I |
| 12.140 | 2.140 | tINS | FF | Clk_ibuf/O |
| 13.362 | 1.222 | tNET | FF | key_filter1/key_flag_s5/CLK |
MPW9
MPW Summary:
| Slack: | 6.521 |
| Actual Width: | 7.771 |
| Required Width: | 1.250 |
| Type: | High Pulse Width |
| Clock: | Clk |
| Objects: | key_filter0/key_flag_s5 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||
| 0.000 | 0.000 | Clk | ||
| 0.000 | 0.000 | tCL | RR | Clk_ibuf/I |
| 4.230 | 4.230 | tINS | RR | Clk_ibuf/O |
| 5.591 | 1.361 | tNET | RR | key_filter0/key_flag_s5/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | Clk | ||
| 10.000 | 0.000 | tCL | FF | Clk_ibuf/I |
| 12.140 | 2.140 | tINS | FF | Clk_ibuf/O |
| 13.362 | 1.222 | tNET | FF | key_filter0/key_flag_s5/CLK |
MPW10
MPW Summary:
| Slack: | 6.521 |
| Actual Width: | 7.771 |
| Required Width: | 1.250 |
| Type: | High Pulse Width |
| Clock: | Clk |
| Objects: | key_filter1/state.FILTER1_s1 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||
| 0.000 | 0.000 | Clk | ||
| 0.000 | 0.000 | tCL | RR | Clk_ibuf/I |
| 4.230 | 4.230 | tINS | RR | Clk_ibuf/O |
| 5.591 | 1.361 | tNET | RR | key_filter1/state.FILTER1_s1/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 10.000 | 0.000 | active clock edge time | ||
| 10.000 | 0.000 | Clk | ||
| 10.000 | 0.000 | tCL | FF | Clk_ibuf/I |
| 12.140 | 2.140 | tINS | FF | Clk_ibuf/O |
| 13.362 | 1.222 | tNET | FF | key_filter1/state.FILTER1_s1/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
| FANOUT | NET NAME | WORST SLACK | MAX DELAY |
|---|---|---|---|
| 66 | Clk_d | 13.912 | 1.727 |
| 20 | en_cnt | 16.878 | 1.232 |
| 20 | en_cnt | 17.149 | 1.171 |
| 9 | key_tmpa | 16.123 | 1.441 |
| 9 | key_tmpa | 16.092 | 1.918 |
| 8 | key_tmpb | 16.658 | 0.501 |
| 8 | cnt_full | 16.058 | 0.832 |
| 8 | key_tmpb | 15.938 | 0.854 |
| 8 | cnt_full | 14.976 | 0.836 |
| 7 | n92_6 | 13.912 | 0.843 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
| GRID LOC | ROUTE CONGESTIONS |
|---|---|
| R13C8 | 84.72% |
| R12C7 | 68.06% |
| R8C7 | 65.28% |
| R12C6 | 62.50% |
| R8C9 | 58.33% |
| R13C9 | 58.33% |
| R7C7 | 56.94% |
| R7C8 | 54.17% |
| R14C8 | 51.39% |
| R13C6 | 48.61% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
| SDC Command Type | State | Detail Command |
|---|