Timing Messages

Report Title	Timing Analysis Report
Design File	/home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/Bincounter/chap_bincounter/impl/gwsynthesis/chap_bincounter.vg
Physical Constraints File	/home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/Bincounter/chap_bincounter/src/chap_bincounter.cst
Timing Constraint File	---
Tool Version	V1.9.10.03 Education
Part Number	GW1NSR-LV4CQN48PC6/I5
Device	GW1NSR-4C
Created Time	Tue Apr 8 10:29:27 2025
Legal Announcement	Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 1.14V 85C C6/I5
Hold Delay Model	Fast 1.26V 0C C6/I5
Numbers of Paths Analyzed	52
Numbers of Endpoints Analyzed	52
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	clk	Base	20.000	50.000	0.000	10.000			clk_ibuf/I

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk	50.000(MHz)	129.110(MHz)	5	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk	Setup	0.000	0
clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	12.255	cnt_22_s0/Q	cnt_0_s0/D	clk:[R]	clk:[R]	20.000	0.000	7.345
2	12.255	cnt_22_s0/Q	cnt_9_s0/D	clk:[R]	clk:[R]	20.000	0.000	7.345
3	12.274	cnt_22_s0/Q	cnt_1_s0/D	clk:[R]	clk:[R]	20.000	0.000	7.326
4	12.274	cnt_22_s0/Q	cnt_7_s0/D	clk:[R]	clk:[R]	20.000	0.000	7.326
5	12.274	cnt_22_s0/Q	cnt_18_s0/D	clk:[R]	clk:[R]	20.000	0.000	7.326
6	12.274	cnt_22_s0/Q	cnt_19_s0/D	clk:[R]	clk:[R]	20.000	0.000	7.326
7	12.287	cnt_9_s0/Q	cnt_21_s0/D	clk:[R]	clk:[R]	20.000	0.000	7.313
8	12.287	cnt_9_s0/Q	cnt_22_s0/D	clk:[R]	clk:[R]	20.000	0.000	7.313
9	12.317	cnt_9_s0/Q	cnt_20_s0/D	clk:[R]	clk:[R]	20.000	0.000	7.283
10	12.338	cnt_9_s0/Q	cnt_23_s0/D	clk:[R]	clk:[R]	20.000	0.000	7.262
11	12.501	cnt_22_s0/Q	cnt_15_s0/D	clk:[R]	clk:[R]	20.000	0.000	7.099
12	12.508	cnt_1_s0/Q	cnt_13_s0/D	clk:[R]	clk:[R]	20.000	0.000	7.092
13	12.508	cnt_1_s0/Q	cnt_14_s0/D	clk:[R]	clk:[R]	20.000	0.000	7.092
14	12.527	cnt_22_s0/Q	cnt_2_s0/D	clk:[R]	clk:[R]	20.000	0.000	7.073
15	12.568	cnt_22_s0/Q	cnt_16_s0/D	clk:[R]	clk:[R]	20.000	0.000	7.032
16	12.590	cnt_22_s0/Q	cnt_6_s0/D	clk:[R]	clk:[R]	20.000	0.000	7.010
17	12.594	cnt_22_s0/Q	cnt_11_s0/D	clk:[R]	clk:[R]	20.000	0.000	7.006
18	12.634	cnt_22_s0/Q	cnt_8_s0/D	clk:[R]	clk:[R]	20.000	0.000	6.966
19	12.654	cnt_1_s0/Q	cnt_17_s0/D	clk:[R]	clk:[R]	20.000	0.000	6.946
20	12.772	cnt_22_s0/Q	cnt_12_s0/D	clk:[R]	clk:[R]	20.000	0.000	6.828
21	12.968	cnt_22_s0/Q	cnt_10_s0/D	clk:[R]	clk:[R]	20.000	0.000	6.632
22	13.000	cnt_22_s0/Q	cnt_3_s0/D	clk:[R]	clk:[R]	20.000	0.000	6.600
23	13.603	cnt_22_s0/Q	cnt_4_s0/D	clk:[R]	clk:[R]	20.000	0.000	5.997
24	13.603	cnt_22_s0/Q	cnt_5_s0/D	clk:[R]	clk:[R]	20.000	0.000	5.997
25	14.110	cnt_8_s0/Q	led_s3/CE	clk:[R]	clk:[R]	20.000	0.000	5.846

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.708	led_s3/Q	led_s3/D	clk:[R]	clk:[R]	0.000	0.000	0.708
2	0.708	cnt_2_s0/Q	cnt_2_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.708
3	0.708	cnt_7_s0/Q	cnt_7_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.708
4	0.708	cnt_9_s0/Q	cnt_9_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.708
5	0.708	cnt_16_s0/Q	cnt_16_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.708
6	0.709	cnt_0_s0/Q	cnt_0_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.709
7	0.709	cnt_5_s0/Q	cnt_5_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.709
8	0.709	cnt_15_s0/Q	cnt_15_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.709
9	0.710	cnt_6_s0/Q	cnt_6_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.710
10	0.710	cnt_13_s0/Q	cnt_13_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.710
11	0.710	cnt_22_s0/Q	cnt_22_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.710
12	0.893	cnt_23_s0/Q	cnt_23_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.893
13	0.943	cnt_10_s0/Q	cnt_11_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.943
14	0.943	cnt_0_s0/Q	cnt_1_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.943
15	0.944	cnt_18_s0/Q	cnt_19_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.944
16	0.946	cnt_13_s0/Q	cnt_14_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.946
17	1.060	cnt_3_s0/Q	cnt_3_s0/D	clk:[R]	clk:[R]	0.000	0.000	1.060
18	1.060	cnt_12_s0/Q	cnt_12_s0/D	clk:[R]	clk:[R]	0.000	0.000	1.060
19	1.061	cnt_18_s0/Q	cnt_18_s0/D	clk:[R]	clk:[R]	0.000	0.000	1.061
20	1.061	cnt_20_s0/Q	cnt_20_s0/D	clk:[R]	clk:[R]	0.000	0.000	1.061
21	1.062	cnt_21_s0/Q	cnt_21_s0/D	clk:[R]	clk:[R]	0.000	0.000	1.062
22	1.063	cnt_8_s0/Q	cnt_8_s0/D	clk:[R]	clk:[R]	0.000	0.000	1.063
23	1.298	cnt_4_s0/Q	cnt_4_s0/D	clk:[R]	clk:[R]	0.000	0.000	1.298
24	1.309	cnt_10_s0/Q	cnt_10_s0/D	clk:[R]	clk:[R]	0.000	0.000	1.309
25	2.010	cnt_4_s0/Q	led_s3/CE	clk:[R]	clk:[R]	0.000	0.000	2.023

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	6.521	7.771	1.250	High Pulse Width	clk	cnt_23_s0
2	6.521	7.771	1.250	High Pulse Width	clk	cnt_22_s0
3	6.521	7.771	1.250	High Pulse Width	clk	cnt_20_s0
4	6.521	7.771	1.250	High Pulse Width	clk	cnt_16_s0
5	6.521	7.771	1.250	High Pulse Width	clk	cnt_8_s0
6	6.521	7.771	1.250	High Pulse Width	clk	cnt_9_s0
7	6.521	7.771	1.250	High Pulse Width	clk	cnt_17_s0
8	6.521	7.771	1.250	High Pulse Width	clk	cnt_10_s0
9	6.521	7.771	1.250	High Pulse Width	clk	cnt_11_s0
10	6.521	7.771	1.250	High Pulse Width	clk	led_s3

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	12.255
Data Arrival Time	12.936
Data Required Time	25.191
From	cnt_22_s0
To	cnt_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R13C7[0][A]	cnt_22_s0/CLK
6.049	0.458	tC2Q	RF	4	R13C7[0][A]	cnt_22_s0/Q
6.865	0.815	tNET	FF	1	R11C8[3][A]	n105_s26/I2
7.687	0.822	tINS	FF	2	R11C8[3][A]	n105_s26/F
8.502	0.816	tNET	FF	1	R12C7[1][B]	n35_s7/I3
9.601	1.099	tINS	FF	1	R12C7[1][B]	n35_s7/F
9.607	0.005	tNET	FF	1	R12C7[3][A]	n35_s4/I2
10.706	1.099	tINS	FF	24	R12C7[3][A]	n35_s4/F
11.904	1.199	tNET	FF	1	R8C8[1][A]	n58_s2/I1
12.936	1.032	tINS	FF	1	R8C8[1][A]	n58_s2/F
12.936	0.000	tNET	FF	1	R8C8[1][A]	cnt_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R8C8[1][A]	cnt_0_s0/CLK
25.191	-0.400	tSu		1	R8C8[1][A]	cnt_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 4.052, 55.165%; route: 2.835, 38.595%; tC2Q: 0.458, 6.240%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path2

Path Summary:

Slack	12.255
Data Arrival Time	12.936
Data Required Time	25.191
From	cnt_22_s0
To	cnt_9_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R13C7[0][A]	cnt_22_s0/CLK
6.049	0.458	tC2Q	RF	4	R13C7[0][A]	cnt_22_s0/Q
6.865	0.815	tNET	FF	1	R11C8[3][A]	n105_s26/I2
7.687	0.822	tINS	FF	2	R11C8[3][A]	n105_s26/F
8.502	0.816	tNET	FF	1	R12C7[1][B]	n35_s7/I3
9.601	1.099	tINS	FF	1	R12C7[1][B]	n35_s7/F
9.607	0.005	tNET	FF	1	R12C7[3][A]	n35_s4/I2
10.706	1.099	tINS	FF	24	R12C7[3][A]	n35_s4/F
11.904	1.199	tNET	FF	1	R8C8[0][A]	n49_s1/I3
12.936	1.032	tINS	FF	1	R8C8[0][A]	n49_s1/F
12.936	0.000	tNET	FF	1	R8C8[0][A]	cnt_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R8C8[0][A]	cnt_9_s0/CLK
25.191	-0.400	tSu		1	R8C8[0][A]	cnt_9_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 4.052, 55.165%; route: 2.835, 38.595%; tC2Q: 0.458, 6.240%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path3

Path Summary:

Slack	12.274
Data Arrival Time	12.917
Data Required Time	25.191
From	cnt_22_s0
To	cnt_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R13C7[0][A]	cnt_22_s0/CLK
6.049	0.458	tC2Q	RF	4	R13C7[0][A]	cnt_22_s0/Q
6.865	0.815	tNET	FF	1	R11C8[3][A]	n105_s26/I2
7.687	0.822	tINS	FF	2	R11C8[3][A]	n105_s26/F
8.502	0.816	tNET	FF	1	R12C7[1][B]	n35_s7/I3
9.601	1.099	tINS	FF	1	R12C7[1][B]	n35_s7/F
9.607	0.005	tNET	FF	1	R12C7[3][A]	n35_s4/I2
10.706	1.099	tINS	FF	24	R12C7[3][A]	n35_s4/F
12.095	1.389	tNET	FF	1	R9C8[2][B]	n57_s1/I2
12.917	0.822	tINS	FF	1	R9C8[2][B]	n57_s1/F
12.917	0.000	tNET	FF	1	R9C8[2][B]	cnt_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R9C8[2][B]	cnt_1_s0/CLK
25.191	-0.400	tSu		1	R9C8[2][B]	cnt_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.842, 52.444%; route: 3.026, 41.299%; tC2Q: 0.458, 6.256%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path4

Path Summary:

Slack	12.274
Data Arrival Time	12.917
Data Required Time	25.191
From	cnt_22_s0
To	cnt_7_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R13C7[0][A]	cnt_22_s0/CLK
6.049	0.458	tC2Q	RF	4	R13C7[0][A]	cnt_22_s0/Q
6.865	0.815	tNET	FF	1	R11C8[3][A]	n105_s26/I2
7.687	0.822	tINS	FF	2	R11C8[3][A]	n105_s26/F
8.502	0.816	tNET	FF	1	R12C7[1][B]	n35_s7/I3
9.601	1.099	tINS	FF	1	R12C7[1][B]	n35_s7/F
9.607	0.005	tNET	FF	1	R12C7[3][A]	n35_s4/I2
10.706	1.099	tINS	FF	24	R12C7[3][A]	n35_s4/F
12.095	1.389	tNET	FF	1	R9C8[0][A]	n51_s1/I3
12.917	0.822	tINS	FF	1	R9C8[0][A]	n51_s1/F
12.917	0.000	tNET	FF	1	R9C8[0][A]	cnt_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R9C8[0][A]	cnt_7_s0/CLK
25.191	-0.400	tSu		1	R9C8[0][A]	cnt_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.842, 52.444%; route: 3.026, 41.299%; tC2Q: 0.458, 6.256%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path5

Path Summary:

Slack	12.274
Data Arrival Time	12.917
Data Required Time	25.191
From	cnt_22_s0
To	cnt_18_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R13C7[0][A]	cnt_22_s0/CLK
6.049	0.458	tC2Q	RF	4	R13C7[0][A]	cnt_22_s0/Q
6.865	0.815	tNET	FF	1	R11C8[3][A]	n105_s26/I2
7.687	0.822	tINS	FF	2	R11C8[3][A]	n105_s26/F
8.502	0.816	tNET	FF	1	R12C7[1][B]	n35_s7/I3
9.601	1.099	tINS	FF	1	R12C7[1][B]	n35_s7/F
9.607	0.005	tNET	FF	1	R12C7[3][A]	n35_s4/I2
10.706	1.099	tINS	FF	24	R12C7[3][A]	n35_s4/F
12.095	1.389	tNET	FF	1	R9C8[0][B]	n40_s1/I2
12.917	0.822	tINS	FF	1	R9C8[0][B]	n40_s1/F
12.917	0.000	tNET	FF	1	R9C8[0][B]	cnt_18_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R9C8[0][B]	cnt_18_s0/CLK
25.191	-0.400	tSu		1	R9C8[0][B]	cnt_18_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.842, 52.444%; route: 3.026, 41.299%; tC2Q: 0.458, 6.256%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path6

Path Summary:

Slack	12.274
Data Arrival Time	12.917
Data Required Time	25.191
From	cnt_22_s0
To	cnt_19_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R13C7[0][A]	cnt_22_s0/CLK
6.049	0.458	tC2Q	RF	4	R13C7[0][A]	cnt_22_s0/Q
6.865	0.815	tNET	FF	1	R11C8[3][A]	n105_s26/I2
7.687	0.822	tINS	FF	2	R11C8[3][A]	n105_s26/F
8.502	0.816	tNET	FF	1	R12C7[1][B]	n35_s7/I3
9.601	1.099	tINS	FF	1	R12C7[1][B]	n35_s7/F
9.607	0.005	tNET	FF	1	R12C7[3][A]	n35_s4/I2
10.706	1.099	tINS	FF	24	R12C7[3][A]	n35_s4/F
12.095	1.389	tNET	FF	1	R9C8[1][B]	n39_s1/I3
12.917	0.822	tINS	FF	1	R9C8[1][B]	n39_s1/F
12.917	0.000	tNET	FF	1	R9C8[1][B]	cnt_19_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R9C8[1][B]	cnt_19_s0/CLK
25.191	-0.400	tSu		1	R9C8[1][B]	cnt_19_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.842, 52.444%; route: 3.026, 41.299%; tC2Q: 0.458, 6.256%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path7

Path Summary:

Slack	12.287
Data Arrival Time	12.904
Data Required Time	25.191
From	cnt_9_s0
To	cnt_21_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R8C8[0][A]	cnt_9_s0/CLK
6.049	0.458	tC2Q	RF	4	R8C8[0][A]	cnt_9_s0/Q
6.866	0.816	tNET	FF	1	R9C7[3][B]	n105_s19/I0
7.965	1.099	tINS	FF	6	R9C7[3][B]	n105_s19/F
8.791	0.826	tNET	FF	1	R11C8[2][B]	n35_s5/I2
9.852	1.061	tINS	FR	2	R11C8[2][B]	n35_s5/F
10.273	0.421	tNET	RR	1	R11C7[3][B]	n35_s2/I3
11.372	1.099	tINS	RF	3	R11C7[3][B]	n35_s2/F
11.872	0.500	tNET	FF	1	R13C7[0][B]	n37_s1/I1
12.904	1.032	tINS	FF	1	R13C7[0][B]	n37_s1/F
12.904	0.000	tNET	FF	1	R13C7[0][B]	cnt_21_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R13C7[0][B]	cnt_21_s0/CLK
25.191	-0.400	tSu		1	R13C7[0][B]	cnt_21_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 4.291, 58.679%; route: 2.563, 35.054%; tC2Q: 0.458, 6.268%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path8

Path Summary:

Slack	12.287
Data Arrival Time	12.904
Data Required Time	25.191
From	cnt_9_s0
To	cnt_22_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R8C8[0][A]	cnt_9_s0/CLK
6.049	0.458	tC2Q	RF	4	R8C8[0][A]	cnt_9_s0/Q
6.866	0.816	tNET	FF	1	R9C7[3][B]	n105_s19/I0
7.965	1.099	tINS	FF	6	R9C7[3][B]	n105_s19/F
8.791	0.826	tNET	FF	1	R11C8[2][B]	n35_s5/I2
9.852	1.061	tINS	FR	2	R11C8[2][B]	n35_s5/F
10.273	0.421	tNET	RR	1	R11C7[3][B]	n35_s2/I3
11.372	1.099	tINS	RF	3	R11C7[3][B]	n35_s2/F
11.872	0.500	tNET	FF	1	R13C7[0][A]	n36_s1/I1
12.904	1.032	tINS	FF	1	R13C7[0][A]	n36_s1/F
12.904	0.000	tNET	FF	1	R13C7[0][A]	cnt_22_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R13C7[0][A]	cnt_22_s0/CLK
25.191	-0.400	tSu		1	R13C7[0][A]	cnt_22_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 4.291, 58.679%; route: 2.563, 35.054%; tC2Q: 0.458, 6.268%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path9

Path Summary:

Slack	12.317
Data Arrival Time	12.874
Data Required Time	25.191
From	cnt_9_s0
To	cnt_20_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R8C8[0][A]	cnt_9_s0/CLK
6.049	0.458	tC2Q	RF	4	R8C8[0][A]	cnt_9_s0/Q
6.866	0.816	tNET	FF	1	R9C7[3][B]	n105_s19/I0
7.965	1.099	tINS	FF	6	R9C7[3][B]	n105_s19/F
8.791	0.826	tNET	FF	1	R11C8[2][B]	n35_s5/I2
9.890	1.099	tINS	FF	2	R11C8[2][B]	n35_s5/F
9.901	0.011	tNET	FF	1	R11C8[1][B]	n38_s4/I3
10.933	1.032	tINS	FF	4	R11C8[1][B]	n38_s4/F
12.248	1.315	tNET	FF	1	R12C7[0][B]	n38_s1/I1
12.874	0.626	tINS	FF	1	R12C7[0][B]	n38_s1/F
12.874	0.000	tNET	FF	1	R12C7[0][B]	cnt_20_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R12C7[0][B]	cnt_20_s0/CLK
25.191	-0.400	tSu		1	R12C7[0][B]	cnt_20_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.856, 52.944%; route: 2.969, 40.763%; tC2Q: 0.458, 6.293%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path10

Path Summary:

Slack	12.338
Data Arrival Time	12.854
Data Required Time	25.191
From	cnt_9_s0
To	cnt_23_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R8C8[0][A]	cnt_9_s0/CLK
6.049	0.458	tC2Q	RF	4	R8C8[0][A]	cnt_9_s0/Q
6.866	0.816	tNET	FF	1	R9C7[3][B]	n105_s19/I0
7.965	1.099	tINS	FF	6	R9C7[3][B]	n105_s19/F
8.791	0.826	tNET	FF	1	R11C8[2][B]	n35_s5/I2
9.852	1.061	tINS	FR	2	R11C8[2][B]	n35_s5/F
10.273	0.421	tNET	RR	1	R11C7[3][B]	n35_s2/I3
11.334	1.061	tINS	RR	3	R11C7[3][B]	n35_s2/F
11.755	0.421	tNET	RR	1	R11C8[2][A]	n35_s1/I0
12.854	1.099	tINS	RF	1	R11C8[2][A]	n35_s1/F
12.854	0.000	tNET	FF	1	R11C8[2][A]	cnt_23_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R11C8[2][A]	cnt_23_s0/CLK
25.191	-0.400	tSu		1	R11C8[2][A]	cnt_23_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 4.320, 59.484%; route: 2.484, 34.205%; tC2Q: 0.458, 6.311%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path11

Path Summary:

Slack	12.501
Data Arrival Time	12.690
Data Required Time	25.191
From	cnt_22_s0
To	cnt_15_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R13C7[0][A]	cnt_22_s0/CLK
6.049	0.458	tC2Q	RF	4	R13C7[0][A]	cnt_22_s0/Q
6.865	0.815	tNET	FF	1	R11C8[3][A]	n105_s26/I2
7.687	0.822	tINS	FF	2	R11C8[3][A]	n105_s26/F
8.502	0.816	tNET	FF	1	R12C7[1][B]	n35_s7/I3
9.601	1.099	tINS	FF	1	R12C7[1][B]	n35_s7/F
9.607	0.005	tNET	FF	1	R12C7[3][A]	n35_s4/I2
10.706	1.099	tINS	FF	24	R12C7[3][A]	n35_s4/F
11.591	0.886	tNET	FF	1	R11C7[1][A]	n43_s1/I3
12.690	1.099	tINS	FF	1	R11C7[1][A]	n43_s1/F
12.690	0.000	tNET	FF	1	R11C7[1][A]	cnt_15_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R11C7[1][A]	cnt_15_s0/CLK
25.191	-0.400	tSu		1	R11C7[1][A]	cnt_15_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 4.119, 58.020%; route: 2.522, 35.524%; tC2Q: 0.458, 6.456%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path12

Path Summary:

Slack	12.508
Data Arrival Time	12.684
Data Required Time	25.191
From	cnt_1_s0
To	cnt_13_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R9C8[2][B]	cnt_1_s0/CLK
6.049	0.458	tC2Q	RF	4	R9C8[2][B]	cnt_1_s0/Q
6.872	0.823	tNET	FF	1	R12C8[1][B]	n51_s2/I1
7.694	0.822	tINS	FF	7	R12C8[1][B]	n51_s2/F
8.526	0.831	tNET	FF	1	R9C8[2][A]	n42_s2/I1
9.587	1.061	tINS	FR	8	R9C8[2][A]	n42_s2/F
10.015	0.429	tNET	RR	1	R9C7[1][A]	n43_s4/I0
10.837	0.822	tINS	RF	3	R9C7[1][A]	n43_s4/F
11.652	0.814	tNET	FF	1	R11C8[1][A]	n45_s1/I1
12.684	1.032	tINS	FF	1	R11C8[1][A]	n45_s1/F
12.684	0.000	tNET	FF	1	R11C8[1][A]	cnt_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R11C8[1][A]	cnt_13_s0/CLK
25.191	-0.400	tSu		1	R11C8[1][A]	cnt_13_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.737, 52.689%; route: 2.897, 40.848%; tC2Q: 0.458, 6.462%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path13

Path Summary:

Slack	12.508
Data Arrival Time	12.684
Data Required Time	25.191
From	cnt_1_s0
To	cnt_14_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R9C8[2][B]	cnt_1_s0/CLK
6.049	0.458	tC2Q	RF	4	R9C8[2][B]	cnt_1_s0/Q
6.872	0.823	tNET	FF	1	R12C8[1][B]	n51_s2/I1
7.694	0.822	tINS	FF	7	R12C8[1][B]	n51_s2/F
8.526	0.831	tNET	FF	1	R9C8[2][A]	n42_s2/I1
9.587	1.061	tINS	FR	8	R9C8[2][A]	n42_s2/F
10.015	0.429	tNET	RR	1	R9C7[1][A]	n43_s4/I0
10.837	0.822	tINS	RF	3	R9C7[1][A]	n43_s4/F
11.652	0.814	tNET	FF	1	R11C8[0][B]	n44_s1/I1
12.684	1.032	tINS	FF	1	R11C8[0][B]	n44_s1/F
12.684	0.000	tNET	FF	1	R11C8[0][B]	cnt_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R11C8[0][B]	cnt_14_s0/CLK
25.191	-0.400	tSu		1	R11C8[0][B]	cnt_14_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.737, 52.689%; route: 2.897, 40.848%; tC2Q: 0.458, 6.462%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path14

Path Summary:

Slack	12.527
Data Arrival Time	12.664
Data Required Time	25.191
From	cnt_22_s0
To	cnt_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R13C7[0][A]	cnt_22_s0/CLK
6.049	0.458	tC2Q	RF	4	R13C7[0][A]	cnt_22_s0/Q
6.865	0.815	tNET	FF	1	R11C8[3][A]	n105_s26/I2
7.687	0.822	tINS	FF	2	R11C8[3][A]	n105_s26/F
8.502	0.816	tNET	FF	1	R12C7[1][B]	n35_s7/I3
9.601	1.099	tINS	FF	1	R12C7[1][B]	n35_s7/F
9.607	0.005	tNET	FF	1	R12C7[3][A]	n35_s4/I2
10.706	1.099	tINS	FF	24	R12C7[3][A]	n35_s4/F
11.565	0.859	tNET	FF	1	R12C8[1][A]	n56_s2/I3
12.664	1.099	tINS	FF	1	R12C8[1][A]	n56_s2/F
12.664	0.000	tNET	FF	1	R12C8[1][A]	cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R12C8[1][A]	cnt_2_s0/CLK
25.191	-0.400	tSu		1	R12C8[1][A]	cnt_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 4.119, 58.236%; route: 2.496, 35.284%; tC2Q: 0.458, 6.480%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path15

Path Summary:

Slack	12.568
Data Arrival Time	12.623
Data Required Time	25.191
From	cnt_22_s0
To	cnt_16_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R13C7[0][A]	cnt_22_s0/CLK
6.049	0.458	tC2Q	RF	4	R13C7[0][A]	cnt_22_s0/Q
6.865	0.815	tNET	FF	1	R11C8[3][A]	n105_s26/I2
7.687	0.822	tINS	FF	2	R11C8[3][A]	n105_s26/F
8.502	0.816	tNET	FF	1	R12C7[1][B]	n35_s7/I3
9.601	1.099	tINS	FF	1	R12C7[1][B]	n35_s7/F
9.607	0.005	tNET	FF	1	R12C7[3][A]	n35_s4/I2
10.706	1.099	tINS	FF	24	R12C7[3][A]	n35_s4/F
11.591	0.886	tNET	FF	1	R11C7[0][A]	n42_s1/I3
12.623	1.032	tINS	FF	1	R11C7[0][A]	n42_s1/F
12.623	0.000	tNET	FF	1	R11C7[0][A]	cnt_16_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R11C7[0][A]	cnt_16_s0/CLK
25.191	-0.400	tSu		1	R11C7[0][A]	cnt_16_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 4.052, 57.620%; route: 2.522, 35.862%; tC2Q: 0.458, 6.518%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path16

Path Summary:

Slack	12.590
Data Arrival Time	12.602
Data Required Time	25.191
From	cnt_22_s0
To	cnt_6_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R13C7[0][A]	cnt_22_s0/CLK
6.049	0.458	tC2Q	RF	4	R13C7[0][A]	cnt_22_s0/Q
6.865	0.815	tNET	FF	1	R11C8[3][A]	n105_s26/I2
7.687	0.822	tINS	FF	2	R11C8[3][A]	n105_s26/F
8.502	0.816	tNET	FF	1	R12C7[1][B]	n35_s7/I3
9.601	1.099	tINS	FF	1	R12C7[1][B]	n35_s7/F
9.607	0.005	tNET	FF	1	R12C7[3][A]	n35_s4/I2
10.706	1.099	tINS	FF	24	R12C7[3][A]	n35_s4/F
11.570	0.864	tNET	FF	1	R13C8[0][A]	n52_s1/I3
12.602	1.032	tINS	FF	1	R13C8[0][A]	n52_s1/F
12.602	0.000	tNET	FF	1	R13C8[0][A]	cnt_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R13C8[0][A]	cnt_6_s0/CLK
25.191	-0.400	tSu		1	R13C8[0][A]	cnt_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 4.052, 57.799%; route: 2.500, 35.663%; tC2Q: 0.458, 6.538%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path17

Path Summary:

Slack	12.594
Data Arrival Time	12.597
Data Required Time	25.191
From	cnt_22_s0
To	cnt_11_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R13C7[0][A]	cnt_22_s0/CLK
6.049	0.458	tC2Q	RF	4	R13C7[0][A]	cnt_22_s0/Q
6.865	0.815	tNET	FF	1	R11C8[3][A]	n105_s26/I2
7.687	0.822	tINS	FF	2	R11C8[3][A]	n105_s26/F
8.502	0.816	tNET	FF	1	R12C7[1][B]	n35_s7/I3
9.601	1.099	tINS	FF	1	R12C7[1][B]	n35_s7/F
9.607	0.005	tNET	FF	1	R12C7[3][A]	n35_s4/I2
10.706	1.099	tINS	FF	24	R12C7[3][A]	n35_s4/F
11.565	0.859	tNET	FF	1	R9C7[1][B]	n47_s1/I3
12.597	1.032	tINS	FF	1	R9C7[1][B]	n47_s1/F
12.597	0.000	tNET	FF	1	R9C7[1][B]	cnt_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R9C7[1][B]	cnt_11_s0/CLK
25.191	-0.400	tSu		1	R9C7[1][B]	cnt_11_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 4.052, 57.837%; route: 2.496, 35.621%; tC2Q: 0.458, 6.542%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path18

Path Summary:

Slack	12.634
Data Arrival Time	12.557
Data Required Time	25.191
From	cnt_22_s0
To	cnt_8_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R13C7[0][A]	cnt_22_s0/CLK
6.049	0.458	tC2Q	RF	4	R13C7[0][A]	cnt_22_s0/Q
6.865	0.815	tNET	FF	1	R11C8[3][A]	n105_s26/I2
7.687	0.822	tINS	FF	2	R11C8[3][A]	n105_s26/F
8.502	0.816	tNET	FF	1	R12C7[1][B]	n35_s7/I3
9.601	1.099	tINS	FF	1	R12C7[1][B]	n35_s7/F
9.607	0.005	tNET	FF	1	R12C7[3][A]	n35_s4/I2
10.706	1.099	tINS	FF	24	R12C7[3][A]	n35_s4/F
11.735	1.029	tNET	FF	1	R8C7[0][B]	n50_s1/I2
12.557	0.822	tINS	FF	1	R8C7[0][B]	n50_s1/F
12.557	0.000	tNET	FF	1	R8C7[0][B]	cnt_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R8C7[0][B]	cnt_8_s0/CLK
25.191	-0.400	tSu		1	R8C7[0][B]	cnt_8_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.842, 55.152%; route: 2.666, 38.268%; tC2Q: 0.458, 6.579%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path19

Path Summary:

Slack	12.654
Data Arrival Time	12.537
Data Required Time	25.191
From	cnt_1_s0
To	cnt_17_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R9C8[2][B]	cnt_1_s0/CLK
6.049	0.458	tC2Q	RF	4	R9C8[2][B]	cnt_1_s0/Q
6.872	0.823	tNET	FF	1	R12C8[1][B]	n51_s2/I1
7.694	0.822	tINS	FF	7	R12C8[1][B]	n51_s2/F
8.526	0.831	tNET	FF	1	R9C8[2][A]	n42_s2/I1
9.625	1.099	tINS	FF	8	R9C8[2][A]	n42_s2/F
10.468	0.843	tNET	FF	1	R11C7[2][B]	n41_s2/I1
11.500	1.032	tINS	FF	1	R11C7[2][B]	n41_s2/F
11.505	0.005	tNET	FF	1	R11C7[1][B]	n41_s1/I1
12.537	1.032	tINS	FF	1	R11C7[1][B]	n41_s1/F
12.537	0.000	tNET	FF	1	R11C7[1][B]	cnt_17_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R11C7[1][B]	cnt_17_s0/CLK
25.191	-0.400	tSu		1	R11C7[1][B]	cnt_17_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.985, 57.368%; route: 2.503, 36.034%; tC2Q: 0.458, 6.598%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path20

Path Summary:

Slack	12.772
Data Arrival Time	12.419
Data Required Time	25.191
From	cnt_22_s0
To	cnt_12_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R13C7[0][A]	cnt_22_s0/CLK
6.049	0.458	tC2Q	RF	4	R13C7[0][A]	cnt_22_s0/Q
6.865	0.815	tNET	FF	1	R11C8[3][A]	n105_s26/I2
7.687	0.822	tINS	FF	2	R11C8[3][A]	n105_s26/F
8.502	0.816	tNET	FF	1	R12C7[1][B]	n35_s7/I3
9.601	1.099	tINS	FF	1	R12C7[1][B]	n35_s7/F
9.607	0.005	tNET	FF	1	R12C7[3][A]	n35_s4/I2
10.706	1.099	tINS	FF	24	R12C7[3][A]	n35_s4/F
11.597	0.891	tNET	FF	1	R9C7[0][B]	n46_s1/I2
12.419	0.822	tINS	FF	1	R9C7[0][B]	n46_s1/F
12.419	0.000	tNET	FF	1	R9C7[0][B]	cnt_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R9C7[0][B]	cnt_12_s0/CLK
25.191	-0.400	tSu		1	R9C7[0][B]	cnt_12_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.842, 56.271%; route: 2.527, 37.016%; tC2Q: 0.458, 6.713%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path21

Path Summary:

Slack	12.968
Data Arrival Time	12.223
Data Required Time	25.191
From	cnt_22_s0
To	cnt_10_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R13C7[0][A]	cnt_22_s0/CLK
6.049	0.458	tC2Q	RF	4	R13C7[0][A]	cnt_22_s0/Q
6.865	0.815	tNET	FF	1	R11C8[3][A]	n105_s26/I2
7.687	0.822	tINS	FF	2	R11C8[3][A]	n105_s26/F
8.502	0.816	tNET	FF	1	R12C7[1][B]	n35_s7/I3
9.601	1.099	tINS	FF	1	R12C7[1][B]	n35_s7/F
9.607	0.005	tNET	FF	1	R12C7[3][A]	n35_s4/I2
10.706	1.099	tINS	FF	24	R12C7[3][A]	n35_s4/F
11.597	0.891	tNET	FF	1	R9C7[2][A]	n48_s1/I2
12.223	0.626	tINS	FF	1	R9C7[2][A]	n48_s1/F
12.223	0.000	tNET	FF	1	R9C7[2][A]	cnt_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R9C7[2][A]	cnt_10_s0/CLK
25.191	-0.400	tSu		1	R9C7[2][A]	cnt_10_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.646, 54.979%; route: 2.527, 38.110%; tC2Q: 0.458, 6.911%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path22

Path Summary:

Slack	13.000
Data Arrival Time	12.191
Data Required Time	25.191
From	cnt_22_s0
To	cnt_3_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R13C7[0][A]	cnt_22_s0/CLK
6.049	0.458	tC2Q	RF	4	R13C7[0][A]	cnt_22_s0/Q
6.865	0.815	tNET	FF	1	R11C8[3][A]	n105_s26/I2
7.687	0.822	tINS	FF	2	R11C8[3][A]	n105_s26/F
8.502	0.816	tNET	FF	1	R12C7[1][B]	n35_s7/I3
9.601	1.099	tINS	FF	1	R12C7[1][B]	n35_s7/F
9.607	0.005	tNET	FF	1	R12C7[3][A]	n35_s4/I2
10.706	1.099	tINS	FF	24	R12C7[3][A]	n35_s4/F
11.565	0.859	tNET	FF	1	R12C8[0][B]	n55_s1/I3
12.191	0.626	tINS	FF	1	R12C8[0][B]	n55_s1/F
12.191	0.000	tNET	FF	1	R12C8[0][B]	cnt_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R12C8[0][B]	cnt_3_s0/CLK
25.191	-0.400	tSu		1	R12C8[0][B]	cnt_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.646, 55.243%; route: 2.496, 37.812%; tC2Q: 0.458, 6.945%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path23

Path Summary:

Slack	13.603
Data Arrival Time	11.588
Data Required Time	25.191
From	cnt_22_s0
To	cnt_4_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R13C7[0][A]	cnt_22_s0/CLK
6.049	0.458	tC2Q	RF	4	R13C7[0][A]	cnt_22_s0/Q
6.865	0.815	tNET	FF	1	R11C8[3][A]	n105_s26/I2
7.687	0.822	tINS	FF	2	R11C8[3][A]	n105_s26/F
8.502	0.816	tNET	FF	1	R12C7[1][B]	n35_s7/I3
9.601	1.099	tINS	FF	1	R12C7[1][B]	n35_s7/F
9.607	0.005	tNET	FF	1	R12C7[3][A]	n35_s4/I2
10.706	1.099	tINS	FF	24	R12C7[3][A]	n35_s4/F
10.766	0.060	tNET	FF	1	R12C7[2][A]	n54_s1/I2
11.588	0.822	tINS	FF	1	R12C7[2][A]	n54_s1/F
11.588	0.000	tNET	FF	1	R12C7[2][A]	cnt_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R12C7[2][A]	cnt_4_s0/CLK
25.191	-0.400	tSu		1	R12C7[2][A]	cnt_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.842, 64.065%; route: 1.697, 28.293%; tC2Q: 0.458, 7.643%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path24

Path Summary:

Slack	13.603
Data Arrival Time	11.588
Data Required Time	25.191
From	cnt_22_s0
To	cnt_5_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R13C7[0][A]	cnt_22_s0/CLK
6.049	0.458	tC2Q	RF	4	R13C7[0][A]	cnt_22_s0/Q
6.865	0.815	tNET	FF	1	R11C8[3][A]	n105_s26/I2
7.687	0.822	tINS	FF	2	R11C8[3][A]	n105_s26/F
8.502	0.816	tNET	FF	1	R12C7[1][B]	n35_s7/I3
9.601	1.099	tINS	FF	1	R12C7[1][B]	n35_s7/F
9.607	0.005	tNET	FF	1	R12C7[3][A]	n35_s4/I2
10.706	1.099	tINS	FF	24	R12C7[3][A]	n35_s4/F
10.766	0.060	tNET	FF	1	R12C7[0][A]	n53_s2/I3
11.588	0.822	tINS	FF	1	R12C7[0][A]	n53_s2/F
11.588	0.000	tNET	FF	1	R12C7[0][A]	cnt_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R12C7[0][A]	cnt_5_s0/CLK
25.191	-0.400	tSu		1	R12C7[0][A]	cnt_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 3.842, 64.065%; route: 1.697, 28.293%; tC2Q: 0.458, 7.643%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Path25

Path Summary:

Slack	14.110
Data Arrival Time	11.438
Data Required Time	25.548
From	cnt_8_s0
To	led_s3
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
4.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
5.591	1.361	tNET	RR	1	R8C7[0][B]	cnt_8_s0/CLK
6.049	0.458	tC2Q	RF	9	R8C7[0][B]	cnt_8_s0/Q
7.378	1.329	tNET	FF	1	R11C8[0][A]	n105_s25/I1
8.180	0.802	tINS	FR	2	R11C8[0][A]	n105_s25/F
8.603	0.423	tNET	RR	1	R12C8[2][B]	n105_s22/I2
9.702	1.099	tINS	RF	1	R12C8[2][B]	n105_s22/F
9.708	0.005	tNET	FF	1	R12C8[3][B]	n105_s18/I3
10.734	1.026	tINS	FR	1	R12C8[3][B]	n105_s18/F
11.438	0.704	tNET	RR	1	R14C8[0][A]	led_s3/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
24.230	4.230	tINS	RR	25	IOT13[A]	clk_ibuf/O
25.591	1.361	tNET	RR	1	R14C8[0][A]	led_s3/CLK
25.548	-0.043	tSu		1	R14C8[0][A]	led_s3

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%
Arrival Data Path Delay	cell: 2.927, 50.065%; route: 2.461, 42.096%; tC2Q: 0.458, 7.840%
Required Clock Path Delay	cell: 4.230, 75.653%; route: 1.361, 24.347%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	led_s3
To	led_s3
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R14C8[0][A]	led_s3/CLK
4.426	0.333	tC2Q	RR	2	R14C8[0][A]	led_s3/Q
4.428	0.002	tNET	RR	1	R14C8[0][A]	n107_s2/I0
4.800	0.372	tINS	RF	1	R14C8[0][A]	n107_s2/F
4.800	0.000	tNET	FF	1	R14C8[0][A]	led_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R14C8[0][A]	led_s3/CLK
4.093	0.000	tHld		1	R14C8[0][A]	led_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path2

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	cnt_2_s0
To	cnt_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R12C8[1][A]	cnt_2_s0/CLK
4.426	0.333	tC2Q	RR	3	R12C8[1][A]	cnt_2_s0/Q
4.428	0.002	tNET	RR	1	R12C8[1][A]	n56_s2/I0
4.800	0.372	tINS	RF	1	R12C8[1][A]	n56_s2/F
4.800	0.000	tNET	FF	1	R12C8[1][A]	cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R12C8[1][A]	cnt_2_s0/CLK
4.093	0.000	tHld		1	R12C8[1][A]	cnt_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path3

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	cnt_7_s0
To	cnt_7_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R9C8[0][A]	cnt_7_s0/CLK
4.426	0.333	tC2Q	RR	4	R9C8[0][A]	cnt_7_s0/Q
4.428	0.002	tNET	RR	1	R9C8[0][A]	n51_s1/I2
4.800	0.372	tINS	RF	1	R9C8[0][A]	n51_s1/F
4.800	0.000	tNET	FF	1	R9C8[0][A]	cnt_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R9C8[0][A]	cnt_7_s0/CLK
4.093	0.000	tHld		1	R9C8[0][A]	cnt_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path4

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	cnt_9_s0
To	cnt_9_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C8[0][A]	cnt_9_s0/CLK
4.426	0.333	tC2Q	RR	4	R8C8[0][A]	cnt_9_s0/Q
4.428	0.002	tNET	RR	1	R8C8[0][A]	n49_s1/I2
4.800	0.372	tINS	RF	1	R8C8[0][A]	n49_s1/F
4.800	0.000	tNET	FF	1	R8C8[0][A]	cnt_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C8[0][A]	cnt_9_s0/CLK
4.093	0.000	tHld		1	R8C8[0][A]	cnt_9_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path5

Path Summary:

Slack	0.708
Data Arrival Time	4.800
Data Required Time	4.093
From	cnt_16_s0
To	cnt_16_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R11C7[0][A]	cnt_16_s0/CLK
4.426	0.333	tC2Q	RR	2	R11C7[0][A]	cnt_16_s0/Q
4.428	0.002	tNET	RR	1	R11C7[0][A]	n42_s1/I2
4.800	0.372	tINS	RF	1	R11C7[0][A]	n42_s1/F
4.800	0.000	tNET	FF	1	R11C7[0][A]	cnt_16_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R11C7[0][A]	cnt_16_s0/CLK
4.093	0.000	tHld		1	R11C7[0][A]	cnt_16_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path6

Path Summary:

Slack	0.709
Data Arrival Time	4.802
Data Required Time	4.093
From	cnt_0_s0
To	cnt_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C8[1][A]	cnt_0_s0/CLK
4.426	0.333	tC2Q	RR	5	R8C8[1][A]	cnt_0_s0/Q
4.430	0.004	tNET	RR	1	R8C8[1][A]	n58_s2/I0
4.802	0.372	tINS	RF	1	R8C8[1][A]	n58_s2/F
4.802	0.000	tNET	FF	1	R8C8[1][A]	cnt_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C8[1][A]	cnt_0_s0/CLK
4.093	0.000	tHld		1	R8C8[1][A]	cnt_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path7

Path Summary:

Slack	0.709
Data Arrival Time	4.802
Data Required Time	4.093
From	cnt_5_s0
To	cnt_5_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R12C7[0][A]	cnt_5_s0/CLK
4.426	0.333	tC2Q	RR	5	R12C7[0][A]	cnt_5_s0/Q
4.430	0.004	tNET	RR	1	R12C7[0][A]	n53_s2/I0
4.802	0.372	tINS	RF	1	R12C7[0][A]	n53_s2/F
4.802	0.000	tNET	FF	1	R12C7[0][A]	cnt_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R12C7[0][A]	cnt_5_s0/CLK
4.093	0.000	tHld		1	R12C7[0][A]	cnt_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path8

Path Summary:

Slack	0.709
Data Arrival Time	4.802
Data Required Time	4.093
From	cnt_15_s0
To	cnt_15_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R11C7[1][A]	cnt_15_s0/CLK
4.426	0.333	tC2Q	RR	3	R11C7[1][A]	cnt_15_s0/Q
4.430	0.004	tNET	RR	1	R11C7[1][A]	n43_s1/I2
4.802	0.372	tINS	RF	1	R11C7[1][A]	n43_s1/F
4.802	0.000	tNET	FF	1	R11C7[1][A]	cnt_15_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R11C7[1][A]	cnt_15_s0/CLK
4.093	0.000	tHld		1	R11C7[1][A]	cnt_15_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path9

Path Summary:

Slack	0.710
Data Arrival Time	4.803
Data Required Time	4.093
From	cnt_6_s0
To	cnt_6_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R13C8[0][A]	cnt_6_s0/CLK
4.426	0.333	tC2Q	RR	4	R13C8[0][A]	cnt_6_s0/Q
4.431	0.005	tNET	RR	1	R13C8[0][A]	n52_s1/I2
4.803	0.372	tINS	RF	1	R13C8[0][A]	n52_s1/F
4.803	0.000	tNET	FF	1	R13C8[0][A]	cnt_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R13C8[0][A]	cnt_6_s0/CLK
4.093	0.000	tHld		1	R13C8[0][A]	cnt_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path10

Path Summary:

Slack	0.710
Data Arrival Time	4.803
Data Required Time	4.093
From	cnt_13_s0
To	cnt_13_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R11C8[1][A]	cnt_13_s0/CLK
4.426	0.333	tC2Q	RR	4	R11C8[1][A]	cnt_13_s0/Q
4.431	0.005	tNET	RR	1	R11C8[1][A]	n45_s1/I0
4.803	0.372	tINS	RF	1	R11C8[1][A]	n45_s1/F
4.803	0.000	tNET	FF	1	R11C8[1][A]	cnt_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R11C8[1][A]	cnt_13_s0/CLK
4.093	0.000	tHld		1	R11C8[1][A]	cnt_13_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path11

Path Summary:

Slack	0.710
Data Arrival Time	4.803
Data Required Time	4.093
From	cnt_22_s0
To	cnt_22_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R13C7[0][A]	cnt_22_s0/CLK
4.426	0.333	tC2Q	RR	4	R13C7[0][A]	cnt_22_s0/Q
4.431	0.005	tNET	RR	1	R13C7[0][A]	n36_s1/I2
4.803	0.372	tINS	RF	1	R13C7[0][A]	n36_s1/F
4.803	0.000	tNET	FF	1	R13C7[0][A]	cnt_22_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R13C7[0][A]	cnt_22_s0/CLK
4.093	0.000	tHld		1	R13C7[0][A]	cnt_22_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path12

Path Summary:

Slack	0.893
Data Arrival Time	4.986
Data Required Time	4.093
From	cnt_23_s0
To	cnt_23_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R11C8[2][A]	cnt_23_s0/CLK
4.426	0.333	tC2Q	RR	3	R11C8[2][A]	cnt_23_s0/Q
4.430	0.004	tNET	RR	1	R11C8[2][A]	n35_s1/I2
4.986	0.556	tINS	RR	1	R11C8[2][A]	n35_s1/F
4.986	0.000	tNET	RR	1	R11C8[2][A]	cnt_23_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R11C8[2][A]	cnt_23_s0/CLK
4.093	0.000	tHld		1	R11C8[2][A]	cnt_23_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.556, 62.271%; route: 0.004, 0.397%; tC2Q: 0.333, 37.333%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path13

Path Summary:

Slack	0.943
Data Arrival Time	5.036
Data Required Time	4.093
From	cnt_10_s0
To	cnt_11_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R9C7[2][A]	cnt_10_s0/CLK
4.426	0.333	tC2Q	RR	4	R9C7[2][A]	cnt_10_s0/Q
4.664	0.238	tNET	RR	1	R9C7[1][B]	n47_s1/I0
5.036	0.372	tINS	RF	1	R9C7[1][B]	n47_s1/F
5.036	0.000	tNET	FF	1	R9C7[1][B]	cnt_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R9C7[1][B]	cnt_11_s0/CLK
4.093	0.000	tHld		1	R9C7[1][B]	cnt_11_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 39.452%; route: 0.238, 25.196%; tC2Q: 0.333, 35.352%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path14

Path Summary:

Slack	0.943
Data Arrival Time	5.036
Data Required Time	4.093
From	cnt_0_s0
To	cnt_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C8[1][A]	cnt_0_s0/CLK
4.426	0.333	tC2Q	RF	5	R8C8[1][A]	cnt_0_s0/Q
4.664	0.238	tNET	FF	1	R9C8[2][B]	n57_s1/I0
5.036	0.372	tINS	FF	1	R9C8[2][B]	n57_s1/F
5.036	0.000	tNET	FF	1	R9C8[2][B]	cnt_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R9C8[2][B]	cnt_1_s0/CLK
4.093	0.000	tHld		1	R9C8[2][B]	cnt_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 39.447%; route: 0.238, 25.207%; tC2Q: 0.333, 35.347%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path15

Path Summary:

Slack	0.944
Data Arrival Time	5.037
Data Required Time	4.093
From	cnt_18_s0
To	cnt_19_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R9C8[0][B]	cnt_18_s0/CLK
4.426	0.333	tC2Q	RR	4	R9C8[0][B]	cnt_18_s0/Q
4.665	0.239	tNET	RR	1	R9C8[1][B]	n39_s1/I0
5.037	0.372	tINS	RF	1	R9C8[1][B]	n39_s1/F
5.037	0.000	tNET	FF	1	R9C8[1][B]	cnt_19_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R9C8[1][B]	cnt_19_s0/CLK
4.093	0.000	tHld		1	R9C8[1][B]	cnt_19_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 39.403%; route: 0.239, 25.289%; tC2Q: 0.333, 35.307%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path16

Path Summary:

Slack	0.946
Data Arrival Time	5.039
Data Required Time	4.093
From	cnt_13_s0
To	cnt_14_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R11C8[1][A]	cnt_13_s0/CLK
4.426	0.333	tC2Q	RF	4	R11C8[1][A]	cnt_13_s0/Q
4.667	0.241	tNET	FF	1	R11C8[0][B]	n44_s1/I0
5.039	0.372	tINS	FF	1	R11C8[0][B]	n44_s1/F
5.039	0.000	tNET	FF	1	R11C8[0][B]	cnt_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R11C8[0][B]	cnt_14_s0/CLK
4.093	0.000	tHld		1	R11C8[0][B]	cnt_14_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.372, 39.312%; route: 0.241, 25.462%; tC2Q: 0.333, 35.226%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path17

Path Summary:

Slack	1.060
Data Arrival Time	5.152
Data Required Time	4.093
From	cnt_3_s0
To	cnt_3_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R12C8[0][B]	cnt_3_s0/CLK
4.426	0.333	tC2Q	RR	2	R12C8[0][B]	cnt_3_s0/Q
4.428	0.002	tNET	RR	1	R12C8[0][B]	n55_s1/I2
5.152	0.724	tINS	RR	1	R12C8[0][B]	n55_s1/F
5.152	0.000	tNET	RR	1	R12C8[0][B]	cnt_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R12C8[0][B]	cnt_3_s0/CLK
4.093	0.000	tHld		1	R12C8[0][B]	cnt_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.724, 68.322%; route: 0.002, 0.223%; tC2Q: 0.333, 31.456%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path18

Path Summary:

Slack	1.060
Data Arrival Time	5.152
Data Required Time	4.093
From	cnt_12_s0
To	cnt_12_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R9C7[0][B]	cnt_12_s0/CLK
4.426	0.333	tC2Q	RR	2	R9C7[0][B]	cnt_12_s0/Q
4.428	0.002	tNET	RR	1	R9C7[0][B]	n46_s1/I1
5.152	0.724	tINS	RR	1	R9C7[0][B]	n46_s1/F
5.152	0.000	tNET	RR	1	R9C7[0][B]	cnt_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R9C7[0][B]	cnt_12_s0/CLK
4.093	0.000	tHld		1	R9C7[0][B]	cnt_12_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.724, 68.322%; route: 0.002, 0.223%; tC2Q: 0.333, 31.456%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path19

Path Summary:

Slack	1.061
Data Arrival Time	5.154
Data Required Time	4.093
From	cnt_18_s0
To	cnt_18_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R9C8[0][B]	cnt_18_s0/CLK
4.426	0.333	tC2Q	RR	4	R9C8[0][B]	cnt_18_s0/Q
4.430	0.004	tNET	RR	1	R9C8[0][B]	n40_s1/I0
5.154	0.724	tINS	RR	1	R9C8[0][B]	n40_s1/F
5.154	0.000	tNET	RR	1	R9C8[0][B]	cnt_18_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R9C8[0][B]	cnt_18_s0/CLK
4.093	0.000	tHld		1	R9C8[0][B]	cnt_18_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.724, 68.246%; route: 0.004, 0.334%; tC2Q: 0.333, 31.421%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path20

Path Summary:

Slack	1.061
Data Arrival Time	5.154
Data Required Time	4.093
From	cnt_20_s0
To	cnt_20_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R12C7[0][B]	cnt_20_s0/CLK
4.426	0.333	tC2Q	RR	4	R12C7[0][B]	cnt_20_s0/Q
4.430	0.004	tNET	RR	1	R12C7[0][B]	n38_s1/I2
5.154	0.724	tINS	RR	1	R12C7[0][B]	n38_s1/F
5.154	0.000	tNET	RR	1	R12C7[0][B]	cnt_20_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R12C7[0][B]	cnt_20_s0/CLK
4.093	0.000	tHld		1	R12C7[0][B]	cnt_20_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.724, 68.246%; route: 0.004, 0.334%; tC2Q: 0.333, 31.421%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path21

Path Summary:

Slack	1.062
Data Arrival Time	5.155
Data Required Time	4.093
From	cnt_21_s0
To	cnt_21_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R13C7[0][B]	cnt_21_s0/CLK
4.426	0.333	tC2Q	RR	5	R13C7[0][B]	cnt_21_s0/Q
4.431	0.005	tNET	RR	1	R13C7[0][B]	n37_s1/I0
5.155	0.724	tINS	RR	1	R13C7[0][B]	n37_s1/F
5.155	0.000	tNET	RR	1	R13C7[0][B]	cnt_21_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R13C7[0][B]	cnt_21_s0/CLK
4.093	0.000	tHld		1	R13C7[0][B]	cnt_21_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.724, 68.170%; route: 0.005, 0.445%; tC2Q: 0.333, 31.386%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path22

Path Summary:

Slack	1.063
Data Arrival Time	5.156
Data Required Time	4.093
From	cnt_8_s0
To	cnt_8_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C7[0][B]	cnt_8_s0/CLK
4.426	0.333	tC2Q	RR	9	R8C7[0][B]	cnt_8_s0/Q
4.432	0.006	tNET	RR	1	R8C7[0][B]	n50_s1/I0
5.156	0.724	tINS	RR	1	R8C7[0][B]	n50_s1/F
5.156	0.000	tNET	RR	1	R8C7[0][B]	cnt_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R8C7[0][B]	cnt_8_s0/CLK
4.093	0.000	tHld		1	R8C7[0][B]	cnt_8_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.724, 68.094%; route: 0.006, 0.555%; tC2Q: 0.333, 31.351%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path23

Path Summary:

Slack	1.298
Data Arrival Time	5.391
Data Required Time	4.093
From	cnt_4_s0
To	cnt_4_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R12C7[2][A]	cnt_4_s0/CLK
4.426	0.333	tC2Q	RR	5	R12C7[2][A]	cnt_4_s0/Q
4.665	0.239	tNET	RR	1	R12C7[2][A]	n54_s1/I0
5.391	0.726	tINS	RR	1	R12C7[2][A]	n54_s1/F
5.391	0.000	tNET	RR	1	R12C7[2][A]	cnt_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R12C7[2][A]	cnt_4_s0/CLK
4.093	0.000	tHld		1	R12C7[2][A]	cnt_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.726, 55.928%; route: 0.239, 18.393%; tC2Q: 0.333, 25.679%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path24

Path Summary:

Slack	1.309
Data Arrival Time	5.402
Data Required Time	4.093
From	cnt_10_s0
To	cnt_10_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R9C7[2][A]	cnt_10_s0/CLK
4.426	0.333	tC2Q	RR	4	R9C7[2][A]	cnt_10_s0/Q
4.676	0.250	tNET	RR	1	R9C7[2][A]	n48_s1/I0
5.402	0.726	tINS	RR	1	R9C7[2][A]	n48_s1/F
5.402	0.000	tNET	RR	1	R9C7[2][A]	cnt_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R9C7[2][A]	cnt_10_s0/CLK
4.093	0.000	tHld		1	R9C7[2][A]	cnt_10_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.726, 55.448%; route: 0.250, 19.094%; tC2Q: 0.333, 25.458%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Path25

Path Summary:

Slack	2.010
Data Arrival Time	6.116
Data Required Time	4.105
From	cnt_4_s0
To	led_s3
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R12C7[2][A]	cnt_4_s0/CLK
4.426	0.333	tC2Q	RF	5	R12C7[2][A]	cnt_4_s0/Q
4.671	0.245	tNET	FF	1	R12C8[0][A]	n105_s21/I0
5.227	0.556	tINS	FR	2	R12C8[0][A]	n105_s21/F
5.230	0.003	tNET	RR	1	R12C8[3][B]	n105_s18/I2
5.615	0.385	tINS	RR	1	R12C8[3][B]	n105_s18/F
6.116	0.501	tNET	RR	1	R14C8[0][A]	led_s3/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT13[A]	clk_ibuf/I
3.126	3.126	tINS	RR	25	IOT13[A]	clk_ibuf/O
4.093	0.966	tNET	RR	1	R14C8[0][A]	led_s3/CLK
4.105	0.012	tHld		1	R14C8[0][A]	led_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	3
Arrival Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%
Arrival Data Path Delay	cell: 0.941, 46.520%; route: 0.748, 37.001%; tC2Q: 0.333, 16.479%
Required Clock Path Delay	cell: 3.126, 76.388%; route: 0.966, 23.612%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	clk
Objects:	cnt_23_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
5.591	1.361	tNET	RR	cnt_23_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
13.362	1.222	tNET	FF	cnt_23_s0/CLK

MPW2

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	clk
Objects:	cnt_22_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
5.591	1.361	tNET	RR	cnt_22_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
13.362	1.222	tNET	FF	cnt_22_s0/CLK

MPW3

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	clk
Objects:	cnt_20_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
5.591	1.361	tNET	RR	cnt_20_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
13.362	1.222	tNET	FF	cnt_20_s0/CLK

MPW4

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	clk
Objects:	cnt_16_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
5.591	1.361	tNET	RR	cnt_16_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
13.362	1.222	tNET	FF	cnt_16_s0/CLK

MPW5

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	clk
Objects:	cnt_8_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
5.591	1.361	tNET	RR	cnt_8_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
13.362	1.222	tNET	FF	cnt_8_s0/CLK

MPW6

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	clk
Objects:	cnt_9_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
5.591	1.361	tNET	RR	cnt_9_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
13.362	1.222	tNET	FF	cnt_9_s0/CLK

MPW7

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	clk
Objects:	cnt_17_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
5.591	1.361	tNET	RR	cnt_17_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
13.362	1.222	tNET	FF	cnt_17_s0/CLK

MPW8

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	clk
Objects:	cnt_10_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
5.591	1.361	tNET	RR	cnt_10_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
13.362	1.222	tNET	FF	cnt_10_s0/CLK

MPW9

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	clk
Objects:	cnt_11_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
5.591	1.361	tNET	RR	cnt_11_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
13.362	1.222	tNET	FF	cnt_11_s0/CLK

MPW10

MPW Summary:

Slack:	6.521
Actual Width:	7.771
Required Width:	1.250
Type:	High Pulse Width
Clock:	clk
Objects:	led_s3

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
5.591	1.361	tNET	RR	led_s3/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
13.362	1.222	tNET	FF	led_s3/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
25	clk_d	12.255	1.727
24	n35_8	12.255	1.389
9	cnt[8]	13.123	1.329
8	n42_6	12.380	0.848
7	n51_6	12.380	0.831
6	n105_23	12.287	1.311
5	cnt[0]	12.413	1.327
5	cnt[21]	14.820	0.815
5	cnt[4]	13.071	0.426
5	cnt[5]	13.267	0.827

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R12C7	66.67%
R9C8	65.28%
R9C7	55.56%
R11C7	54.17%
R11C8	51.39%
R12C8	43.06%
R13C7	43.06%
R13C8	33.33%
R8C8	31.94%
R14C8	26.39%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command