PnR Messages

Report Title PnR Report
Design File /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/Bincounter/chap_bincounter/impl/gwsynthesis/chap_bincounter.vg
Physical Constraints File /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/Bincounter/chap_bincounter/src/chap_bincounter.cst
Timing Constraints File ---
Tool Version V1.9.10.03 Education
Part Number GW1NSR-LV4CQN48PC6/I5
Device GW1NSR-4C
Created Time Tue Apr 8 10:29:27 2025
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

PnR Details

Place & Route Process Running placement: Placement Phase 0: CPU time = 0h 0m 0.019s, Elapsed time = 0h 0m 0.025s Placement Phase 1: CPU time = 0h 0m 0.196s, Elapsed time = 0h 0m 0.198s Placement Phase 2: CPU time = 0h 0m 0.005s, Elapsed time = 0h 0m 0.004s Placement Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s Total Placement: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s Running routing: Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.011s Routing Phase 1: CPU time = 0h 0m 0.1s, Elapsed time = 0h 0m 0.103s Routing Phase 2: CPU time = 0h 0m 0.111s, Elapsed time = 0h 0m 0.109s Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Total Routing: CPU time = 0h 0m 0.211s, Elapsed time = 0h 0m 0.223s Generate output files: CPU time = 0h 0m 0.396s, Elapsed time = 0h 0m 0.411s
Total Time and Memory Usage CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 252MB

Resource

Resource Usage Summary:

Resource Usage Utilization
Logic 55/4608 2%
    --LUT,ALU,ROM16 55(55 LUT, 0 ALU, 0 ROM16) -
    --SSRAM(RAM16) 0 -
Register 25/3573 <1%
    --Logic Register as Latch 0/3456 0%
    --Logic Register as FF 25/3456 <1%
    --I/O Register as Latch 0/117 0%
    --I/O Register as FF 0/117 0%
CLS 31/2304 2%
I/O Port 3/39 8%
I/O Buf 3 -
    --Input Buf 2 -
    --Output Buf 1 -
    --Inout Buf 0 -

I/O Bank Usage Summary:

I/O Bank UsageUtilization
bank 0 0/90%
bank 1 1/1010%
bank 2 0/90%
bank 3 2/1119%

Clock Resource Usage Summary:

Clock Resource Usage Utilization
PRIMARY 1/8 13%
LW 0/8 0%
GCLK_PIN 0/5 0%

Global Clock Signals:

Signal Global Clock Location
clk_d PRIMARY LEFT

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor BankVccio
clk - 45/1 Y in IOT13[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
reset_n - 15/3 Y in IOB5[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
led - 13/3 Y out IOB4[A] LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8

All Package Pins:

Loc./Bank Signal Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor Bank Vccio
3/0 - in IOT2[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
4/0 - out IOT2[B] LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
6/0 - in IOT3[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
7/0 - in IOT3[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
8/0 - in IOT4[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
9/0 - in IOT5[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
10/0 - in IOT7[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
1/0 - in IOT10[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
2/0 - in IOT10[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
48/1 - in IOT11[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
47/1 - in IOT11[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
45/1 clk in IOT13[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
46/1 - in IOT13[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
43/1 - in IOT17[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
44/1 - in IOT17[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
41/1 - in IOT20[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
42/1 - in IOT20[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
39/1 - in IOT26[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
40/1 - in IOT26[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
13/3 led out IOB4[A] LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
14/3 - in IOB4[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
15/3 reset_n in IOB5[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
16/3 - in IOB6[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
17/3 - in IOB6[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
18/3 - in IOB13[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
19/3 - in IOB13[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
20/3 - in IOB16[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
21/3 - in IOB16[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
22/3 - in IOB22[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
23/3 - in IOB22[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
35/2 - in IOR2[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
34/2 - in IOR2[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
33/2 - in IOR9[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
32/2 - in IOR11[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
31/2 - in IOR11[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
30/2 - in IOR15[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
29/2 - in IOR15[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
28/2 - in IOR17[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
27/2 - in IOR17[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8