Pin Messages

Report Title Pin Report
Design File /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/Bincounter/chap_bincounter/impl/gwsynthesis/chap_bincounter.vg
Physical Constraints File /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/Bincounter/chap_bincounter/src/chap_bincounter.cst
Timing Constraints File ---
Tool Version V1.9.10.03 Education
Part Number GW1NSR-LV4CQN48PC6/I5
Device GW1NSR-4C
Created Time Tue Apr 8 10:29:27 2025
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Pin Details

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor BankVccio
clk - 45/1 Y in IOT13[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
reset_n - 15/3 Y in IOB5[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
led - 13/3 Y out IOB4[A] LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8

All Package Pins:

Loc./Bank Signal Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor Bank Vccio
3/0 - in IOT2[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
4/0 - out IOT2[B] LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
6/0 - in IOT3[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
7/0 - in IOT3[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
8/0 - in IOT4[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
9/0 - in IOT5[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
10/0 - in IOT7[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
1/0 - in IOT10[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
2/0 - in IOT10[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
48/1 - in IOT11[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
47/1 - in IOT11[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
45/1 clk in IOT13[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
46/1 - in IOT13[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
43/1 - in IOT17[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
44/1 - in IOT17[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
41/1 - in IOT20[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
42/1 - in IOT20[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
39/1 - in IOT26[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
40/1 - in IOT26[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
13/3 led out IOB4[A] LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
14/3 - in IOB4[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
15/3 reset_n in IOB5[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
16/3 - in IOB6[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
17/3 - in IOB6[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
18/3 - in IOB13[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
19/3 - in IOB13[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
20/3 - in IOB16[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
21/3 - in IOB16[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
22/3 - in IOB22[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
23/3 - in IOB22[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
35/2 - in IOR2[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
34/2 - in IOR2[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
33/2 - in IOR9[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
32/2 - in IOR11[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
31/2 - in IOR11[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
30/2 - in IOR15[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
29/2 - in IOR15[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
28/2 - in IOR17[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
27/2 - in IOR17[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8