Synthesis Messages

Report Title	GowinSynthesis Report
Design File	/home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/Bincounter/chap_bincounter/src/bin_counter.v /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_4k/Example code/Bincounter/chap_bincounter/src/bin_counter_tb.v
GowinSynthesis Constraints File	---
Tool Version	V1.9.10.03 Education
Part Number	GW1NSR-LV4CQN48PC6/I5
Device	GW1NSR-4C
Created Time	Tue Apr 8 10:29:23 2025
Legal Announcement	Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module	bin_counter
Synthesis Process	Running parser:     CPU time = 0h 0m 0.061s, Elapsed time = 0h 0m 0.071s, Peak memory usage = 157.230MB Running netlist conversion:     CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization:     Optimizing Phase 0: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 157.824MB     Optimizing Phase 1: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0s, Peak memory usage = 157.824MB     Optimizing Phase 2: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0s, Peak memory usage = 157.824MB Running inference:     Inferring Phase 0: CPU time = 0h 0m 0.002s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 158.141MB     Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 158.305MB     Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 158.305MB     Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 158.305MB Running technical mapping:     Tech-Mapping Phase 0: CPU time = 0h 0m 0.003s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 158.305MB     Tech-Mapping Phase 1: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0s, Peak memory usage = 158.305MB     Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 158.305MB     Tech-Mapping Phase 3: CPU time = 0h 0m 0.478s, Elapsed time = 0h 0m 0.492s, Peak memory usage = 188.910MB     Tech-Mapping Phase 4: CPU time = 0h 0m 0.016s, Elapsed time = 0h 0m 0.026s, Peak memory usage = 188.910MB Generate output files:     CPU time = 0h 0m 0.034s, Elapsed time = 0h 0m 0.05s, Peak memory usage = 188.910MB
Total Time and Memory Usage	CPU time = 0h 0m 0.598s, Elapsed time = 0h 0m 0.643s, Peak memory usage = 188.910MB

Resource

Resource Usage Summary

Resource	Usage
I/O Port	3
I/O Buf	3
IBUF	2
OBUF	1
Register	25
DFFC	24
DFFCE	1
LUT	54
LUT2	10
LUT3	14
LUT4	30
INV	2
INV	2

Resource Utilization Summary

Resource	Usage	Utilization
Logic	56(56 LUT, 0 ALU) / 4608	2%
Register	25 / 3573	<1%
--Register as Latch	0 / 3573	0%
--Register as FF	25 / 3573	<1%
BSRAM	0 / 10	0%

Timing

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Object
1	clk	Base	20.000	50.0	0.000	10.000			clk_ibuf/I

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk	50.000(MHz)	99.460(MHz)	5	TOP

Detail Timing Paths Information

Path 1

Path Summary:

Slack	9.946
Data Arrival Time	10.380
Data Required Time	20.326
From	cnt_1_s0
To	cnt_17_s0
Launch Clk	clk[R]
Latch Clk	clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.000	0.000	tINS	RR	25	clk_ibuf/O
0.726	0.726	tNET	RR	1	cnt_1_s0/CLK
1.184	0.458	tC2Q	RF	4	cnt_1_s0/Q
2.144	0.960	tNET	FF	1	n51_s2/I1
3.243	1.099	tINS	FF	7	n51_s2/F
4.203	0.960	tNET	FF	1	n42_s2/I1
5.302	1.099	tINS	FF	8	n42_s2/F
6.262	0.960	tNET	FF	1	n41_s2/I1
7.361	1.099	tINS	FF	1	n41_s2/F
8.321	0.960	tNET	FF	1	n41_s1/I1
9.420	1.099	tINS	FF	1	n41_s1/F
10.380	0.960	tNET	FF	1	cnt_17_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	0.000				clk
20.000	0.000	tCL	RR	1	clk_ibuf/I
20.000	0.000	tINS	RR	25	clk_ibuf/O
20.726	0.726	tNET	RR	1	cnt_17_s0/CLK
20.326	-0.400	tSu		1	cnt_17_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay:	cell: 4.396, 45.534%; route: 4.800, 49.719%; tC2Q: 0.458, 4.747%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 2

Path Summary:

Slack	10.013
Data Arrival Time	10.313
Data Required Time	20.326
From	cnt_1_s0
To	cnt_0_s0
Launch Clk	clk[R]
Latch Clk	clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.000	0.000	tINS	RR	25	clk_ibuf/O
0.726	0.726	tNET	RR	1	cnt_1_s0/CLK
1.184	0.458	tC2Q	RF	4	cnt_1_s0/Q
2.144	0.960	tNET	FF	1	n51_s2/I1
3.243	1.099	tINS	FF	7	n51_s2/F
4.203	0.960	tNET	FF	1	n35_s6/I1
5.302	1.099	tINS	FF	1	n35_s6/F
6.262	0.960	tNET	FF	1	n35_s4/I0
7.294	1.032	tINS	FF	24	n35_s4/F
8.254	0.960	tNET	FF	1	n58_s2/I1
9.353	1.099	tINS	FF	1	n58_s2/F
10.313	0.960	tNET	FF	1	cnt_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	0.000				clk
20.000	0.000	tCL	RR	1	clk_ibuf/I
20.000	0.000	tINS	RR	25	clk_ibuf/O
20.726	0.726	tNET	RR	1	cnt_0_s0/CLK
20.326	-0.400	tSu		1	cnt_0_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay:	cell: 4.329, 45.153%; route: 4.800, 50.066%; tC2Q: 0.458, 4.781%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 3

Path Summary:

Slack	10.013
Data Arrival Time	10.313
Data Required Time	20.326
From	cnt_1_s0
To	cnt_13_s0
Launch Clk	clk[R]
Latch Clk	clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.000	0.000	tINS	RR	25	clk_ibuf/O
0.726	0.726	tNET	RR	1	cnt_1_s0/CLK
1.184	0.458	tC2Q	RF	4	cnt_1_s0/Q
2.144	0.960	tNET	FF	1	n51_s2/I1
3.243	1.099	tINS	FF	7	n51_s2/F
4.203	0.960	tNET	FF	1	n42_s2/I1
5.302	1.099	tINS	FF	8	n42_s2/F
6.262	0.960	tNET	FF	1	n43_s4/I0
7.294	1.032	tINS	FF	3	n43_s4/F
8.254	0.960	tNET	FF	1	n45_s1/I1
9.353	1.099	tINS	FF	1	n45_s1/F
10.313	0.960	tNET	FF	1	cnt_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	0.000				clk
20.000	0.000	tCL	RR	1	clk_ibuf/I
20.000	0.000	tINS	RR	25	clk_ibuf/O
20.726	0.726	tNET	RR	1	cnt_13_s0/CLK
20.326	-0.400	tSu		1	cnt_13_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay:	cell: 4.329, 45.153%; route: 4.800, 50.066%; tC2Q: 0.458, 4.781%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 4

Path Summary:

Slack	10.013
Data Arrival Time	10.313
Data Required Time	20.326
From	cnt_1_s0
To	cnt_14_s0
Launch Clk	clk[R]
Latch Clk	clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.000	0.000	tINS	RR	25	clk_ibuf/O
0.726	0.726	tNET	RR	1	cnt_1_s0/CLK
1.184	0.458	tC2Q	RF	4	cnt_1_s0/Q
2.144	0.960	tNET	FF	1	n51_s2/I1
3.243	1.099	tINS	FF	7	n51_s2/F
4.203	0.960	tNET	FF	1	n42_s2/I1
5.302	1.099	tINS	FF	8	n42_s2/F
6.262	0.960	tNET	FF	1	n43_s4/I0
7.294	1.032	tINS	FF	3	n43_s4/F
8.254	0.960	tNET	FF	1	n44_s1/I1
9.353	1.099	tINS	FF	1	n44_s1/F
10.313	0.960	tNET	FF	1	cnt_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	0.000				clk
20.000	0.000	tCL	RR	1	clk_ibuf/I
20.000	0.000	tINS	RR	25	clk_ibuf/O
20.726	0.726	tNET	RR	1	cnt_14_s0/CLK
20.326	-0.400	tSu		1	cnt_14_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay:	cell: 4.329, 45.153%; route: 4.800, 50.066%; tC2Q: 0.458, 4.781%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 5

Path Summary:

Slack	10.013
Data Arrival Time	10.313
Data Required Time	20.326
From	cnt_1_s0
To	cnt_15_s0
Launch Clk	clk[R]
Latch Clk	clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.000	0.000	tINS	RR	25	clk_ibuf/O
0.726	0.726	tNET	RR	1	cnt_1_s0/CLK
1.184	0.458	tC2Q	RF	4	cnt_1_s0/Q
2.144	0.960	tNET	FF	1	n51_s2/I1
3.243	1.099	tINS	FF	7	n51_s2/F
4.203	0.960	tNET	FF	1	n42_s2/I1
5.302	1.099	tINS	FF	8	n42_s2/F
6.262	0.960	tNET	FF	1	n43_s4/I0
7.294	1.032	tINS	FF	3	n43_s4/F
8.254	0.960	tNET	FF	1	n43_s1/I1
9.353	1.099	tINS	FF	1	n43_s1/F
10.313	0.960	tNET	FF	1	cnt_15_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	0.000				clk
20.000	0.000	tCL	RR	1	clk_ibuf/I
20.000	0.000	tINS	RR	25	clk_ibuf/O
20.726	0.726	tNET	RR	1	cnt_15_s0/CLK
20.326	-0.400	tSu		1	cnt_15_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay:	cell: 4.329, 45.153%; route: 4.800, 50.066%; tC2Q: 0.458, 4.781%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%