Synthesis Messages

Report Title	GowinSynthesis Report
Design File	C:\Users\ADMIN\Desktop\onekiwi_fpga_board-main\fpga_1P5\EXAMPLE CODE\UART_transmit_receive_multiple_byte\src\uart_byte_rx.v C:\Users\ADMIN\Desktop\onekiwi_fpga_board-main\fpga_1P5\EXAMPLE CODE\UART_transmit_receive_multiple_byte\src\uart_byte_tx.v C:\Users\ADMIN\Desktop\onekiwi_fpga_board-main\fpga_1P5\EXAMPLE CODE\UART_transmit_receive_multiple_byte\src\uart_data_rx.v C:\Users\ADMIN\Desktop\onekiwi_fpga_board-main\fpga_1P5\EXAMPLE CODE\UART_transmit_receive_multiple_byte\src\uart_data_tx.v C:\Users\ADMIN\Desktop\onekiwi_fpga_board-main\fpga_1P5\EXAMPLE CODE\UART_transmit_receive_multiple_byte\src\uart_loopback.v
GowinSynthesis Constraints File	---
Tool Version	V1.9.11.03 (64-bit)
Part Number	GW1N-UV1P5QN48XFC7/I6
Device	GW1N-1P5
Device Version	C
Created Time	Wed Jul 30 11:57:26 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module	uart_loopback
Synthesis Process	Running parser:     CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.056s, Peak memory usage = 190.242MB Running netlist conversion:     CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization:     Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 190.719MB     Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 190.801MB     Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 190.898MB Running inference:     Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 191.070MB     Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 191.160MB     Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 191.223MB     Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 191.301MB Running technical mapping:     Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 191.316MB     Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 191.320MB     Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 191.320MB     Tech-Mapping Phase 3: CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.603s, Peak memory usage = 220.820MB     Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.142s, Peak memory usage = 220.820MB Generate output files:     CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 220.820MB
Total Time and Memory Usage	CPU time = 0h 0m 0.388s, Elapsed time = 0h 0m 0.875s, Peak memory usage = 220.820MB

Resource

Resource Usage Summary

Resource	Usage
I/O Port	6
I/O Buf	6
IBUF	3
OBUF	3
Register	244
DFFE	26
DFFRE	8
DFFP	1
DFFC	56
DFFCE	153
LUT	317
LUT2	35
LUT3	107
LUT4	175
INV	1
INV	1

Resource Utilization Summary

Resource	Usage	Utilization
Logic	318(318 LUT, 0 ALU) / 1584	21%
Register	244 / 1704	15%
--Register as Latch	0 / 1704	0%
--Register as FF	244 / 1704	15%
BSRAM	0 / 4	0%

Timing

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Object
1	Clk	Base	20.000	50.000	0.000	10.000			Clk_ibuf/I

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	Clk	50.000(MHz)	135.124(MHz)	5	TOP

Detail Timing Paths Information

Path 1

Path Summary:

Slack	12.599
Data Arrival Time	7.642
Data Required Time	20.242
From	uart_data_rx/timeout_cnt_5_s0
To	uart_data_rx/timeout_cnt_11_s0
Launch Clk	Clk[R]
Latch Clk	Clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				Clk
0.000	0.000	tCL	RR	1	Clk_ibuf/I
0.000	0.000	tINS	RR	244	Clk_ibuf/O
0.538	0.538	tNET	RR	1	uart_data_rx/timeout_cnt_5_s0/CLK
0.878	0.340	tC2Q	RF	4	uart_data_rx/timeout_cnt_5_s0/Q
1.589	0.711	tNET	FF	1	uart_data_rx/n187_s4/I1
2.403	0.814	tINS	FF	4	uart_data_rx/n187_s4/F
3.115	0.711	tNET	FF	1	uart_data_rx/n185_s5/I1
3.929	0.814	tINS	FF	5	uart_data_rx/n185_s5/F
4.640	0.711	tNET	FF	1	uart_data_rx/n184_s3/I1
5.455	0.814	tINS	FF	1	uart_data_rx/n184_s3/F
6.166	0.711	tNET	FF	1	uart_data_rx/n184_s2/I0
6.931	0.765	tINS	FF	1	uart_data_rx/n184_s2/F
7.642	0.711	tNET	FF	1	uart_data_rx/timeout_cnt_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	0.000				Clk
20.000	0.000	tCL	RR	1	Clk_ibuf/I
20.000	0.000	tINS	RR	244	Clk_ibuf/O
20.538	0.538	tNET	RR	1	uart_data_rx/timeout_cnt_11_s0/CLK
20.242	-0.296	tSu		1	uart_data_rx/timeout_cnt_11_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay:	cell: 3.208, 45.153%; route: 3.557, 50.066%; tC2Q: 0.340, 4.781%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 2

Path Summary:

Slack	12.599
Data Arrival Time	7.642
Data Required Time	20.242
From	uart_data_rx/timeout_cnt_5_s0
To	uart_data_rx/timeout_cnt_15_s0
Launch Clk	Clk[R]
Latch Clk	Clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				Clk
0.000	0.000	tCL	RR	1	Clk_ibuf/I
0.000	0.000	tINS	RR	244	Clk_ibuf/O
0.538	0.538	tNET	RR	1	uart_data_rx/timeout_cnt_5_s0/CLK
0.878	0.340	tC2Q	RF	4	uart_data_rx/timeout_cnt_5_s0/Q
1.589	0.711	tNET	FF	1	uart_data_rx/n187_s4/I1
2.403	0.814	tINS	FF	4	uart_data_rx/n187_s4/F
3.115	0.711	tNET	FF	1	uart_data_rx/n181_s3/I1
3.929	0.814	tINS	FF	2	uart_data_rx/n181_s3/F
4.640	0.711	tNET	FF	1	uart_data_rx/n180_s3/I1
5.455	0.814	tINS	FF	1	uart_data_rx/n180_s3/F
6.166	0.711	tNET	FF	1	uart_data_rx/n180_s2/I0
6.931	0.765	tINS	FF	1	uart_data_rx/n180_s2/F
7.642	0.711	tNET	FF	1	uart_data_rx/timeout_cnt_15_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	0.000				Clk
20.000	0.000	tCL	RR	1	Clk_ibuf/I
20.000	0.000	tINS	RR	244	Clk_ibuf/O
20.538	0.538	tNET	RR	1	uart_data_rx/timeout_cnt_15_s0/CLK
20.242	-0.296	tSu		1	uart_data_rx/timeout_cnt_15_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay:	cell: 3.208, 45.153%; route: 3.557, 50.066%; tC2Q: 0.340, 4.781%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 3

Path Summary:

Slack	12.649
Data Arrival Time	7.593
Data Required Time	20.242
From	uart_data_rx/timeout_cnt_1_s0
To	uart_data_rx/timeout_cnt_2_s0
Launch Clk	Clk[R]
Latch Clk	Clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				Clk
0.000	0.000	tCL	RR	1	Clk_ibuf/I
0.000	0.000	tINS	RR	244	Clk_ibuf/O
0.538	0.538	tNET	RR	1	uart_data_rx/timeout_cnt_1_s0/CLK
0.878	0.340	tC2Q	RF	5	uart_data_rx/timeout_cnt_1_s0/Q
1.589	0.711	tNET	FF	1	uart_data_rx/n98_s101/I1
2.403	0.814	tINS	FF	1	uart_data_rx/n98_s101/F
3.115	0.711	tNET	FF	1	uart_data_rx/n98_s98/I0
3.879	0.765	tINS	FF	1	uart_data_rx/n98_s98/F
4.591	0.711	tNET	FF	1	uart_data_rx/n98_s109/I0
5.355	0.765	tINS	FF	19	uart_data_rx/n98_s109/F
6.067	0.711	tNET	FF	1	uart_data_rx/n193_s2/I1
6.881	0.814	tINS	FF	1	uart_data_rx/n193_s2/F
7.593	0.711	tNET	FF	1	uart_data_rx/timeout_cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	0.000				Clk
20.000	0.000	tCL	RR	1	Clk_ibuf/I
20.000	0.000	tINS	RR	244	Clk_ibuf/O
20.538	0.538	tNET	RR	1	uart_data_rx/timeout_cnt_2_s0/CLK
20.242	-0.296	tSu		1	uart_data_rx/timeout_cnt_2_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay:	cell: 3.158, 44.767%; route: 3.557, 50.419%; tC2Q: 0.340, 4.814%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 4

Path Summary:

Slack	12.649
Data Arrival Time	7.593
Data Required Time	20.242
From	uart_data_rx/timeout_cnt_1_s0
To	uart_data_rx/timeout_cnt_3_s0
Launch Clk	Clk[R]
Latch Clk	Clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				Clk
0.000	0.000	tCL	RR	1	Clk_ibuf/I
0.000	0.000	tINS	RR	244	Clk_ibuf/O
0.538	0.538	tNET	RR	1	uart_data_rx/timeout_cnt_1_s0/CLK
0.878	0.340	tC2Q	RF	5	uart_data_rx/timeout_cnt_1_s0/Q
1.589	0.711	tNET	FF	1	uart_data_rx/n98_s101/I1
2.403	0.814	tINS	FF	1	uart_data_rx/n98_s101/F
3.115	0.711	tNET	FF	1	uart_data_rx/n98_s98/I0
3.879	0.765	tINS	FF	1	uart_data_rx/n98_s98/F
4.591	0.711	tNET	FF	1	uart_data_rx/n98_s109/I0
5.355	0.765	tINS	FF	19	uart_data_rx/n98_s109/F
6.067	0.711	tNET	FF	1	uart_data_rx/n192_s2/I1
6.881	0.814	tINS	FF	1	uart_data_rx/n192_s2/F
7.593	0.711	tNET	FF	1	uart_data_rx/timeout_cnt_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	0.000				Clk
20.000	0.000	tCL	RR	1	Clk_ibuf/I
20.000	0.000	tINS	RR	244	Clk_ibuf/O
20.538	0.538	tNET	RR	1	uart_data_rx/timeout_cnt_3_s0/CLK
20.242	-0.296	tSu		1	uart_data_rx/timeout_cnt_3_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay:	cell: 3.158, 44.767%; route: 3.557, 50.419%; tC2Q: 0.340, 4.814%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 5

Path Summary:

Slack	12.649
Data Arrival Time	7.593
Data Required Time	20.242
From	uart_data_rx/timeout_cnt_1_s0
To	uart_data_rx/timeout_cnt_5_s0
Launch Clk	Clk[R]
Latch Clk	Clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				Clk
0.000	0.000	tCL	RR	1	Clk_ibuf/I
0.000	0.000	tINS	RR	244	Clk_ibuf/O
0.538	0.538	tNET	RR	1	uart_data_rx/timeout_cnt_1_s0/CLK
0.878	0.340	tC2Q	RF	5	uart_data_rx/timeout_cnt_1_s0/Q
1.589	0.711	tNET	FF	1	uart_data_rx/n98_s101/I1
2.403	0.814	tINS	FF	1	uart_data_rx/n98_s101/F
3.115	0.711	tNET	FF	1	uart_data_rx/n98_s98/I0
3.879	0.765	tINS	FF	1	uart_data_rx/n98_s98/F
4.591	0.711	tNET	FF	1	uart_data_rx/n98_s109/I0
5.355	0.765	tINS	FF	19	uart_data_rx/n98_s109/F
6.067	0.711	tNET	FF	1	uart_data_rx/n190_s2/I1
6.881	0.814	tINS	FF	1	uart_data_rx/n190_s2/F
7.593	0.711	tNET	FF	1	uart_data_rx/timeout_cnt_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	0.000				Clk
20.000	0.000	tCL	RR	1	Clk_ibuf/I
20.000	0.000	tINS	RR	244	Clk_ibuf/O
20.538	0.538	tNET	RR	1	uart_data_rx/timeout_cnt_5_s0/CLK
20.242	-0.296	tSu		1	uart_data_rx/timeout_cnt_5_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay:	cell: 3.158, 44.767%; route: 3.557, 50.419%; tC2Q: 0.340, 4.814%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%