Timing Messages

Report Title Timing Analysis Report
Design File C:\quanggit_lab\example_code\UART_tX_1BYTE\impl\gwsynthesis\uart_tx.vg
Physical Constraints File C:\quanggit_lab\example_code\UART_tX_1BYTE\src\uart_tx.cst
Timing Constraint File ---
Tool Version V1.9.11.03 (64-bit)
Part Number GW1N-UV1P5QN48XFC7/I6
Device GW1N-1P5
Device Version C
Created Time Mon Jul 21 10:14:48 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 1.71V 85C C7/I6
Hold Delay Model Fast 3.6V 0C C7/I6
Numbers of Paths Analyzed 156
Numbers of Endpoints Analyzed 155
Numbers of Falling Endpoints 0
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
1 clk Base 20.000 50.000 0.000 10.000 clk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 50.000(MHz) 150.427(MHz) 5 TOP

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
clk Setup 0.000 0
clk Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 13.352 cnt_0_s0/Q cnt_7_s0/D clk:[R] clk:[R] 20.000 0.000 6.351
2 13.456 cnt_0_s0/Q cnt_15_s0/D clk:[R] clk:[R] 20.000 0.000 6.248
3 13.471 cnt_0_s0/Q cnt_6_s0/D clk:[R] clk:[R] 20.000 0.000 6.232
4 13.758 cnt_0_s0/Q cnt_12_s0/D clk:[R] clk:[R] 20.000 0.000 5.946
5 13.758 cnt_0_s0/Q cnt_23_s0/D clk:[R] clk:[R] 20.000 0.000 5.946
6 13.761 cnt_0_s0/Q cnt_16_s0/D clk:[R] clk:[R] 20.000 0.000 5.943
7 13.806 cnt_0_s0/Q cnt_11_s0/D clk:[R] clk:[R] 20.000 0.000 5.898
8 13.991 cnt_0_s0/Q cnt_22_s0/D clk:[R] clk:[R] 20.000 0.000 5.712
9 14.053 cnt_0_s0/Q cnt_13_s0/D clk:[R] clk:[R] 20.000 0.000 5.651
10 14.053 cnt_0_s0/Q cnt_19_s0/D clk:[R] clk:[R] 20.000 0.000 5.651
11 14.058 cnt_0_s0/Q cnt_20_s0/D clk:[R] clk:[R] 20.000 0.000 5.645
12 14.067 cnt_0_s0/Q cnt_17_s0/D clk:[R] clk:[R] 20.000 0.000 5.637
13 14.067 cnt_0_s0/Q cnt_24_s0/D clk:[R] clk:[R] 20.000 0.000 5.637
14 14.100 cnt_0_s0/Q cnt_14_s0/D clk:[R] clk:[R] 20.000 0.000 5.604
15 14.258 cnt_0_s0/Q cnt_10_s0/D clk:[R] clk:[R] 20.000 0.000 5.446
16 14.287 cnt_0_s0/Q cnt_25_s0/D clk:[R] clk:[R] 20.000 0.000 5.416
17 14.407 cnt_0_s0/Q send_en_s0/D clk:[R] clk:[R] 20.000 0.000 5.297
18 14.417 cnt_0_s0/Q cnt_21_s0/D clk:[R] clk:[R] 20.000 0.000 5.286
19 14.564 uart_byte_tx/data_byte_reg_3_s0/Q uart_byte_tx/uart_tx_s0/D clk:[R] clk:[R] 20.000 0.000 5.140
20 14.832 uart_byte_tx/div_cnt_6_s0/Q uart_byte_tx/div_cnt_15_s0/D clk:[R] clk:[R] 20.000 0.000 4.872
21 14.994 uart_byte_tx/div_cnt_14_s0/Q uart_byte_tx/div_cnt_7_s0/D clk:[R] clk:[R] 20.000 0.000 4.710
22 15.013 uart_byte_tx/div_cnt_6_s0/Q uart_byte_tx/div_cnt_12_s0/D clk:[R] clk:[R] 20.000 0.000 4.691
23 15.090 uart_byte_tx/div_cnt_14_s0/Q uart_byte_tx/div_cnt_2_s0/D clk:[R] clk:[R] 20.000 0.000 4.613
24 15.095 uart_byte_tx/div_cnt_6_s0/Q uart_byte_tx/div_cnt_13_s0/D clk:[R] clk:[R] 20.000 0.000 4.608
25 15.139 uart_byte_tx/div_cnt_14_s0/Q uart_byte_tx/div_cnt_0_s0/D clk:[R] clk:[R] 20.000 0.000 4.565

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.524 uart_byte_tx/div_cnt_15_s0/Q uart_byte_tx/div_cnt_15_s0/D clk:[R] clk:[R] 0.000 0.000 0.524
2 0.524 cnt_25_s0/Q cnt_25_s0/D clk:[R] clk:[R] 0.000 0.000 0.524
3 0.524 data_byte_0_s0/Q data_byte_0_s0/D clk:[R] clk:[R] 0.000 0.000 0.524
4 0.524 cnt_1_s0/Q cnt_1_s0/D clk:[R] clk:[R] 0.000 0.000 0.524
5 0.524 cnt_2_s0/Q cnt_2_s0/D clk:[R] clk:[R] 0.000 0.000 0.524
6 0.524 cnt_3_s0/Q cnt_3_s0/D clk:[R] clk:[R] 0.000 0.000 0.524
7 0.524 cnt_5_s0/Q cnt_5_s0/D clk:[R] clk:[R] 0.000 0.000 0.524
8 0.524 cnt_16_s0/Q cnt_16_s0/D clk:[R] clk:[R] 0.000 0.000 0.524
9 0.524 cnt_22_s0/Q cnt_22_s0/D clk:[R] clk:[R] 0.000 0.000 0.524
10 0.525 uart_byte_tx/bps_cnt_3_s1/Q uart_byte_tx/bps_cnt_3_s1/D clk:[R] clk:[R] 0.000 0.000 0.525
11 0.525 uart_byte_tx/div_cnt_4_s0/Q uart_byte_tx/div_cnt_4_s0/D clk:[R] clk:[R] 0.000 0.000 0.525
12 0.525 uart_byte_tx/div_cnt_9_s0/Q uart_byte_tx/div_cnt_9_s0/D clk:[R] clk:[R] 0.000 0.000 0.525
13 0.525 cnt_8_s0/Q cnt_8_s0/D clk:[R] clk:[R] 0.000 0.000 0.525
14 0.525 cnt_15_s0/Q cnt_15_s0/D clk:[R] clk:[R] 0.000 0.000 0.525
15 0.526 uart_byte_tx/bps_cnt_2_s1/Q uart_byte_tx/bps_cnt_2_s1/D clk:[R] clk:[R] 0.000 0.000 0.526
16 0.526 uart_byte_tx/div_cnt_11_s0/Q uart_byte_tx/div_cnt_11_s0/D clk:[R] clk:[R] 0.000 0.000 0.526
17 0.526 cnt_13_s0/Q cnt_13_s0/D clk:[R] clk:[R] 0.000 0.000 0.526
18 0.527 uart_byte_tx/div_cnt_10_s0/Q uart_byte_tx/div_cnt_10_s0/D clk:[R] clk:[R] 0.000 0.000 0.527
19 0.541 data_byte_2_s0/Q data_byte_2_s0/D clk:[R] clk:[R] 0.000 0.000 0.541
20 0.541 data_byte_6_s0/Q data_byte_6_s0/D clk:[R] clk:[R] 0.000 0.000 0.541
21 0.632 data_byte_1_s0/Q data_byte_1_s0/D clk:[R] clk:[R] 0.000 0.000 0.632
22 0.661 send_en_s0/Q uart_byte_tx/data_byte_reg_2_s0/CE clk:[R] clk:[R] 0.000 0.000 0.671
23 0.661 send_en_s0/Q uart_byte_tx/data_byte_reg_4_s0/CE clk:[R] clk:[R] 0.000 0.000 0.671
24 0.662 uart_byte_tx/div_cnt_2_s0/Q uart_byte_tx/div_cnt_2_s0/D clk:[R] clk:[R] 0.000 0.000 0.662
25 0.662 cnt_0_s0/Q cnt_0_s0/D clk:[R] clk:[R] 0.000 0.000 0.662

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 6.948 7.874 0.926 High Pulse Width clk cnt_24_s0
2 6.948 7.874 0.926 High Pulse Width clk cnt_23_s0
3 6.948 7.874 0.926 High Pulse Width clk cnt_21_s0
4 6.948 7.874 0.926 High Pulse Width clk cnt_17_s0
5 6.948 7.874 0.926 High Pulse Width clk cnt_9_s0
6 6.948 7.874 0.926 High Pulse Width clk data_byte_2_s0
7 6.948 7.874 0.926 High Pulse Width clk uart_byte_tx/bps_cnt_2_s1
8 6.948 7.874 0.926 High Pulse Width clk uart_byte_tx/bps_cnt_3_s1
9 6.948 7.874 0.926 High Pulse Width clk data_byte_3_s0
10 6.948 7.874 0.926 High Pulse Width clk uart_byte_tx/uart_tx_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 13.352
Data Arrival Time 10.762
Data Required Time 24.114
From cnt_0_s0
To cnt_7_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
4.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
4.411 0.181 tNET RR 1 R8C8[2][A] cnt_0_s0/CLK
4.750 0.340 tC2Q RF 5 R8C8[2][A] cnt_0_s0/Q
5.608 0.858 tNET FF 1 R7C7[0][B] n70_s3/I0
6.072 0.464 tINS FF 7 R7C7[0][B] n70_s3/F
7.042 0.970 tNET FF 1 R9C9[2][B] n26_s4/I0
7.828 0.786 tINS FR 3 R9C9[2][B] n26_s4/F
8.142 0.313 tNET RR 1 R9C8[2][B] n26_s1/I2
8.956 0.814 tINS RF 15 R9C8[2][B] n26_s1/F
9.948 0.991 tNET FF 1 R9C9[2][A] n72_s2/I2
10.762 0.814 tINS FF 1 R9C9[2][A] n72_s2/F
10.762 0.000 tNET FF 1 R9C9[2][A] cnt_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
24.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
24.411 0.181 tNET RR 1 R9C9[2][A] cnt_7_s0/CLK
24.114 -0.296 tSu 1 R9C9[2][A] cnt_7_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay cell: 2.879, 45.326%; route: 3.133, 49.327%; tC2Q: 0.340, 5.347%
Required Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%

Path2

Path Summary:

Slack 13.456
Data Arrival Time 10.659
Data Required Time 24.114
From cnt_0_s0
To cnt_15_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
4.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
4.411 0.181 tNET RR 1 R8C8[2][A] cnt_0_s0/CLK
4.750 0.340 tC2Q RF 5 R8C8[2][A] cnt_0_s0/Q
5.608 0.858 tNET FF 1 R7C7[0][B] n70_s3/I0
6.072 0.464 tINS FF 7 R7C7[0][B] n70_s3/F
7.042 0.970 tNET FF 1 R9C9[2][B] n26_s4/I0
7.828 0.786 tINS FR 3 R9C9[2][B] n26_s4/F
8.142 0.313 tNET RR 1 R9C8[2][B] n26_s1/I2
8.956 0.814 tINS RF 15 R9C8[2][B] n26_s1/F
9.844 0.888 tNET FF 1 R7C8[1][A] n64_s2/I0
10.659 0.814 tINS FF 1 R7C8[1][A] n64_s2/F
10.659 0.000 tNET FF 1 R7C8[1][A] cnt_15_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
24.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
24.411 0.181 tNET RR 1 R7C8[1][A] cnt_15_s0/CLK
24.114 -0.296 tSu 1 R7C8[1][A] cnt_15_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay cell: 2.879, 46.075%; route: 3.030, 48.489%; tC2Q: 0.340, 5.436%
Required Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%

Path3

Path Summary:

Slack 13.471
Data Arrival Time 10.643
Data Required Time 24.114
From cnt_0_s0
To cnt_6_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
4.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
4.411 0.181 tNET RR 1 R8C8[2][A] cnt_0_s0/CLK
4.750 0.340 tC2Q RF 5 R8C8[2][A] cnt_0_s0/Q
5.608 0.858 tNET FF 1 R7C7[0][B] n70_s3/I0
6.072 0.464 tINS FF 7 R7C7[0][B] n70_s3/F
7.042 0.970 tNET FF 1 R9C9[2][B] n26_s4/I0
7.828 0.786 tINS FR 3 R9C9[2][B] n26_s4/F
8.142 0.313 tNET RR 1 R9C8[2][B] n26_s1/I2
8.956 0.814 tINS RF 15 R9C8[2][B] n26_s1/F
9.829 0.873 tNET FF 1 R8C9[2][B] n73_s2/I0
10.643 0.814 tINS FF 1 R8C9[2][B] n73_s2/F
10.643 0.000 tNET FF 1 R8C9[2][B] cnt_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
24.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
24.411 0.181 tNET RR 1 R8C9[2][B] cnt_6_s0/CLK
24.114 -0.296 tSu 1 R8C9[2][B] cnt_6_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay cell: 2.879, 46.191%; route: 3.014, 48.360%; tC2Q: 0.340, 5.449%
Required Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%

Path4

Path Summary:

Slack 13.758
Data Arrival Time 10.357
Data Required Time 24.114
From cnt_0_s0
To cnt_12_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
4.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
4.411 0.181 tNET RR 1 R8C8[2][A] cnt_0_s0/CLK
4.750 0.340 tC2Q RF 5 R8C8[2][A] cnt_0_s0/Q
5.608 0.858 tNET FF 1 R7C7[0][B] n70_s3/I0
6.072 0.464 tINS FF 7 R7C7[0][B] n70_s3/F
7.042 0.970 tNET FF 1 R9C9[2][B] n26_s4/I0
7.828 0.786 tINS FR 3 R9C9[2][B] n26_s4/F
8.142 0.313 tNET RR 1 R9C8[2][B] n26_s1/I2
8.956 0.814 tINS RF 15 R9C8[2][B] n26_s1/F
9.592 0.636 tNET FF 1 R7C8[0][B] n67_s2/I2
10.357 0.765 tINS FF 1 R7C8[0][B] n67_s2/F
10.357 0.000 tNET FF 1 R7C8[0][B] cnt_12_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
24.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
24.411 0.181 tNET RR 1 R7C8[0][B] cnt_12_s0/CLK
24.114 -0.296 tSu 1 R7C8[0][B] cnt_12_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay cell: 2.829, 47.581%; route: 2.777, 46.708%; tC2Q: 0.340, 5.712%
Required Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%

Path5

Path Summary:

Slack 13.758
Data Arrival Time 10.357
Data Required Time 24.114
From cnt_0_s0
To cnt_23_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
4.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
4.411 0.181 tNET RR 1 R8C8[2][A] cnt_0_s0/CLK
4.750 0.340 tC2Q RF 5 R8C8[2][A] cnt_0_s0/Q
5.608 0.858 tNET FF 1 R7C7[0][B] n70_s3/I0
6.072 0.464 tINS FF 7 R7C7[0][B] n70_s3/F
7.042 0.970 tNET FF 1 R9C9[2][B] n26_s4/I0
7.828 0.786 tINS FR 3 R9C9[2][B] n26_s4/F
8.142 0.313 tNET RR 1 R9C8[2][B] n26_s1/I2
8.956 0.814 tINS RF 15 R9C8[2][B] n26_s1/F
9.592 0.636 tNET FF 1 R7C8[1][B] n56_s2/I0
10.357 0.765 tINS FF 1 R7C8[1][B] n56_s2/F
10.357 0.000 tNET FF 1 R7C8[1][B] cnt_23_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
24.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
24.411 0.181 tNET RR 1 R7C8[1][B] cnt_23_s0/CLK
24.114 -0.296 tSu 1 R7C8[1][B] cnt_23_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay cell: 2.829, 47.581%; route: 2.777, 46.708%; tC2Q: 0.340, 5.712%
Required Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%

Path6

Path Summary:

Slack 13.761
Data Arrival Time 10.353
Data Required Time 24.114
From cnt_0_s0
To cnt_16_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
4.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
4.411 0.181 tNET RR 1 R8C8[2][A] cnt_0_s0/CLK
4.750 0.340 tC2Q RF 5 R8C8[2][A] cnt_0_s0/Q
5.608 0.858 tNET FF 1 R7C7[0][B] n70_s3/I0
6.072 0.464 tINS FF 7 R7C7[0][B] n70_s3/F
7.042 0.970 tNET FF 1 R9C9[2][B] n26_s4/I0
7.828 0.786 tINS FR 3 R9C9[2][B] n26_s4/F
8.142 0.313 tNET RR 1 R9C8[2][B] n26_s1/I2
8.956 0.814 tINS RF 15 R9C8[2][B] n26_s1/F
9.589 0.632 tNET FF 1 R8C9[0][A] n63_s2/I0
10.353 0.765 tINS FF 1 R8C9[0][A] n63_s2/F
10.353 0.000 tNET FF 1 R8C9[0][A] cnt_16_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
24.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
24.411 0.181 tNET RR 1 R8C9[0][A] cnt_16_s0/CLK
24.114 -0.296 tSu 1 R8C9[0][A] cnt_16_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay cell: 2.829, 47.608%; route: 2.774, 46.677%; tC2Q: 0.340, 5.715%
Required Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%

Path7

Path Summary:

Slack 13.806
Data Arrival Time 10.308
Data Required Time 24.114
From cnt_0_s0
To cnt_11_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
4.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
4.411 0.181 tNET RR 1 R8C8[2][A] cnt_0_s0/CLK
4.750 0.340 tC2Q RF 5 R8C8[2][A] cnt_0_s0/Q
5.608 0.858 tNET FF 1 R7C7[0][B] n70_s3/I0
6.072 0.464 tINS FF 7 R7C7[0][B] n70_s3/F
7.042 0.970 tNET FF 1 R9C9[2][B] n26_s4/I0
7.828 0.786 tINS FR 3 R9C9[2][B] n26_s4/F
8.142 0.313 tNET RR 1 R9C8[2][B] n26_s1/I2
8.956 0.814 tINS RF 15 R9C8[2][B] n26_s1/F
9.844 0.888 tNET FF 1 R7C8[2][B] n68_s2/I2
10.308 0.464 tINS FF 1 R7C8[2][B] n68_s2/F
10.308 0.000 tNET FF 1 R7C8[2][B] cnt_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
24.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
24.411 0.181 tNET RR 1 R7C8[2][B] cnt_11_s0/CLK
24.114 -0.296 tSu 1 R7C8[2][B] cnt_11_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay cell: 2.528, 42.870%; route: 3.030, 51.371%; tC2Q: 0.340, 5.759%
Required Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%

Path8

Path Summary:

Slack 13.991
Data Arrival Time 10.123
Data Required Time 24.114
From cnt_0_s0
To cnt_22_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
4.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
4.411 0.181 tNET RR 1 R8C8[2][A] cnt_0_s0/CLK
4.750 0.340 tC2Q RF 5 R8C8[2][A] cnt_0_s0/Q
5.608 0.858 tNET FF 1 R7C7[0][B] n70_s3/I0
6.072 0.464 tINS FF 7 R7C7[0][B] n70_s3/F
6.925 0.853 tNET FF 1 R8C8[3][A] n61_s3/I0
7.389 0.464 tINS FF 7 R8C8[3][A] n61_s3/F
8.257 0.868 tNET FF 1 R9C7[3][A] n57_s5/I2
9.043 0.786 tINS FR 4 R9C7[3][A] n57_s5/F
9.358 0.315 tNET RR 1 R9C8[0][A] n57_s2/I0
10.123 0.765 tINS RF 1 R9C8[0][A] n57_s2/F
10.123 0.000 tNET FF 1 R9C8[0][A] cnt_22_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
24.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
24.411 0.181 tNET RR 1 R9C8[0][A] cnt_22_s0/CLK
24.114 -0.296 tSu 1 R9C8[0][A] cnt_22_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay cell: 2.479, 43.393%; route: 2.894, 50.662%; tC2Q: 0.340, 5.946%
Required Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%

Path9

Path Summary:

Slack 14.053
Data Arrival Time 10.061
Data Required Time 24.114
From cnt_0_s0
To cnt_13_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
4.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
4.411 0.181 tNET RR 1 R8C8[2][A] cnt_0_s0/CLK
4.750 0.340 tC2Q RF 5 R8C8[2][A] cnt_0_s0/Q
5.608 0.858 tNET FF 1 R7C7[0][B] n70_s3/I0
6.072 0.464 tINS FF 7 R7C7[0][B] n70_s3/F
7.042 0.970 tNET FF 1 R9C9[2][B] n26_s4/I0
7.828 0.786 tINS FR 3 R9C9[2][B] n26_s4/F
8.142 0.313 tNET RR 1 R9C8[2][B] n26_s1/I2
8.928 0.786 tINS RR 15 R9C8[2][B] n26_s1/F
9.247 0.319 tNET RR 1 R9C7[0][A] n66_s2/I0
10.061 0.814 tINS RF 1 R9C7[0][A] n66_s2/F
10.061 0.000 tNET FF 1 R9C7[0][A] cnt_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
24.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
24.411 0.181 tNET RR 1 R9C7[0][A] cnt_13_s0/CLK
24.114 -0.296 tSu 1 R9C7[0][A] cnt_13_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay cell: 2.851, 50.447%; route: 2.461, 43.543%; tC2Q: 0.340, 6.010%
Required Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%

Path10

Path Summary:

Slack 14.053
Data Arrival Time 10.061
Data Required Time 24.114
From cnt_0_s0
To cnt_19_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
4.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
4.411 0.181 tNET RR 1 R8C8[2][A] cnt_0_s0/CLK
4.750 0.340 tC2Q RF 5 R8C8[2][A] cnt_0_s0/Q
5.608 0.858 tNET FF 1 R7C7[0][B] n70_s3/I0
6.072 0.464 tINS FF 7 R7C7[0][B] n70_s3/F
7.042 0.970 tNET FF 1 R9C9[2][B] n26_s4/I0
7.828 0.786 tINS FR 3 R9C9[2][B] n26_s4/F
8.142 0.313 tNET RR 1 R9C8[2][B] n26_s1/I2
8.928 0.786 tINS RR 15 R9C8[2][B] n26_s1/F
9.247 0.319 tNET RR 1 R9C7[2][A] n60_s2/I0
10.061 0.814 tINS RF 1 R9C7[2][A] n60_s2/F
10.061 0.000 tNET FF 1 R9C7[2][A] cnt_19_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
24.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
24.411 0.181 tNET RR 1 R9C7[2][A] cnt_19_s0/CLK
24.114 -0.296 tSu 1 R9C7[2][A] cnt_19_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay cell: 2.851, 50.447%; route: 2.461, 43.543%; tC2Q: 0.340, 6.010%
Required Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%

Path11

Path Summary:

Slack 14.058
Data Arrival Time 10.056
Data Required Time 24.114
From cnt_0_s0
To cnt_20_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
4.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
4.411 0.181 tNET RR 1 R8C8[2][A] cnt_0_s0/CLK
4.750 0.340 tC2Q RF 5 R8C8[2][A] cnt_0_s0/Q
5.608 0.858 tNET FF 1 R7C7[0][B] n70_s3/I0
6.072 0.464 tINS FF 7 R7C7[0][B] n70_s3/F
6.925 0.853 tNET FF 1 R8C8[3][A] n61_s3/I0
7.389 0.464 tINS FF 7 R8C8[3][A] n61_s3/F
8.257 0.868 tNET FF 1 R9C7[3][A] n57_s5/I2
9.071 0.814 tINS FF 4 R9C7[3][A] n57_s5/F
9.447 0.375 tNET FF 1 R9C8[1][B] n59_s2/I0
10.056 0.609 tINS FF 1 R9C8[1][B] n59_s2/F
10.056 0.000 tNET FF 1 R9C8[1][B] cnt_20_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
24.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
24.411 0.181 tNET RR 1 R9C8[1][B] cnt_20_s0/CLK
24.114 -0.296 tSu 1 R9C8[1][B] cnt_20_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay cell: 2.351, 41.649%; route: 2.954, 52.335%; tC2Q: 0.340, 6.016%
Required Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%

Path12

Path Summary:

Slack 14.067
Data Arrival Time 10.047
Data Required Time 24.114
From cnt_0_s0
To cnt_17_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
4.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
4.411 0.181 tNET RR 1 R8C8[2][A] cnt_0_s0/CLK
4.750 0.340 tC2Q RF 5 R8C8[2][A] cnt_0_s0/Q
5.608 0.858 tNET FF 1 R7C7[0][B] n70_s3/I0
6.072 0.464 tINS FF 7 R7C7[0][B] n70_s3/F
7.042 0.970 tNET FF 1 R9C9[2][B] n26_s4/I0
7.828 0.786 tINS FR 3 R9C9[2][B] n26_s4/F
8.142 0.313 tNET RR 1 R9C8[2][B] n26_s1/I2
8.956 0.814 tINS RF 15 R9C8[2][B] n26_s1/F
9.584 0.627 tNET FF 1 R8C9[1][B] n62_s2/I2
10.047 0.464 tINS FF 1 R8C9[1][B] n62_s2/F
10.047 0.000 tNET FF 1 R8C9[1][B] cnt_17_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
24.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
24.411 0.181 tNET RR 1 R8C9[1][B] cnt_17_s0/CLK
24.114 -0.296 tSu 1 R8C9[1][B] cnt_17_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay cell: 2.528, 44.854%; route: 2.769, 49.121%; tC2Q: 0.340, 6.025%
Required Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%

Path13

Path Summary:

Slack 14.067
Data Arrival Time 10.047
Data Required Time 24.114
From cnt_0_s0
To cnt_24_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
4.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
4.411 0.181 tNET RR 1 R8C8[2][A] cnt_0_s0/CLK
4.750 0.340 tC2Q RF 5 R8C8[2][A] cnt_0_s0/Q
5.608 0.858 tNET FF 1 R7C7[0][B] n70_s3/I0
6.072 0.464 tINS FF 7 R7C7[0][B] n70_s3/F
7.042 0.970 tNET FF 1 R9C9[2][B] n26_s4/I0
7.828 0.786 tINS FR 3 R9C9[2][B] n26_s4/F
8.142 0.313 tNET RR 1 R9C8[2][B] n26_s1/I2
8.956 0.814 tINS RF 15 R9C8[2][B] n26_s1/F
9.584 0.627 tNET FF 1 R8C9[0][B] n55_s2/I2
10.047 0.464 tINS FF 1 R8C9[0][B] n55_s2/F
10.047 0.000 tNET FF 1 R8C9[0][B] cnt_24_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
24.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
24.411 0.181 tNET RR 1 R8C9[0][B] cnt_24_s0/CLK
24.114 -0.296 tSu 1 R8C9[0][B] cnt_24_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay cell: 2.528, 44.854%; route: 2.769, 49.121%; tC2Q: 0.340, 6.025%
Required Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%

Path14

Path Summary:

Slack 14.100
Data Arrival Time 10.015
Data Required Time 24.114
From cnt_0_s0
To cnt_14_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
4.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
4.411 0.181 tNET RR 1 R8C8[2][A] cnt_0_s0/CLK
4.750 0.340 tC2Q RF 5 R8C8[2][A] cnt_0_s0/Q
5.608 0.858 tNET FF 1 R7C7[0][B] n70_s3/I0
6.072 0.464 tINS FF 7 R7C7[0][B] n70_s3/F
7.042 0.970 tNET FF 1 R9C9[2][B] n26_s4/I0
7.828 0.786 tINS FR 3 R9C9[2][B] n26_s4/F
8.142 0.313 tNET RR 1 R9C8[2][B] n26_s1/I2
8.928 0.786 tINS RR 15 R9C8[2][B] n26_s1/F
9.250 0.322 tNET RR 1 R8C8[1][B] n65_s2/I2
10.015 0.765 tINS RF 1 R8C8[1][B] n65_s2/F
10.015 0.000 tNET FF 1 R8C8[1][B] cnt_14_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
24.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
24.411 0.181 tNET RR 1 R8C8[1][B] cnt_14_s0/CLK
24.114 -0.296 tSu 1 R8C8[1][B] cnt_14_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay cell: 2.801, 49.981%; route: 2.463, 43.958%; tC2Q: 0.340, 6.060%
Required Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%

Path15

Path Summary:

Slack 14.258
Data Arrival Time 9.856
Data Required Time 24.114
From cnt_0_s0
To cnt_10_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
4.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
4.411 0.181 tNET RR 1 R8C8[2][A] cnt_0_s0/CLK
4.750 0.340 tC2Q RF 5 R8C8[2][A] cnt_0_s0/Q
5.608 0.858 tNET FF 1 R7C7[0][B] n70_s3/I0
6.072 0.464 tINS FF 7 R7C7[0][B] n70_s3/F
7.042 0.970 tNET FF 1 R9C9[2][B] n26_s4/I0
7.828 0.786 tINS FR 3 R9C9[2][B] n26_s4/F
8.142 0.313 tNET RR 1 R9C8[2][B] n26_s1/I2
8.928 0.786 tINS RR 15 R9C8[2][B] n26_s1/F
9.247 0.319 tNET RR 1 R8C8[1][A] n69_s2/I0
9.856 0.609 tINS RF 1 R8C8[1][A] n69_s2/F
9.856 0.000 tNET FF 1 R8C8[1][A] cnt_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
24.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
24.411 0.181 tNET RR 1 R8C8[1][A] cnt_10_s0/CLK
24.114 -0.296 tSu 1 R8C8[1][A] cnt_10_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay cell: 2.645, 48.579%; route: 2.461, 45.184%; tC2Q: 0.340, 6.237%
Required Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%

Path16

Path Summary:

Slack 14.287
Data Arrival Time 9.827
Data Required Time 24.114
From cnt_0_s0
To cnt_25_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
4.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
4.411 0.181 tNET RR 1 R8C8[2][A] cnt_0_s0/CLK
4.750 0.340 tC2Q RF 5 R8C8[2][A] cnt_0_s0/Q
5.608 0.858 tNET FF 1 R7C7[0][B] n70_s3/I0
6.072 0.464 tINS FF 7 R7C7[0][B] n70_s3/F
6.925 0.853 tNET FF 1 R8C8[3][A] n61_s3/I0
7.388 0.463 tINS FR 7 R8C8[3][A] n61_s3/F
7.704 0.316 tNET RR 1 R9C8[2][A] n54_s3/I1
8.168 0.464 tINS RF 3 R9C8[2][A] n54_s3/F
9.013 0.845 tNET FF 1 R8C9[1][A] n54_s2/I0
9.827 0.814 tINS FF 1 R8C9[1][A] n54_s2/F
9.827 0.000 tNET FF 1 R8C9[1][A] cnt_25_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
24.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
24.411 0.181 tNET RR 1 R8C9[1][A] cnt_25_s0/CLK
24.114 -0.296 tSu 1 R8C9[1][A] cnt_25_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay cell: 2.205, 40.713%; route: 2.872, 53.016%; tC2Q: 0.340, 6.270%
Required Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%

Path17

Path Summary:

Slack 14.407
Data Arrival Time 9.707
Data Required Time 24.114
From cnt_0_s0
To send_en_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
4.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
4.411 0.181 tNET RR 1 R8C8[2][A] cnt_0_s0/CLK
4.750 0.340 tC2Q RF 5 R8C8[2][A] cnt_0_s0/Q
5.608 0.858 tNET FF 1 R7C7[0][B] n70_s3/I0
6.072 0.464 tINS FF 7 R7C7[0][B] n70_s3/F
7.042 0.970 tNET FF 1 R9C9[2][B] n26_s4/I0
7.828 0.786 tINS FR 3 R9C9[2][B] n26_s4/F
8.142 0.313 tNET RR 1 R9C8[2][B] n26_s1/I2
8.928 0.786 tINS RR 15 R9C8[2][B] n26_s1/F
9.707 0.779 tNET RR 1 R9C9[0][A] send_en_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
24.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
24.411 0.181 tNET RR 1 R9C9[0][A] send_en_s0/CLK
24.114 -0.296 tSu 1 R9C9[0][A] send_en_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 4
Arrival Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay cell: 2.036, 38.445%; route: 2.921, 55.143%; tC2Q: 0.340, 6.412%
Required Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%

Path18

Path Summary:

Slack 14.417
Data Arrival Time 9.697
Data Required Time 24.114
From cnt_0_s0
To cnt_21_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
4.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
4.411 0.181 tNET RR 1 R8C8[2][A] cnt_0_s0/CLK
4.750 0.340 tC2Q RF 5 R8C8[2][A] cnt_0_s0/Q
5.608 0.858 tNET FF 1 R7C7[0][B] n70_s3/I0
6.072 0.464 tINS FF 7 R7C7[0][B] n70_s3/F
6.925 0.853 tNET FF 1 R8C8[3][A] n61_s3/I0
7.389 0.464 tINS FF 7 R8C8[3][A] n61_s3/F
8.257 0.868 tNET FF 1 R9C7[3][A] n57_s5/I2
9.071 0.814 tINS FF 4 R9C7[3][A] n57_s5/F
9.088 0.016 tNET FF 1 R9C7[1][B] n58_s3/I0
9.697 0.609 tINS FF 1 R9C7[1][B] n58_s3/F
9.697 0.000 tNET FF 1 R9C7[1][B] cnt_21_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
24.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
24.411 0.181 tNET RR 1 R9C7[1][B] cnt_21_s0/CLK
24.114 -0.296 tSu 1 R9C7[1][B] cnt_21_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay cell: 2.351, 44.478%; route: 2.595, 49.098%; tC2Q: 0.340, 6.425%
Required Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%

Path19

Path Summary:

Slack 14.564
Data Arrival Time 9.550
Data Required Time 24.114
From uart_byte_tx/data_byte_reg_3_s0
To uart_byte_tx/uart_tx_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
4.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
4.411 0.181 tNET RR 1 R7C11[0][B] uart_byte_tx/data_byte_reg_3_s0/CLK
4.750 0.340 tC2Q RR 1 R7C11[0][B] uart_byte_tx/data_byte_reg_3_s0/Q
5.060 0.310 tNET RR 1 R7C11[3][A] uart_byte_tx/n177_s33/I1
5.875 0.814 tINS RF 1 R7C11[3][A] uart_byte_tx/n177_s33/F
5.875 0.000 tNET FF 1 R7C11[3][A] uart_byte_tx/n177_s22/I0
5.985 0.110 tINS FF 1 R7C11[3][A] uart_byte_tx/n177_s22/O
6.355 0.370 tNET FF 1 R7C11[2][A] uart_byte_tx/n177_s35/I0
6.819 0.464 tINS FF 1 R7C11[2][A] uart_byte_tx/n177_s35/F
6.819 0.000 tNET FF 1 R7C11[2][A] uart_byte_tx/n177_s26/I0
6.930 0.110 tINS FF 1 R7C11[2][A] uart_byte_tx/n177_s26/O
7.533 0.603 tNET FF 1 R8C12[1][A] uart_byte_tx/n177_s28/I0
8.347 0.814 tINS FF 1 R8C12[1][A] uart_byte_tx/n177_s28/F
9.550 1.203 tNET FF 1 IOR11[A] uart_byte_tx/uart_tx_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
24.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
24.411 0.181 tNET RR 1 IOR11[A] uart_byte_tx/uart_tx_s0/CLK
24.114 -0.296 tSu 1 IOR11[A] uart_byte_tx/uart_tx_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 4
Arrival Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay cell: 2.313, 45.010%; route: 2.487, 48.382%; tC2Q: 0.340, 6.608%
Required Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%

Path20

Path Summary:

Slack 14.832
Data Arrival Time 9.282
Data Required Time 24.114
From uart_byte_tx/div_cnt_6_s0
To uart_byte_tx/div_cnt_15_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
4.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
4.411 0.181 tNET RR 1 R8C10[2][A] uart_byte_tx/div_cnt_6_s0/CLK
4.750 0.340 tC2Q RF 4 R8C10[2][A] uart_byte_tx/div_cnt_6_s0/Q
5.364 0.614 tNET FF 1 R8C12[1][B] uart_byte_tx/n125_s5/I2
6.178 0.814 tINS FF 5 R8C12[1][B] uart_byte_tx/n125_s5/F
7.137 0.958 tNET FF 1 R8C10[3][A] uart_byte_tx/n112_s3/I0
7.601 0.464 tINS FF 3 R8C10[3][A] uart_byte_tx/n112_s3/F
7.613 0.012 tNET FF 1 R8C10[3][B] uart_byte_tx/n110_s3/I0
8.207 0.594 tINS FR 1 R8C10[3][B] uart_byte_tx/n110_s3/F
8.517 0.310 tNET RR 1 R7C10[1][A] uart_byte_tx/n110_s2/I0
9.282 0.765 tINS RF 1 R7C10[1][A] uart_byte_tx/n110_s2/F
9.282 0.000 tNET FF 1 R7C10[1][A] uart_byte_tx/div_cnt_15_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
24.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
24.411 0.181 tNET RR 1 R7C10[1][A] uart_byte_tx/div_cnt_15_s0/CLK
24.114 -0.296 tSu 1 R7C10[1][A] uart_byte_tx/div_cnt_15_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay cell: 2.637, 54.135%; route: 1.895, 38.893%; tC2Q: 0.340, 6.972%
Required Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%

Path21

Path Summary:

Slack 14.994
Data Arrival Time 9.121
Data Required Time 24.114
From uart_byte_tx/div_cnt_14_s0
To uart_byte_tx/div_cnt_7_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
4.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
4.411 0.181 tNET RR 1 R9C10[2][A] uart_byte_tx/div_cnt_14_s0/CLK
4.750 0.340 tC2Q RF 4 R9C10[2][A] uart_byte_tx/div_cnt_14_s0/Q
5.367 0.616 tNET FF 1 R9C11[3][B] uart_byte_tx/n125_s8/I1
6.181 0.814 tINS FF 1 R9C11[3][B] uart_byte_tx/n125_s8/F
6.185 0.004 tNET FF 1 R9C11[2][A] uart_byte_tx/n125_s7/I2
6.945 0.760 tINS FR 1 R9C11[2][A] uart_byte_tx/n125_s7/F
7.256 0.310 tNET RR 1 R9C10[2][B] uart_byte_tx/n125_s4/I2
7.865 0.609 tINS RF 15 R9C10[2][B] uart_byte_tx/n125_s4/F
8.511 0.647 tNET FF 1 R9C12[0][B] uart_byte_tx/n118_s2/I2
9.121 0.609 tINS FF 1 R9C12[0][B] uart_byte_tx/n118_s2/F
9.121 0.000 tNET FF 1 R9C12[0][B] uart_byte_tx/div_cnt_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
24.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
24.411 0.181 tNET RR 1 R9C12[0][B] uart_byte_tx/div_cnt_7_s0/CLK
24.114 -0.296 tSu 1 R9C12[0][B] uart_byte_tx/div_cnt_7_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay cell: 2.793, 59.297%; route: 1.577, 33.492%; tC2Q: 0.340, 7.211%
Required Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%

Path22

Path Summary:

Slack 15.013
Data Arrival Time 9.101
Data Required Time 24.114
From uart_byte_tx/div_cnt_6_s0
To uart_byte_tx/div_cnt_12_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
4.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
4.411 0.181 tNET RR 1 R8C10[2][A] uart_byte_tx/div_cnt_6_s0/CLK
4.750 0.340 tC2Q RF 4 R8C10[2][A] uart_byte_tx/div_cnt_6_s0/Q
5.364 0.614 tNET FF 1 R8C12[1][B] uart_byte_tx/n125_s5/I2
6.178 0.814 tINS FF 5 R8C12[1][B] uart_byte_tx/n125_s5/F
6.774 0.596 tNET FF 1 R9C11[0][B] uart_byte_tx/n115_s3/I0
7.383 0.609 tINS FF 3 R9C11[0][B] uart_byte_tx/n115_s3/F
7.396 0.012 tNET FF 1 R9C11[2][B] uart_byte_tx/n113_s3/I0
8.182 0.786 tINS FR 1 R9C11[2][B] uart_byte_tx/n113_s3/F
8.492 0.310 tNET RR 1 R9C12[0][A] uart_byte_tx/n113_s2/I0
9.101 0.609 tINS RF 1 R9C12[0][A] uart_byte_tx/n113_s2/F
9.101 0.000 tNET FF 1 R9C12[0][A] uart_byte_tx/div_cnt_12_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
24.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
24.411 0.181 tNET RR 1 R9C12[0][A] uart_byte_tx/div_cnt_12_s0/CLK
24.114 -0.296 tSu 1 R9C12[0][A] uart_byte_tx/div_cnt_12_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay cell: 2.819, 60.093%; route: 1.532, 32.666%; tC2Q: 0.340, 7.240%
Required Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%

Path23

Path Summary:

Slack 15.090
Data Arrival Time 9.024
Data Required Time 24.114
From uart_byte_tx/div_cnt_14_s0
To uart_byte_tx/div_cnt_2_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
4.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
4.411 0.181 tNET RR 1 R9C10[2][A] uart_byte_tx/div_cnt_14_s0/CLK
4.750 0.340 tC2Q RF 4 R9C10[2][A] uart_byte_tx/div_cnt_14_s0/Q
5.367 0.616 tNET FF 1 R9C11[3][B] uart_byte_tx/n125_s8/I1
6.181 0.814 tINS FF 1 R9C11[3][B] uart_byte_tx/n125_s8/F
6.185 0.004 tNET FF 1 R9C11[2][A] uart_byte_tx/n125_s7/I2
6.945 0.760 tINS FR 1 R9C11[2][A] uart_byte_tx/n125_s7/F
7.256 0.310 tNET RR 1 R9C10[2][B] uart_byte_tx/n125_s4/I2
7.865 0.609 tINS RF 15 R9C10[2][B] uart_byte_tx/n125_s4/F
8.259 0.394 tNET FF 1 R9C12[2][A] uart_byte_tx/n123_s4/I3
9.024 0.765 tINS FF 1 R9C12[2][A] uart_byte_tx/n123_s4/F
9.024 0.000 tNET FF 1 R9C12[2][A] uart_byte_tx/div_cnt_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
24.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
24.411 0.181 tNET RR 1 R9C12[2][A] uart_byte_tx/div_cnt_2_s0/CLK
24.114 -0.296 tSu 1 R9C12[2][A] uart_byte_tx/div_cnt_2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay cell: 2.948, 63.914%; route: 1.325, 28.724%; tC2Q: 0.340, 7.362%
Required Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%

Path24

Path Summary:

Slack 15.095
Data Arrival Time 9.019
Data Required Time 24.114
From uart_byte_tx/div_cnt_6_s0
To uart_byte_tx/div_cnt_13_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
4.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
4.411 0.181 tNET RR 1 R8C10[2][A] uart_byte_tx/div_cnt_6_s0/CLK
4.750 0.340 tC2Q RF 4 R8C10[2][A] uart_byte_tx/div_cnt_6_s0/Q
5.364 0.614 tNET FF 1 R8C12[1][B] uart_byte_tx/n125_s5/I2
6.178 0.814 tINS FF 5 R8C12[1][B] uart_byte_tx/n125_s5/F
7.137 0.958 tNET FF 1 R8C10[3][A] uart_byte_tx/n112_s3/I0
7.601 0.464 tINS FF 3 R8C10[3][A] uart_byte_tx/n112_s3/F
8.205 0.604 tNET FF 1 R8C12[2][B] uart_byte_tx/n112_s2/I0
9.019 0.814 tINS FF 1 R8C12[2][B] uart_byte_tx/n112_s2/F
9.019 0.000 tNET FF 1 R8C12[2][B] uart_byte_tx/div_cnt_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
24.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
24.411 0.181 tNET RR 1 R8C12[2][B] uart_byte_tx/div_cnt_13_s0/CLK
24.114 -0.296 tSu 1 R8C12[2][B] uart_byte_tx/div_cnt_13_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 4
Arrival Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay cell: 2.093, 45.408%; route: 2.176, 47.223%; tC2Q: 0.340, 7.370%
Required Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%

Path25

Path Summary:

Slack 15.139
Data Arrival Time 8.975
Data Required Time 24.114
From uart_byte_tx/div_cnt_14_s0
To uart_byte_tx/div_cnt_0_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
4.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
4.411 0.181 tNET RR 1 R9C10[2][A] uart_byte_tx/div_cnt_14_s0/CLK
4.750 0.340 tC2Q RF 4 R9C10[2][A] uart_byte_tx/div_cnt_14_s0/Q
5.367 0.616 tNET FF 1 R9C11[3][B] uart_byte_tx/n125_s8/I1
6.181 0.814 tINS FF 1 R9C11[3][B] uart_byte_tx/n125_s8/F
6.185 0.004 tNET FF 1 R9C11[2][A] uart_byte_tx/n125_s7/I2
6.945 0.760 tINS FR 1 R9C11[2][A] uart_byte_tx/n125_s7/F
7.256 0.310 tNET RR 1 R9C10[2][B] uart_byte_tx/n125_s4/I2
7.865 0.609 tINS RF 15 R9C10[2][B] uart_byte_tx/n125_s4/F
8.511 0.647 tNET FF 1 R9C12[2][B] uart_byte_tx/n125_s3/I1
8.975 0.464 tINS FF 1 R9C12[2][B] uart_byte_tx/n125_s3/F
8.975 0.000 tNET FF 1 R9C12[2][B] uart_byte_tx/div_cnt_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk
20.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
24.230 4.230 tINS RR 67 IOL6[A] clk_ibuf/O
24.411 0.181 tNET RR 1 R9C12[2][B] uart_byte_tx/div_cnt_0_s0/CLK
24.114 -0.296 tSu 1 R9C12[2][B] uart_byte_tx/div_cnt_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay cell: 2.648, 58.002%; route: 1.577, 34.558%; tC2Q: 0.340, 7.440%
Required Clock Path Delay cell: 4.230, 95.902%; route: 0.181, 4.098%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.524
Data Arrival Time 3.788
Data Required Time 3.263
From uart_byte_tx/div_cnt_15_s0
To uart_byte_tx/div_cnt_15_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R7C10[1][A] uart_byte_tx/div_cnt_15_s0/CLK
3.510 0.247 tC2Q RR 3 R7C10[1][A] uart_byte_tx/div_cnt_15_s0/Q
3.512 0.002 tNET RR 1 R7C10[1][A] uart_byte_tx/n110_s2/I1
3.788 0.276 tINS RF 1 R7C10[1][A] uart_byte_tx/n110_s2/F
3.788 0.000 tNET FF 1 R7C10[1][A] uart_byte_tx/div_cnt_15_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R7C10[1][A] uart_byte_tx/div_cnt_15_s0/CLK
3.263 0.000 tHld 1 R7C10[1][A] uart_byte_tx/div_cnt_15_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%

Path2

Path Summary:

Slack 0.524
Data Arrival Time 3.788
Data Required Time 3.263
From cnt_25_s0
To cnt_25_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R8C9[1][A] cnt_25_s0/CLK
3.510 0.247 tC2Q RR 2 R8C9[1][A] cnt_25_s0/Q
3.512 0.002 tNET RR 1 R8C9[1][A] n54_s2/I3
3.788 0.276 tINS RF 1 R8C9[1][A] n54_s2/F
3.788 0.000 tNET FF 1 R8C9[1][A] cnt_25_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R8C9[1][A] cnt_25_s0/CLK
3.263 0.000 tHld 1 R8C9[1][A] cnt_25_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%

Path3

Path Summary:

Slack 0.524
Data Arrival Time 3.788
Data Required Time 3.263
From data_byte_0_s0
To data_byte_0_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R7C7[0][A] data_byte_0_s0/CLK
3.510 0.247 tC2Q RR 3 R7C7[0][A] data_byte_0_s0/Q
3.512 0.002 tNET RR 1 R7C7[0][A] n142_s2/I0
3.788 0.276 tINS RF 1 R7C7[0][A] n142_s2/F
3.788 0.000 tNET FF 1 R7C7[0][A] data_byte_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R7C7[0][A] data_byte_0_s0/CLK
3.263 0.000 tHld 1 R7C7[0][A] data_byte_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%

Path4

Path Summary:

Slack 0.524
Data Arrival Time 3.788
Data Required Time 3.263
From cnt_1_s0
To cnt_1_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R7C8[0][A] cnt_1_s0/CLK
3.510 0.247 tC2Q RR 4 R7C8[0][A] cnt_1_s0/Q
3.512 0.002 tNET RR 1 R7C8[0][A] n78_s2/I1
3.788 0.276 tINS RF 1 R7C8[0][A] n78_s2/F
3.788 0.000 tNET FF 1 R7C8[0][A] cnt_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R7C8[0][A] cnt_1_s0/CLK
3.263 0.000 tHld 1 R7C8[0][A] cnt_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%

Path5

Path Summary:

Slack 0.524
Data Arrival Time 3.788
Data Required Time 3.263
From cnt_2_s0
To cnt_2_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R8C7[0][A] cnt_2_s0/CLK
3.510 0.247 tC2Q RR 3 R8C7[0][A] cnt_2_s0/Q
3.512 0.002 tNET RR 1 R8C7[0][A] n77_s2/I2
3.788 0.276 tINS RF 1 R8C7[0][A] n77_s2/F
3.788 0.000 tNET FF 1 R8C7[0][A] cnt_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R8C7[0][A] cnt_2_s0/CLK
3.263 0.000 tHld 1 R8C7[0][A] cnt_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%

Path6

Path Summary:

Slack 0.524
Data Arrival Time 3.788
Data Required Time 3.263
From cnt_3_s0
To cnt_3_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R7C7[1][A] cnt_3_s0/CLK
3.510 0.247 tC2Q RR 2 R7C7[1][A] cnt_3_s0/Q
3.512 0.002 tNET RR 1 R7C7[1][A] n76_s2/I3
3.788 0.276 tINS RF 1 R7C7[1][A] n76_s2/F
3.788 0.000 tNET FF 1 R7C7[1][A] cnt_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R7C7[1][A] cnt_3_s0/CLK
3.263 0.000 tHld 1 R7C7[1][A] cnt_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%

Path7

Path Summary:

Slack 0.524
Data Arrival Time 3.788
Data Required Time 3.263
From cnt_5_s0
To cnt_5_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R9C9[1][A] cnt_5_s0/CLK
3.510 0.247 tC2Q RR 3 R9C9[1][A] cnt_5_s0/Q
3.512 0.002 tNET RR 1 R9C9[1][A] n74_s2/I2
3.788 0.276 tINS RF 1 R9C9[1][A] n74_s2/F
3.788 0.000 tNET FF 1 R9C9[1][A] cnt_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R9C9[1][A] cnt_5_s0/CLK
3.263 0.000 tHld 1 R9C9[1][A] cnt_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%

Path8

Path Summary:

Slack 0.524
Data Arrival Time 3.788
Data Required Time 3.263
From cnt_16_s0
To cnt_16_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R8C9[0][A] cnt_16_s0/CLK
3.510 0.247 tC2Q RR 3 R8C9[0][A] cnt_16_s0/Q
3.512 0.002 tNET RR 1 R8C9[0][A] n63_s2/I2
3.788 0.276 tINS RF 1 R8C9[0][A] n63_s2/F
3.788 0.000 tNET FF 1 R8C9[0][A] cnt_16_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R8C9[0][A] cnt_16_s0/CLK
3.263 0.000 tHld 1 R8C9[0][A] cnt_16_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%

Path9

Path Summary:

Slack 0.524
Data Arrival Time 3.788
Data Required Time 3.263
From cnt_22_s0
To cnt_22_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R9C8[0][A] cnt_22_s0/CLK
3.510 0.247 tC2Q RR 3 R9C8[0][A] cnt_22_s0/Q
3.512 0.002 tNET RR 1 R9C8[0][A] n57_s2/I3
3.788 0.276 tINS RF 1 R9C8[0][A] n57_s2/F
3.788 0.000 tNET FF 1 R9C8[0][A] cnt_22_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R9C8[0][A] cnt_22_s0/CLK
3.263 0.000 tHld 1 R9C8[0][A] cnt_22_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%

Path10

Path Summary:

Slack 0.525
Data Arrival Time 3.788
Data Required Time 3.263
From uart_byte_tx/bps_cnt_3_s1
To uart_byte_tx/bps_cnt_3_s1
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R8C12[0][A] uart_byte_tx/bps_cnt_3_s1/CLK
3.510 0.247 tC2Q RR 4 R8C12[0][A] uart_byte_tx/bps_cnt_3_s1/Q
3.513 0.003 tNET RR 1 R8C12[0][A] uart_byte_tx/n157_s3/I1
3.788 0.276 tINS RF 1 R8C12[0][A] uart_byte_tx/n157_s3/F
3.788 0.000 tNET FF 1 R8C12[0][A] uart_byte_tx/bps_cnt_3_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R8C12[0][A] uart_byte_tx/bps_cnt_3_s1/CLK
3.263 0.000 tHld 1 R8C12[0][A] uart_byte_tx/bps_cnt_3_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%

Path11

Path Summary:

Slack 0.525
Data Arrival Time 3.788
Data Required Time 3.263
From uart_byte_tx/div_cnt_4_s0
To uart_byte_tx/div_cnt_4_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R8C10[0][A] uart_byte_tx/div_cnt_4_s0/CLK
3.510 0.247 tC2Q RR 6 R8C10[0][A] uart_byte_tx/div_cnt_4_s0/Q
3.513 0.003 tNET RR 1 R8C10[0][A] uart_byte_tx/n121_s2/I1
3.788 0.276 tINS RF 1 R8C10[0][A] uart_byte_tx/n121_s2/F
3.788 0.000 tNET FF 1 R8C10[0][A] uart_byte_tx/div_cnt_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R8C10[0][A] uart_byte_tx/div_cnt_4_s0/CLK
3.263 0.000 tHld 1 R8C10[0][A] uart_byte_tx/div_cnt_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%

Path12

Path Summary:

Slack 0.525
Data Arrival Time 3.788
Data Required Time 3.263
From uart_byte_tx/div_cnt_9_s0
To uart_byte_tx/div_cnt_9_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R9C10[1][A] uart_byte_tx/div_cnt_9_s0/CLK
3.510 0.247 tC2Q RR 5 R9C10[1][A] uart_byte_tx/div_cnt_9_s0/Q
3.513 0.003 tNET RR 1 R9C10[1][A] uart_byte_tx/n116_s2/I2
3.788 0.276 tINS RF 1 R9C10[1][A] uart_byte_tx/n116_s2/F
3.788 0.000 tNET FF 1 R9C10[1][A] uart_byte_tx/div_cnt_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R9C10[1][A] uart_byte_tx/div_cnt_9_s0/CLK
3.263 0.000 tHld 1 R9C10[1][A] uart_byte_tx/div_cnt_9_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%

Path13

Path Summary:

Slack 0.525
Data Arrival Time 3.788
Data Required Time 3.263
From cnt_8_s0
To cnt_8_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R9C7[1][A] cnt_8_s0/CLK
3.510 0.247 tC2Q RR 5 R9C7[1][A] cnt_8_s0/Q
3.513 0.003 tNET RR 1 R9C7[1][A] n71_s2/I2
3.788 0.276 tINS RF 1 R9C7[1][A] n71_s2/F
3.788 0.000 tNET FF 1 R9C7[1][A] cnt_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R9C7[1][A] cnt_8_s0/CLK
3.263 0.000 tHld 1 R9C7[1][A] cnt_8_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%

Path14

Path Summary:

Slack 0.525
Data Arrival Time 3.788
Data Required Time 3.263
From cnt_15_s0
To cnt_15_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R7C8[1][A] cnt_15_s0/CLK
3.510 0.247 tC2Q RR 3 R7C8[1][A] cnt_15_s0/Q
3.513 0.003 tNET RR 1 R7C8[1][A] n64_s2/I2
3.788 0.276 tINS RF 1 R7C8[1][A] n64_s2/F
3.788 0.000 tNET FF 1 R7C8[1][A] cnt_15_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R7C8[1][A] cnt_15_s0/CLK
3.263 0.000 tHld 1 R7C8[1][A] cnt_15_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%

Path15

Path Summary:

Slack 0.526
Data Arrival Time 3.789
Data Required Time 3.263
From uart_byte_tx/bps_cnt_2_s1
To uart_byte_tx/bps_cnt_2_s1
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R7C12[1][A] uart_byte_tx/bps_cnt_2_s1/CLK
3.510 0.247 tC2Q RR 6 R7C12[1][A] uart_byte_tx/bps_cnt_2_s1/Q
3.514 0.003 tNET RR 1 R7C12[1][A] uart_byte_tx/n158_s3/I1
3.789 0.276 tINS RF 1 R7C12[1][A] uart_byte_tx/n158_s3/F
3.789 0.000 tNET FF 1 R7C12[1][A] uart_byte_tx/bps_cnt_2_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R7C12[1][A] uart_byte_tx/bps_cnt_2_s1/CLK
3.263 0.000 tHld 1 R7C12[1][A] uart_byte_tx/bps_cnt_2_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%

Path16

Path Summary:

Slack 0.526
Data Arrival Time 3.789
Data Required Time 3.263
From uart_byte_tx/div_cnt_11_s0
To uart_byte_tx/div_cnt_11_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R9C11[0][A] uart_byte_tx/div_cnt_11_s0/CLK
3.510 0.247 tC2Q RR 5 R9C11[0][A] uart_byte_tx/div_cnt_11_s0/Q
3.514 0.003 tNET RR 1 R9C11[0][A] uart_byte_tx/n114_s2/I2
3.789 0.276 tINS RF 1 R9C11[0][A] uart_byte_tx/n114_s2/F
3.789 0.000 tNET FF 1 R9C11[0][A] uart_byte_tx/div_cnt_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R9C11[0][A] uart_byte_tx/div_cnt_11_s0/CLK
3.263 0.000 tHld 1 R9C11[0][A] uart_byte_tx/div_cnt_11_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%

Path17

Path Summary:

Slack 0.526
Data Arrival Time 3.789
Data Required Time 3.263
From cnt_13_s0
To cnt_13_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R9C7[0][A] cnt_13_s0/CLK
3.510 0.247 tC2Q RR 7 R9C7[0][A] cnt_13_s0/Q
3.514 0.003 tNET RR 1 R9C7[0][A] n66_s2/I2
3.789 0.276 tINS RF 1 R9C7[0][A] n66_s2/F
3.789 0.000 tNET FF 1 R9C7[0][A] cnt_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R9C7[0][A] cnt_13_s0/CLK
3.263 0.000 tHld 1 R9C7[0][A] cnt_13_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%

Path18

Path Summary:

Slack 0.527
Data Arrival Time 3.790
Data Required Time 3.263
From uart_byte_tx/div_cnt_10_s0
To uart_byte_tx/div_cnt_10_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R9C11[1][A] uart_byte_tx/div_cnt_10_s0/CLK
3.510 0.247 tC2Q RR 6 R9C11[1][A] uart_byte_tx/div_cnt_10_s0/Q
3.515 0.004 tNET RR 1 R9C11[1][A] uart_byte_tx/n115_s2/I1
3.790 0.276 tINS RF 1 R9C11[1][A] uart_byte_tx/n115_s2/F
3.790 0.000 tNET FF 1 R9C11[1][A] uart_byte_tx/div_cnt_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R9C11[1][A] uart_byte_tx/div_cnt_10_s0/CLK
3.263 0.000 tHld 1 R9C11[1][A] uart_byte_tx/div_cnt_10_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay cell: 0.276, 52.303%; route: 0.004, 0.830%; tC2Q: 0.247, 46.867%
Required Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%

Path19

Path Summary:

Slack 0.541
Data Arrival Time 3.804
Data Required Time 3.263
From data_byte_2_s0
To data_byte_2_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R7C9[1][A] data_byte_2_s0/CLK
3.510 0.247 tC2Q RR 2 R7C9[1][A] data_byte_2_s0/Q
3.512 0.002 tNET RR 2 R7C9[1][A] n140_s/I1
3.804 0.292 tINS RF 1 R7C9[1][A] n140_s/SUM
3.804 0.000 tNET FF 1 R7C9[1][A] data_byte_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R7C9[1][A] data_byte_2_s0/CLK
3.263 0.000 tHld 1 R7C9[1][A] data_byte_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay cell: 0.292, 53.995%; route: 0.002, 0.324%; tC2Q: 0.247, 45.681%
Required Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%

Path20

Path Summary:

Slack 0.541
Data Arrival Time 3.804
Data Required Time 3.263
From data_byte_6_s0
To data_byte_6_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R7C10[0][A] data_byte_6_s0/CLK
3.510 0.247 tC2Q RR 2 R7C10[0][A] data_byte_6_s0/Q
3.512 0.002 tNET RR 2 R7C10[0][A] n136_s/I1
3.804 0.292 tINS RF 1 R7C10[0][A] n136_s/SUM
3.804 0.000 tNET FF 1 R7C10[0][A] data_byte_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R7C10[0][A] data_byte_6_s0/CLK
3.263 0.000 tHld 1 R7C10[0][A] data_byte_6_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay cell: 0.292, 53.995%; route: 0.002, 0.324%; tC2Q: 0.247, 45.681%
Required Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%

Path21

Path Summary:

Slack 0.632
Data Arrival Time 3.895
Data Required Time 3.263
From data_byte_1_s0
To data_byte_1_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R7C9[0][B] data_byte_1_s0/CLK
3.510 0.247 tC2Q RR 2 R7C9[0][B] data_byte_1_s0/Q
3.512 0.002 tNET RR 2 R7C9[0][B] n141_s/I0
3.895 0.383 tINS RF 1 R7C9[0][B] n141_s/SUM
3.895 0.000 tNET FF 1 R7C9[0][B] data_byte_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R7C9[0][B] data_byte_1_s0/CLK
3.263 0.000 tHld 1 R7C9[0][B] data_byte_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay cell: 0.383, 60.631%; route: 0.002, 0.277%; tC2Q: 0.247, 39.092%
Required Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%

Path22

Path Summary:

Slack 0.661
Data Arrival Time 3.934
Data Required Time 3.272
From send_en_s0
To uart_byte_tx/data_byte_reg_2_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R9C9[0][A] send_en_s0/CLK
3.510 0.247 tC2Q RR 10 R9C9[0][A] send_en_s0/Q
3.934 0.424 tNET RR 1 R8C11[1][B] uart_byte_tx/data_byte_reg_2_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R8C11[1][B] uart_byte_tx/data_byte_reg_2_s0/CLK
3.272 0.009 tHld 1 R8C11[1][B] uart_byte_tx/data_byte_reg_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.424, 63.164%; tC2Q: 0.247, 36.836%
Required Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%

Path23

Path Summary:

Slack 0.661
Data Arrival Time 3.934
Data Required Time 3.272
From send_en_s0
To uart_byte_tx/data_byte_reg_4_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R9C9[0][A] send_en_s0/CLK
3.510 0.247 tC2Q RR 10 R9C9[0][A] send_en_s0/Q
3.934 0.424 tNET RR 1 R8C11[1][A] uart_byte_tx/data_byte_reg_4_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R8C11[1][A] uart_byte_tx/data_byte_reg_4_s0/CLK
3.272 0.009 tHld 1 R8C11[1][A] uart_byte_tx/data_byte_reg_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.424, 63.164%; tC2Q: 0.247, 36.836%
Required Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%

Path24

Path Summary:

Slack 0.662
Data Arrival Time 3.925
Data Required Time 3.263
From uart_byte_tx/div_cnt_2_s0
To uart_byte_tx/div_cnt_2_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R9C12[2][A] uart_byte_tx/div_cnt_2_s0/CLK
3.510 0.247 tC2Q RR 5 R9C12[2][A] uart_byte_tx/div_cnt_2_s0/Q
3.513 0.003 tNET RR 1 R9C12[2][A] uart_byte_tx/n123_s4/I2
3.925 0.412 tINS RR 1 R9C12[2][A] uart_byte_tx/n123_s4/F
3.925 0.000 tNET RR 1 R9C12[2][A] uart_byte_tx/div_cnt_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R9C12[2][A] uart_byte_tx/div_cnt_2_s0/CLK
3.263 0.000 tHld 1 R9C12[2][A] uart_byte_tx/div_cnt_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay cell: 0.412, 62.271%; route: 0.003, 0.397%; tC2Q: 0.247, 37.333%
Required Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%

Path25

Path Summary:

Slack 0.662
Data Arrival Time 3.925
Data Required Time 3.263
From cnt_0_s0
To cnt_0_s0
Launch Clk clk:[R]
Latch Clk clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R8C8[2][A] cnt_0_s0/CLK
3.510 0.247 tC2Q RR 5 R8C8[2][A] cnt_0_s0/Q
3.513 0.003 tNET RR 1 R8C8[2][A] n79_s4/I0
3.925 0.412 tINS RR 1 R8C8[2][A] n79_s4/F
3.925 0.000 tNET RR 1 R8C8[2][A] cnt_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
3.126 3.126 tINS RR 67 IOL6[A] clk_ibuf/O
3.263 0.137 tNET RR 1 R8C8[2][A] cnt_0_s0/CLK
3.263 0.000 tHld 1 R8C8[2][A] cnt_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay cell: 0.412, 62.271%; route: 0.003, 0.397%; tC2Q: 0.247, 37.333%
Required Clock Path Delay cell: 3.126, 95.808%; route: 0.137, 4.192%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 6.948
Actual Width: 7.874
Required Width: 0.926
Type: High Pulse Width
Clock: clk
Objects: cnt_24_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR clk_ibuf/I
4.230 4.230 tINS RR clk_ibuf/O
4.411 0.181 tNET RR cnt_24_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF clk_ibuf/I
12.140 2.140 tINS FF clk_ibuf/O
12.285 0.145 tNET FF cnt_24_s0/CLK

MPW2

MPW Summary:

Slack: 6.948
Actual Width: 7.874
Required Width: 0.926
Type: High Pulse Width
Clock: clk
Objects: cnt_23_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR clk_ibuf/I
4.230 4.230 tINS RR clk_ibuf/O
4.411 0.181 tNET RR cnt_23_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF clk_ibuf/I
12.140 2.140 tINS FF clk_ibuf/O
12.285 0.145 tNET FF cnt_23_s0/CLK

MPW3

MPW Summary:

Slack: 6.948
Actual Width: 7.874
Required Width: 0.926
Type: High Pulse Width
Clock: clk
Objects: cnt_21_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR clk_ibuf/I
4.230 4.230 tINS RR clk_ibuf/O
4.411 0.181 tNET RR cnt_21_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF clk_ibuf/I
12.140 2.140 tINS FF clk_ibuf/O
12.285 0.145 tNET FF cnt_21_s0/CLK

MPW4

MPW Summary:

Slack: 6.948
Actual Width: 7.874
Required Width: 0.926
Type: High Pulse Width
Clock: clk
Objects: cnt_17_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR clk_ibuf/I
4.230 4.230 tINS RR clk_ibuf/O
4.411 0.181 tNET RR cnt_17_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF clk_ibuf/I
12.140 2.140 tINS FF clk_ibuf/O
12.285 0.145 tNET FF cnt_17_s0/CLK

MPW5

MPW Summary:

Slack: 6.948
Actual Width: 7.874
Required Width: 0.926
Type: High Pulse Width
Clock: clk
Objects: cnt_9_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR clk_ibuf/I
4.230 4.230 tINS RR clk_ibuf/O
4.411 0.181 tNET RR cnt_9_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF clk_ibuf/I
12.140 2.140 tINS FF clk_ibuf/O
12.285 0.145 tNET FF cnt_9_s0/CLK

MPW6

MPW Summary:

Slack: 6.948
Actual Width: 7.874
Required Width: 0.926
Type: High Pulse Width
Clock: clk
Objects: data_byte_2_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR clk_ibuf/I
4.230 4.230 tINS RR clk_ibuf/O
4.411 0.181 tNET RR data_byte_2_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF clk_ibuf/I
12.140 2.140 tINS FF clk_ibuf/O
12.285 0.145 tNET FF data_byte_2_s0/CLK

MPW7

MPW Summary:

Slack: 6.948
Actual Width: 7.874
Required Width: 0.926
Type: High Pulse Width
Clock: clk
Objects: uart_byte_tx/bps_cnt_2_s1

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR clk_ibuf/I
4.230 4.230 tINS RR clk_ibuf/O
4.411 0.181 tNET RR uart_byte_tx/bps_cnt_2_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF clk_ibuf/I
12.140 2.140 tINS FF clk_ibuf/O
12.285 0.145 tNET FF uart_byte_tx/bps_cnt_2_s1/CLK

MPW8

MPW Summary:

Slack: 6.948
Actual Width: 7.874
Required Width: 0.926
Type: High Pulse Width
Clock: clk
Objects: uart_byte_tx/bps_cnt_3_s1

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR clk_ibuf/I
4.230 4.230 tINS RR clk_ibuf/O
4.411 0.181 tNET RR uart_byte_tx/bps_cnt_3_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF clk_ibuf/I
12.140 2.140 tINS FF clk_ibuf/O
12.285 0.145 tNET FF uart_byte_tx/bps_cnt_3_s1/CLK

MPW9

MPW Summary:

Slack: 6.948
Actual Width: 7.874
Required Width: 0.926
Type: High Pulse Width
Clock: clk
Objects: data_byte_3_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR clk_ibuf/I
4.230 4.230 tINS RR clk_ibuf/O
4.411 0.181 tNET RR data_byte_3_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF clk_ibuf/I
12.140 2.140 tINS FF clk_ibuf/O
12.285 0.145 tNET FF data_byte_3_s0/CLK

MPW10

MPW Summary:

Slack: 6.948
Actual Width: 7.874
Required Width: 0.926
Type: High Pulse Width
Clock: clk
Objects: uart_byte_tx/uart_tx_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk
0.000 0.000 tCL RR clk_ibuf/I
4.230 4.230 tINS RR clk_ibuf/O
4.411 0.181 tNET RR uart_byte_tx/uart_tx_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk
10.000 0.000 tCL FF clk_ibuf/I
12.140 2.140 tINS FF clk_ibuf/O
12.285 0.145 tNET FF uart_byte_tx/uart_tx_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
67 clk_d 13.352 0.195
15 n26_5 13.352 0.991
15 uart_byte_tx/n125_9 14.994 0.647
10 send_en 18.173 1.323
10 uart_byte_tx/bps_cnt[0] 14.759 0.321
8 tx_done_Z 18.218 1.682
8 uart_byte_tx/n121_8 15.174 0.620
7 n70_8 13.352 1.215
7 uart_byte_tx/bps_cnt[1] 14.859 0.616
7 cnt[13] 15.947 0.979

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R2C2 100.00%
R2C3 100.00%
R2C10 100.00%
R2C11 100.00%
R3C9 100.00%
R5C5 100.00%
R8C15 100.00%
R16C13 100.00%
R18C19 100.00%
R18C18 100.00%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command