Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Users\phutruong\Documents\GitHub\example_code\PWM_LED\src\led_pwm.v
C:\Users\phutruong\Documents\GitHub\example_code\PWM_LED\src\pwm_gen.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.01 (64-bit)
Part Number GW1N-UV1P5QN48XFC7/I6
Device GW1N-1P5
Device Version C
Created Time Wed Nov 19 11:01:58 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module pwm_gen_test
Synthesis Process Running parser:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.092s, Peak memory usage = 134.645MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 134.645MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 134.645MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 134.645MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 134.645MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 134.645MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 134.645MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 134.645MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 134.645MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 134.645MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 134.645MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.373s, Peak memory usage = 163.223MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.05s, Peak memory usage = 163.223MB
Generate output files:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.038s, Peak memory usage = 163.223MB
Total Time and Memory Usage CPU time = 0h 0m 0.45s, Elapsed time = 0h 0m 0.574s, Peak memory usage = 163.223MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 3
I/O Buf 3
    IBUF 2
    OBUF 1
Register 72
    DFFP 5
    DFFPE 1
    DFFC 64
    DFFCE 2
LUT 122
    LUT2 16
    LUT3 37
    LUT4 69
ALU 12
    ALU 12
INV 3
    INV 3

Resource Utilization Summary

Resource Usage Utilization
Logic 137(125 LUT, 12 ALU) / 1584 9%
Register 72 / 1704 5%
  --Register as Latch 0 / 1704 0%
  --Register as FF 72 / 1704 5%
BSRAM 0 / 4 0%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk Base 20.000 50.000 0.000 10.000 clk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 50.000(MHz) 134.223(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 12.550
Data Arrival Time 7.692
Data Required Time 20.242
From pwm_gen_inst/pwm_gen_cnt_22_s0
To pwm_gen_inst/pwm_gen_cnt_0_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 72 clk_ibuf/O
0.538 0.538 tNET RR 1 pwm_gen_inst/pwm_gen_cnt_22_s0/CLK
0.878 0.340 tC2Q RF 3 pwm_gen_inst/pwm_gen_cnt_22_s0/Q
1.589 0.711 tNET FF 1 pwm_gen_inst/n138_s119/I1
2.403 0.814 tINS FF 3 pwm_gen_inst/n138_s119/F
3.115 0.711 tNET FF 1 pwm_gen_inst/n103_s5/I1
3.929 0.814 tINS FF 3 pwm_gen_inst/n103_s5/F
4.640 0.711 tNET FF 1 pwm_gen_inst/n103_s4/I1
5.455 0.814 tINS FF 31 pwm_gen_inst/n103_s4/F
6.166 0.711 tNET FF 1 pwm_gen_inst/n103_s3/I1
6.980 0.814 tINS FF 1 pwm_gen_inst/n103_s3/F
7.692 0.711 tNET FF 1 pwm_gen_inst/pwm_gen_cnt_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 72 clk_ibuf/O
20.538 0.538 tNET RR 1 pwm_gen_inst/pwm_gen_cnt_0_s0/CLK
20.242 -0.296 tSu 1 pwm_gen_inst/pwm_gen_cnt_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.257, 45.534%; route: 3.557, 49.719%; tC2Q: 0.340, 4.747%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 2

Path Summary:
Slack 12.550
Data Arrival Time 7.692
Data Required Time 20.242
From pwm_gen_inst/pwm_gen_cnt_10_s0
To pwm_gen_inst/pwm_gen_cnt_23_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 72 clk_ibuf/O
0.538 0.538 tNET RR 1 pwm_gen_inst/pwm_gen_cnt_10_s0/CLK
0.878 0.340 tC2Q RF 4 pwm_gen_inst/pwm_gen_cnt_10_s0/Q
1.589 0.711 tNET FF 1 pwm_gen_inst/n91_s3/I1
2.403 0.814 tINS FF 3 pwm_gen_inst/n91_s3/F
3.115 0.711 tNET FF 1 pwm_gen_inst/n86_s4/I1
3.929 0.814 tINS FF 11 pwm_gen_inst/n86_s4/F
4.640 0.711 tNET FF 1 pwm_gen_inst/n81_s4/I1
5.455 0.814 tINS FF 2 pwm_gen_inst/n81_s4/F
6.166 0.711 tNET FF 1 pwm_gen_inst/n80_s2/I1
6.980 0.814 tINS FF 1 pwm_gen_inst/n80_s2/F
7.692 0.711 tNET FF 1 pwm_gen_inst/pwm_gen_cnt_23_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 72 clk_ibuf/O
20.538 0.538 tNET RR 1 pwm_gen_inst/pwm_gen_cnt_23_s0/CLK
20.242 -0.296 tSu 1 pwm_gen_inst/pwm_gen_cnt_23_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.257, 45.534%; route: 3.557, 49.719%; tC2Q: 0.340, 4.747%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 3

Path Summary:
Slack 12.550
Data Arrival Time 7.692
Data Required Time 20.242
From pwm_gen_inst/pwm_gen_cnt_22_s0
To pwm_gen_inst/pwm_gen_cnt_30_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 72 clk_ibuf/O
0.538 0.538 tNET RR 1 pwm_gen_inst/pwm_gen_cnt_22_s0/CLK
0.878 0.340 tC2Q RF 3 pwm_gen_inst/pwm_gen_cnt_22_s0/Q
1.589 0.711 tNET FF 1 pwm_gen_inst/n138_s119/I1
2.403 0.814 tINS FF 3 pwm_gen_inst/n138_s119/F
3.115 0.711 tNET FF 1 pwm_gen_inst/n103_s5/I1
3.929 0.814 tINS FF 3 pwm_gen_inst/n103_s5/F
4.640 0.711 tNET FF 1 pwm_gen_inst/n74_s3/I1
5.455 0.814 tINS FF 3 pwm_gen_inst/n74_s3/F
6.166 0.711 tNET FF 1 pwm_gen_inst/n73_s2/I1
6.980 0.814 tINS FF 1 pwm_gen_inst/n73_s2/F
7.692 0.711 tNET FF 1 pwm_gen_inst/pwm_gen_cnt_30_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 72 clk_ibuf/O
20.538 0.538 tNET RR 1 pwm_gen_inst/pwm_gen_cnt_30_s0/CLK
20.242 -0.296 tSu 1 pwm_gen_inst/pwm_gen_cnt_30_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.257, 45.534%; route: 3.557, 49.719%; tC2Q: 0.340, 4.747%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 4

Path Summary:
Slack 12.599
Data Arrival Time 7.642
Data Required Time 20.242
From t500ms_dly_cnt_10_s0
To t500ms_dly_cnt_19_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 72 clk_ibuf/O
0.538 0.538 tNET RR 1 t500ms_dly_cnt_10_s0/CLK
0.878 0.340 tC2Q RF 4 t500ms_dly_cnt_10_s0/Q
1.589 0.711 tNET FF 1 n25_s6/I1
2.403 0.814 tINS FF 2 n25_s6/F
3.115 0.711 tNET FF 1 n53_s3/I1
3.929 0.814 tINS FF 7 n53_s3/F
4.640 0.711 tNET FF 1 n52_s7/I0
5.405 0.765 tINS FF 6 n52_s7/F
6.116 0.711 tNET FF 1 n57_s2/I1
6.931 0.814 tINS FF 1 n57_s2/F
7.642 0.711 tNET FF 1 t500ms_dly_cnt_19_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 72 clk_ibuf/O
20.538 0.538 tNET RR 1 t500ms_dly_cnt_19_s0/CLK
20.242 -0.296 tSu 1 t500ms_dly_cnt_19_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.208, 45.153%; route: 3.557, 50.066%; tC2Q: 0.340, 4.781%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 5

Path Summary:
Slack 12.599
Data Arrival Time 7.642
Data Required Time 20.242
From pwm_gen_inst/pwm_gen_cnt_22_s0
To pwm_gen_inst/pwm_gen_cnt_29_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 72 clk_ibuf/O
0.538 0.538 tNET RR 1 pwm_gen_inst/pwm_gen_cnt_22_s0/CLK
0.878 0.340 tC2Q RF 3 pwm_gen_inst/pwm_gen_cnt_22_s0/Q
1.589 0.711 tNET FF 1 pwm_gen_inst/n138_s119/I1
2.403 0.814 tINS FF 3 pwm_gen_inst/n138_s119/F
3.115 0.711 tNET FF 1 pwm_gen_inst/n103_s5/I1
3.929 0.814 tINS FF 3 pwm_gen_inst/n103_s5/F
4.640 0.711 tNET FF 1 pwm_gen_inst/n103_s4/I1
5.455 0.814 tINS FF 31 pwm_gen_inst/n103_s4/F
6.166 0.711 tNET FF 1 pwm_gen_inst/n74_s2/I0
6.931 0.765 tINS FF 1 pwm_gen_inst/n74_s2/F
7.642 0.711 tNET FF 1 pwm_gen_inst/pwm_gen_cnt_29_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 72 clk_ibuf/O
20.538 0.538 tNET RR 1 pwm_gen_inst/pwm_gen_cnt_29_s0/CLK
20.242 -0.296 tSu 1 pwm_gen_inst/pwm_gen_cnt_29_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.208, 45.153%; route: 3.557, 50.066%; tC2Q: 0.340, 4.781%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%