Timing Messages

Report Title	Timing Analysis Report
Design File	/home/quang1806/Desktop/USING FOR 1P5/example_code/LED_BLINK/impl/gwsynthesis/led_flash.vg
Physical Constraints File	/home/quang1806/Desktop/USING FOR 1P5/example_code/LED_BLINK/src/led_flash.cst
Timing Constraint File	---
Tool Version	V1.9.11
Part Number	GW1N-UV1P5QN48XFC7/I6
Device	GW1N-1P5
Device Version	C
Created Time	Wed Jul 16 10:58:31 2025
Legal Announcement	Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 1.71V 85C C7/I6
Hold Delay Model	Fast 3.6V 0C C7/I6
Numbers of Paths Analyzed	58
Numbers of Endpoints Analyzed	58
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	clk	Base	20.000	50.000	0.000	10.000			clk_ibuf/I

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk	50.000(MHz)	162.281(MHz)	5	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk	Setup	0.000	0
clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	13.838	cnt_13_s0/Q	cnt_9_s0/D	clk:[R]	clk:[R]	20.000	0.000	5.866
2	14.002	cnt_13_s0/Q	cnt_14_s0/D	clk:[R]	clk:[R]	20.000	0.000	5.702
3	14.002	cnt_13_s0/Q	cnt_13_s0/D	clk:[R]	clk:[R]	20.000	0.000	5.702
4	14.303	cnt_13_s0/Q	cnt_16_s0/D	clk:[R]	clk:[R]	20.000	0.000	5.401
5	14.303	cnt_13_s0/Q	cnt_15_s0/D	clk:[R]	clk:[R]	20.000	0.000	5.401
6	14.325	cnt_13_s0/Q	cnt_0_s0/D	clk:[R]	clk:[R]	20.000	0.000	5.379
7	14.325	cnt_13_s0/Q	cnt_7_s0/D	clk:[R]	clk:[R]	20.000	0.000	5.379
8	14.333	cnt_13_s0/Q	cnt_8_s0/D	clk:[R]	clk:[R]	20.000	0.000	5.371
9	14.365	cnt_13_s0/Q	cnt_1_s0/D	clk:[R]	clk:[R]	20.000	0.000	5.339
10	14.365	cnt_13_s0/Q	cnt_2_s0/D	clk:[R]	clk:[R]	20.000	0.000	5.339
11	14.371	cnt_13_s0/Q	cnt_6_s0/D	clk:[R]	clk:[R]	20.000	0.000	5.332
12	14.371	cnt_13_s0/Q	cnt_23_s0/D	clk:[R]	clk:[R]	20.000	0.000	5.332
13	14.371	cnt_13_s0/Q	cnt_24_s0/D	clk:[R]	clk:[R]	20.000	0.000	5.332
14	14.375	cnt_13_s0/Q	cnt_17_s0/D	clk:[R]	clk:[R]	20.000	0.000	5.329
15	14.375	cnt_13_s0/Q	cnt_5_s0/D	clk:[R]	clk:[R]	20.000	0.000	5.329
16	14.420	cnt_13_s0/Q	cnt_3_s0/D	clk:[R]	clk:[R]	20.000	0.000	5.283
17	14.614	cnt_13_s0/Q	cnt_19_s0/D	clk:[R]	clk:[R]	20.000	0.000	5.089
18	14.614	cnt_13_s0/Q	cnt_11_s0/D	clk:[R]	clk:[R]	20.000	0.000	5.089
19	14.614	cnt_13_s0/Q	cnt_10_s0/D	clk:[R]	clk:[R]	20.000	0.000	5.089
20	14.614	cnt_13_s0/Q	cnt_4_s0/D	clk:[R]	clk:[R]	20.000	0.000	5.089
21	14.695	cnt_13_s0/Q	cnt_20_s0/D	clk:[R]	clk:[R]	20.000	0.000	5.008
22	14.987	cnt_13_s0/Q	cnt_12_s0/D	clk:[R]	clk:[R]	20.000	0.000	4.717
23	15.465	cnt_13_s0/Q	cnt_22_s0/D	clk:[R]	clk:[R]	20.000	0.000	4.239
24	15.466	cnt_13_s0/Q	led_s3/CE	clk:[R]	clk:[R]	20.000	0.000	4.502
25	15.466	cnt_13_s0/Q	led1_s3/CE	clk:[R]	clk:[R]	20.000	0.000	4.502

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.524	led1_s3/Q	led1_s3/D	clk:[R]	clk:[R]	0.000	0.000	0.524
2	0.524	cnt_2_s0/Q	cnt_2_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.524
3	0.524	cnt_5_s0/Q	cnt_5_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.524
4	0.524	cnt_13_s0/Q	cnt_13_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.524
5	0.524	cnt_14_s0/Q	cnt_14_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.524
6	0.524	cnt_22_s0/Q	cnt_22_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.524
7	0.525	cnt_1_s0/Q	cnt_1_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.525
8	0.525	cnt_10_s0/Q	cnt_10_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.525
9	0.525	cnt_17_s0/Q	cnt_17_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.525
10	0.525	cnt_23_s0/Q	cnt_23_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.525
11	0.526	cnt_8_s0/Q	cnt_8_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.526
12	0.526	cnt_21_s0/Q	cnt_21_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.526
13	0.699	cnt_10_s0/Q	cnt_11_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.699
14	0.704	cnt_23_s0/Q	cnt_24_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.704
15	0.785	led_s3/Q	led_s3/D	clk:[R]	clk:[R]	0.000	0.000	0.785
16	0.785	cnt_3_s0/Q	cnt_3_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.785
17	0.785	cnt_15_s0/Q	cnt_15_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.785
18	0.785	cnt_16_s0/Q	cnt_16_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.785
19	0.786	cnt_4_s0/Q	cnt_4_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.786
20	0.786	cnt_6_s0/Q	cnt_6_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.786
21	0.786	cnt_9_s0/Q	cnt_9_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.786
22	0.786	cnt_12_s0/Q	cnt_12_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.786
23	0.787	cnt_0_s0/Q	cnt_0_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.787
24	0.787	cnt_20_s0/Q	cnt_20_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.787
25	0.787	cnt_18_s0/Q	cnt_18_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.787

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	6.948	7.874	0.926	High Pulse Width	clk	cnt_24_s0
2	6.948	7.874	0.926	High Pulse Width	clk	cnt_23_s0
3	6.948	7.874	0.926	High Pulse Width	clk	cnt_21_s0
4	6.948	7.874	0.926	High Pulse Width	clk	cnt_17_s0
5	6.948	7.874	0.926	High Pulse Width	clk	cnt_9_s0
6	6.948	7.874	0.926	High Pulse Width	clk	cnt_10_s0
7	6.948	7.874	0.926	High Pulse Width	clk	cnt_18_s0
8	6.948	7.874	0.926	High Pulse Width	clk	cnt_11_s0
9	6.948	7.874	0.926	High Pulse Width	clk	led1_s3
10	6.948	7.874	0.926	High Pulse Width	clk	cnt_12_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	13.838
Data Arrival Time	10.276
Data Required Time	24.114
From	cnt_13_s0
To	cnt_9_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C8[1][A]	cnt_13_s0/CLK
4.750	0.340	tC2Q	RF	5	R8C8[1][A]	cnt_13_s0/Q
5.023	0.273	tNET	FF	1	R8C8[3][A]	n45_s2/I0
5.838	0.814	tINS	FF	6	R8C8[3][A]	n45_s2/F
6.805	0.967	tNET	FF	1	R9C11[2][B]	n112_s20/I1
7.570	0.765	tINS	FF	2	R9C11[2][B]	n112_s20/F
7.578	0.008	tNET	FF	1	R9C11[3][B]	n38_s3/I2
8.342	0.765	tINS	FF	22	R9C11[3][B]	n38_s3/F
9.812	1.470	tNET	FF	1	R8C11[1][B]	n53_s1/I2
10.276	0.464	tINS	FF	1	R8C11[1][B]	n53_s1/F
10.276	0.000	tNET	FF	1	R8C11[1][B]	cnt_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R8C11[1][B]	cnt_9_s0/CLK
24.114	-0.296	tSu		1	R8C11[1][B]	cnt_9_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.808, 47.865%; route: 2.718, 46.345%; tC2Q: 0.340, 5.790%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path2

Path Summary:

Slack	14.002
Data Arrival Time	10.112
Data Required Time	24.114
From	cnt_13_s0
To	cnt_14_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C8[1][A]	cnt_13_s0/CLK
4.750	0.340	tC2Q	RF	5	R8C8[1][A]	cnt_13_s0/Q
5.023	0.273	tNET	FF	1	R8C8[3][A]	n45_s2/I0
5.838	0.814	tINS	FF	6	R8C8[3][A]	n45_s2/F
6.805	0.967	tNET	FF	1	R9C11[2][B]	n112_s20/I1
7.570	0.765	tINS	FF	2	R9C11[2][B]	n112_s20/F
7.578	0.008	tNET	FF	1	R9C11[3][B]	n38_s3/I2
8.342	0.765	tINS	FF	22	R9C11[3][B]	n38_s3/F
9.347	1.005	tNET	FF	1	R8C8[0][A]	n48_s1/I2
10.112	0.765	tINS	FF	1	R8C8[0][A]	n48_s1/F
10.112	0.000	tNET	FF	1	R8C8[0][A]	cnt_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R8C8[0][A]	cnt_14_s0/CLK
24.114	-0.296	tSu		1	R8C8[0][A]	cnt_14_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 3.108, 54.521%; route: 2.253, 39.523%; tC2Q: 0.340, 5.957%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path3

Path Summary:

Slack	14.002
Data Arrival Time	10.112
Data Required Time	24.114
From	cnt_13_s0
To	cnt_13_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C8[1][A]	cnt_13_s0/CLK
4.750	0.340	tC2Q	RF	5	R8C8[1][A]	cnt_13_s0/Q
5.023	0.273	tNET	FF	1	R8C8[3][A]	n45_s2/I0
5.838	0.814	tINS	FF	6	R8C8[3][A]	n45_s2/F
6.805	0.967	tNET	FF	1	R9C11[2][B]	n112_s20/I1
7.570	0.765	tINS	FF	2	R9C11[2][B]	n112_s20/F
7.578	0.008	tNET	FF	1	R9C11[3][B]	n38_s3/I2
8.342	0.765	tINS	FF	22	R9C11[3][B]	n38_s3/F
9.347	1.005	tNET	FF	1	R8C8[1][A]	n49_s1/I0
10.112	0.765	tINS	FF	1	R8C8[1][A]	n49_s1/F
10.112	0.000	tNET	FF	1	R8C8[1][A]	cnt_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R8C8[1][A]	cnt_13_s0/CLK
24.114	-0.296	tSu		1	R8C8[1][A]	cnt_13_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 3.108, 54.521%; route: 2.253, 39.523%; tC2Q: 0.340, 5.957%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path4

Path Summary:

Slack	14.303
Data Arrival Time	9.811
Data Required Time	24.114
From	cnt_13_s0
To	cnt_16_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C8[1][A]	cnt_13_s0/CLK
4.750	0.340	tC2Q	RF	5	R8C8[1][A]	cnt_13_s0/Q
5.023	0.273	tNET	FF	1	R8C8[3][A]	n45_s2/I0
5.838	0.814	tINS	FF	6	R8C8[3][A]	n45_s2/F
6.805	0.967	tNET	FF	1	R9C11[2][B]	n112_s20/I1
7.570	0.765	tINS	FF	2	R9C11[2][B]	n112_s20/F
7.578	0.008	tNET	FF	1	R9C11[3][B]	n38_s3/I2
8.342	0.765	tINS	FF	22	R9C11[3][B]	n38_s3/F
9.347	1.005	tNET	FF	1	R8C8[1][B]	n46_s1/I2
9.811	0.464	tINS	FF	1	R8C8[1][B]	n46_s1/F
9.811	0.000	tNET	FF	1	R8C8[1][B]	cnt_16_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R8C8[1][B]	cnt_16_s0/CLK
24.114	-0.296	tSu		1	R8C8[1][B]	cnt_16_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.808, 51.987%; route: 2.253, 41.724%; tC2Q: 0.340, 6.289%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path5

Path Summary:

Slack	14.303
Data Arrival Time	9.811
Data Required Time	24.114
From	cnt_13_s0
To	cnt_15_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C8[1][A]	cnt_13_s0/CLK
4.750	0.340	tC2Q	RF	5	R8C8[1][A]	cnt_13_s0/Q
5.023	0.273	tNET	FF	1	R8C8[3][A]	n45_s2/I0
5.838	0.814	tINS	FF	6	R8C8[3][A]	n45_s2/F
6.805	0.967	tNET	FF	1	R9C11[2][B]	n112_s20/I1
7.570	0.765	tINS	FF	2	R9C11[2][B]	n112_s20/F
7.578	0.008	tNET	FF	1	R9C11[3][B]	n38_s3/I2
8.342	0.765	tINS	FF	22	R9C11[3][B]	n38_s3/F
9.347	1.005	tNET	FF	1	R8C8[0][B]	n47_s1/I2
9.811	0.464	tINS	FF	1	R8C8[0][B]	n47_s1/F
9.811	0.000	tNET	FF	1	R8C8[0][B]	cnt_15_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R8C8[0][B]	cnt_15_s0/CLK
24.114	-0.296	tSu		1	R8C8[0][B]	cnt_15_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.808, 51.987%; route: 2.253, 41.724%; tC2Q: 0.340, 6.289%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path6

Path Summary:

Slack	14.325
Data Arrival Time	9.789
Data Required Time	24.114
From	cnt_13_s0
To	cnt_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C8[1][A]	cnt_13_s0/CLK
4.750	0.340	tC2Q	RF	5	R8C8[1][A]	cnt_13_s0/Q
5.023	0.273	tNET	FF	1	R8C8[3][A]	n45_s2/I0
5.838	0.814	tINS	FF	6	R8C8[3][A]	n45_s2/F
6.805	0.967	tNET	FF	1	R9C11[2][B]	n112_s20/I1
7.570	0.765	tINS	FF	2	R9C11[2][B]	n112_s20/F
7.578	0.008	tNET	FF	1	R9C11[3][B]	n38_s3/I2
8.342	0.765	tINS	FF	22	R9C11[3][B]	n38_s3/F
8.975	0.632	tNET	FF	1	R8C10[2][B]	n62_s2/I1
9.789	0.814	tINS	FF	1	R8C10[2][B]	n62_s2/F
9.789	0.000	tNET	FF	1	R8C10[2][B]	cnt_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R8C10[2][B]	cnt_0_s0/CLK
24.114	-0.296	tSu		1	R8C10[2][B]	cnt_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 3.158, 58.717%; route: 1.881, 34.969%; tC2Q: 0.340, 6.314%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path7

Path Summary:

Slack	14.325
Data Arrival Time	9.789
Data Required Time	24.114
From	cnt_13_s0
To	cnt_7_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C8[1][A]	cnt_13_s0/CLK
4.750	0.340	tC2Q	RF	5	R8C8[1][A]	cnt_13_s0/Q
5.023	0.273	tNET	FF	1	R8C8[3][A]	n45_s2/I0
5.838	0.814	tINS	FF	6	R8C8[3][A]	n45_s2/F
6.805	0.967	tNET	FF	1	R9C11[2][B]	n112_s20/I1
7.570	0.765	tINS	FF	2	R9C11[2][B]	n112_s20/F
7.578	0.008	tNET	FF	1	R9C11[3][B]	n38_s3/I2
8.342	0.765	tINS	FF	22	R9C11[3][B]	n38_s3/F
8.975	0.632	tNET	FF	1	R8C10[2][A]	n55_s1/I2
9.789	0.814	tINS	FF	1	R8C10[2][A]	n55_s1/F
9.789	0.000	tNET	FF	1	R8C10[2][A]	cnt_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R8C10[2][A]	cnt_7_s0/CLK
24.114	-0.296	tSu		1	R8C10[2][A]	cnt_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 3.158, 58.717%; route: 1.881, 34.969%; tC2Q: 0.340, 6.314%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path8

Path Summary:

Slack	14.333
Data Arrival Time	9.781
Data Required Time	24.114
From	cnt_13_s0
To	cnt_8_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C8[1][A]	cnt_13_s0/CLK
4.750	0.340	tC2Q	RF	5	R8C8[1][A]	cnt_13_s0/Q
5.023	0.273	tNET	FF	1	R8C8[3][A]	n45_s2/I0
5.838	0.814	tINS	FF	6	R8C8[3][A]	n45_s2/F
6.805	0.967	tNET	FF	1	R9C11[2][B]	n112_s20/I1
7.570	0.765	tINS	FF	2	R9C11[2][B]	n112_s20/F
7.578	0.008	tNET	FF	1	R9C11[3][B]	n38_s3/I2
8.342	0.765	tINS	FF	22	R9C11[3][B]	n38_s3/F
8.967	0.625	tNET	FF	1	R8C11[1][A]	n54_s2/I0
9.781	0.814	tINS	FF	1	R8C11[1][A]	n54_s2/F
9.781	0.000	tNET	FF	1	R8C11[1][A]	cnt_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R8C11[1][A]	cnt_8_s0/CLK
24.114	-0.296	tSu		1	R8C11[1][A]	cnt_8_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 3.158, 58.803%; route: 1.873, 34.873%; tC2Q: 0.340, 6.324%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path9

Path Summary:

Slack	14.365
Data Arrival Time	9.750
Data Required Time	24.114
From	cnt_13_s0
To	cnt_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C8[1][A]	cnt_13_s0/CLK
4.750	0.340	tC2Q	RF	5	R8C8[1][A]	cnt_13_s0/Q
5.023	0.273	tNET	FF	1	R8C8[3][A]	n45_s2/I0
5.838	0.814	tINS	FF	6	R8C8[3][A]	n45_s2/F
6.805	0.967	tNET	FF	1	R9C11[2][B]	n112_s20/I1
7.570	0.765	tINS	FF	2	R9C11[2][B]	n112_s20/F
7.578	0.008	tNET	FF	1	R9C11[3][B]	n38_s3/I2
8.342	0.765	tINS	FF	22	R9C11[3][B]	n38_s3/F
8.985	0.643	tNET	FF	1	R8C9[1][A]	n61_s1/I0
9.750	0.765	tINS	FF	1	R8C9[1][A]	n61_s1/F
9.750	0.000	tNET	FF	1	R8C9[1][A]	cnt_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R8C9[1][A]	cnt_1_s0/CLK
24.114	-0.296	tSu		1	R8C9[1][A]	cnt_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 3.108, 58.222%; route: 1.891, 35.417%; tC2Q: 0.340, 6.361%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path10

Path Summary:

Slack	14.365
Data Arrival Time	9.750
Data Required Time	24.114
From	cnt_13_s0
To	cnt_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C8[1][A]	cnt_13_s0/CLK
4.750	0.340	tC2Q	RF	5	R8C8[1][A]	cnt_13_s0/Q
5.023	0.273	tNET	FF	1	R8C8[3][A]	n45_s2/I0
5.838	0.814	tINS	FF	6	R8C8[3][A]	n45_s2/F
6.805	0.967	tNET	FF	1	R9C11[2][B]	n112_s20/I1
7.570	0.765	tINS	FF	2	R9C11[2][B]	n112_s20/F
7.578	0.008	tNET	FF	1	R9C11[3][B]	n38_s3/I2
8.342	0.765	tINS	FF	22	R9C11[3][B]	n38_s3/F
8.985	0.643	tNET	FF	1	R8C9[0][A]	n60_s2/I0
9.750	0.765	tINS	FF	1	R8C9[0][A]	n60_s2/F
9.750	0.000	tNET	FF	1	R8C9[0][A]	cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R8C9[0][A]	cnt_2_s0/CLK
24.114	-0.296	tSu		1	R8C9[0][A]	cnt_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 3.108, 58.222%; route: 1.891, 35.417%; tC2Q: 0.340, 6.361%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path11

Path Summary:

Slack	14.371
Data Arrival Time	9.743
Data Required Time	24.114
From	cnt_13_s0
To	cnt_6_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C8[1][A]	cnt_13_s0/CLK
4.750	0.340	tC2Q	RF	5	R8C8[1][A]	cnt_13_s0/Q
5.023	0.273	tNET	FF	1	R8C8[3][A]	n45_s2/I0
5.838	0.814	tINS	FF	6	R8C8[3][A]	n45_s2/F
6.805	0.967	tNET	FF	1	R9C11[2][B]	n112_s20/I1
7.570	0.765	tINS	FF	2	R9C11[2][B]	n112_s20/F
7.578	0.008	tNET	FF	1	R9C11[3][B]	n38_s3/I2
8.342	0.765	tINS	FF	22	R9C11[3][B]	n38_s3/F
8.978	0.636	tNET	FF	1	R8C12[0][B]	n56_s1/I0
9.743	0.765	tINS	FF	1	R8C12[0][B]	n56_s1/F
9.743	0.000	tNET	FF	1	R8C12[0][B]	cnt_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R8C12[0][B]	cnt_6_s0/CLK
24.114	-0.296	tSu		1	R8C12[0][B]	cnt_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 3.108, 58.295%; route: 1.884, 35.336%; tC2Q: 0.340, 6.369%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path12

Path Summary:

Slack	14.371
Data Arrival Time	9.743
Data Required Time	24.114
From	cnt_13_s0
To	cnt_23_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C8[1][A]	cnt_13_s0/CLK
4.750	0.340	tC2Q	RF	5	R8C8[1][A]	cnt_13_s0/Q
5.023	0.273	tNET	FF	1	R8C8[3][A]	n45_s2/I0
5.838	0.814	tINS	FF	6	R8C8[3][A]	n45_s2/F
6.805	0.967	tNET	FF	1	R9C11[2][B]	n112_s20/I1
7.570	0.765	tINS	FF	2	R9C11[2][B]	n112_s20/F
7.578	0.008	tNET	FF	1	R9C11[3][B]	n38_s3/I2
8.342	0.765	tINS	FF	22	R9C11[3][B]	n38_s3/F
8.978	0.636	tNET	FF	1	R8C12[1][A]	n39_s1/I0
9.743	0.765	tINS	FF	1	R8C12[1][A]	n39_s1/F
9.743	0.000	tNET	FF	1	R8C12[1][A]	cnt_23_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R8C12[1][A]	cnt_23_s0/CLK
24.114	-0.296	tSu		1	R8C12[1][A]	cnt_23_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 3.108, 58.295%; route: 1.884, 35.336%; tC2Q: 0.340, 6.369%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path13

Path Summary:

Slack	14.371
Data Arrival Time	9.743
Data Required Time	24.114
From	cnt_13_s0
To	cnt_24_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C8[1][A]	cnt_13_s0/CLK
4.750	0.340	tC2Q	RF	5	R8C8[1][A]	cnt_13_s0/Q
5.023	0.273	tNET	FF	1	R8C8[3][A]	n45_s2/I0
5.838	0.814	tINS	FF	6	R8C8[3][A]	n45_s2/F
6.805	0.967	tNET	FF	1	R9C11[2][B]	n112_s20/I1
7.570	0.765	tINS	FF	2	R9C11[2][B]	n112_s20/F
7.578	0.008	tNET	FF	1	R9C11[3][B]	n38_s3/I2
8.342	0.765	tINS	FF	22	R9C11[3][B]	n38_s3/F
8.978	0.636	tNET	FF	1	R8C12[1][B]	n38_s1/I3
9.743	0.765	tINS	FF	1	R8C12[1][B]	n38_s1/F
9.743	0.000	tNET	FF	1	R8C12[1][B]	cnt_24_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R8C12[1][B]	cnt_24_s0/CLK
24.114	-0.296	tSu		1	R8C12[1][B]	cnt_24_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 3.108, 58.295%; route: 1.884, 35.336%; tC2Q: 0.340, 6.369%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path14

Path Summary:

Slack	14.375
Data Arrival Time	9.740
Data Required Time	24.114
From	cnt_13_s0
To	cnt_17_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C8[1][A]	cnt_13_s0/CLK
4.750	0.340	tC2Q	RF	5	R8C8[1][A]	cnt_13_s0/Q
5.023	0.273	tNET	FF	1	R8C8[3][A]	n45_s2/I0
5.838	0.814	tINS	FF	6	R8C8[3][A]	n45_s2/F
6.805	0.967	tNET	FF	1	R9C11[2][B]	n112_s20/I1
7.570	0.765	tINS	FF	2	R9C11[2][B]	n112_s20/F
7.578	0.008	tNET	FF	1	R9C11[3][B]	n38_s3/I2
8.342	0.765	tINS	FF	22	R9C11[3][B]	n38_s3/F
8.975	0.632	tNET	FF	1	R8C10[1][A]	n45_s1/I2
9.740	0.765	tINS	FF	1	R8C10[1][A]	n45_s1/F
9.740	0.000	tNET	FF	1	R8C10[1][A]	cnt_17_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R8C10[1][A]	cnt_17_s0/CLK
24.114	-0.296	tSu		1	R8C10[1][A]	cnt_17_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 3.108, 58.332%; route: 1.881, 35.295%; tC2Q: 0.340, 6.373%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path15

Path Summary:

Slack	14.375
Data Arrival Time	9.740
Data Required Time	24.114
From	cnt_13_s0
To	cnt_5_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C8[1][A]	cnt_13_s0/CLK
4.750	0.340	tC2Q	RF	5	R8C8[1][A]	cnt_13_s0/Q
5.023	0.273	tNET	FF	1	R8C8[3][A]	n45_s2/I0
5.838	0.814	tINS	FF	6	R8C8[3][A]	n45_s2/F
6.805	0.967	tNET	FF	1	R9C11[2][B]	n112_s20/I1
7.570	0.765	tINS	FF	2	R9C11[2][B]	n112_s20/F
7.578	0.008	tNET	FF	1	R9C11[3][B]	n38_s3/I2
8.342	0.765	tINS	FF	22	R9C11[3][B]	n38_s3/F
8.975	0.632	tNET	FF	1	R8C10[0][A]	n57_s1/I2
9.740	0.765	tINS	FF	1	R8C10[0][A]	n57_s1/F
9.740	0.000	tNET	FF	1	R8C10[0][A]	cnt_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R8C10[0][A]	cnt_5_s0/CLK
24.114	-0.296	tSu		1	R8C10[0][A]	cnt_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 3.108, 58.332%; route: 1.881, 35.295%; tC2Q: 0.340, 6.373%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path16

Path Summary:

Slack	14.420
Data Arrival Time	9.694
Data Required Time	24.114
From	cnt_13_s0
To	cnt_3_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C8[1][A]	cnt_13_s0/CLK
4.750	0.340	tC2Q	RF	5	R8C8[1][A]	cnt_13_s0/Q
5.023	0.273	tNET	FF	1	R8C8[3][A]	n45_s2/I0
5.838	0.814	tINS	FF	6	R8C8[3][A]	n45_s2/F
6.805	0.967	tNET	FF	1	R9C11[2][B]	n112_s20/I1
7.570	0.765	tINS	FF	2	R9C11[2][B]	n112_s20/F
7.578	0.008	tNET	FF	1	R9C11[3][B]	n38_s3/I2
8.342	0.765	tINS	FF	22	R9C11[3][B]	n38_s3/F
9.230	0.888	tNET	FF	1	R8C9[1][B]	n59_s1/I2
9.694	0.464	tINS	FF	1	R8C9[1][B]	n59_s1/F
9.694	0.000	tNET	FF	1	R8C9[1][B]	cnt_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R8C9[1][B]	cnt_3_s0/CLK
24.114	-0.296	tSu		1	R8C9[1][B]	cnt_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.808, 53.141%; route: 2.136, 40.430%; tC2Q: 0.340, 6.428%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path17

Path Summary:

Slack	14.614
Data Arrival Time	9.500
Data Required Time	24.114
From	cnt_13_s0
To	cnt_19_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C8[1][A]	cnt_13_s0/CLK
4.750	0.340	tC2Q	RF	5	R8C8[1][A]	cnt_13_s0/Q
5.023	0.273	tNET	FF	1	R8C8[3][A]	n45_s2/I0
5.838	0.814	tINS	FF	6	R8C8[3][A]	n45_s2/F
6.805	0.967	tNET	FF	1	R9C11[2][B]	n112_s20/I1
7.570	0.765	tINS	FF	2	R9C11[2][B]	n112_s20/F
7.578	0.008	tNET	FF	1	R9C11[3][B]	n38_s3/I2
8.342	0.765	tINS	FF	22	R9C11[3][B]	n38_s3/F
8.735	0.393	tNET	FF	1	R9C10[2][A]	n43_s1/I2
9.500	0.765	tINS	FF	1	R9C10[2][A]	n43_s1/F
9.500	0.000	tNET	FF	1	R9C10[2][A]	cnt_19_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R9C10[2][A]	cnt_19_s0/CLK
24.114	-0.296	tSu		1	R9C10[2][A]	cnt_19_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 3.108, 61.078%; route: 1.641, 32.249%; tC2Q: 0.340, 6.673%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path18

Path Summary:

Slack	14.614
Data Arrival Time	9.500
Data Required Time	24.114
From	cnt_13_s0
To	cnt_11_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C8[1][A]	cnt_13_s0/CLK
4.750	0.340	tC2Q	RF	5	R8C8[1][A]	cnt_13_s0/Q
5.023	0.273	tNET	FF	1	R8C8[3][A]	n45_s2/I0
5.838	0.814	tINS	FF	6	R8C8[3][A]	n45_s2/F
6.805	0.967	tNET	FF	1	R9C11[2][B]	n112_s20/I1
7.570	0.765	tINS	FF	2	R9C11[2][B]	n112_s20/F
7.578	0.008	tNET	FF	1	R9C11[3][B]	n38_s3/I2
8.342	0.765	tINS	FF	22	R9C11[3][B]	n38_s3/F
8.735	0.393	tNET	FF	1	R9C10[0][B]	n51_s1/I2
9.500	0.765	tINS	FF	1	R9C10[0][B]	n51_s1/F
9.500	0.000	tNET	FF	1	R9C10[0][B]	cnt_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R9C10[0][B]	cnt_11_s0/CLK
24.114	-0.296	tSu		1	R9C10[0][B]	cnt_11_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 3.108, 61.078%; route: 1.641, 32.249%; tC2Q: 0.340, 6.673%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path19

Path Summary:

Slack	14.614
Data Arrival Time	9.500
Data Required Time	24.114
From	cnt_13_s0
To	cnt_10_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C8[1][A]	cnt_13_s0/CLK
4.750	0.340	tC2Q	RF	5	R8C8[1][A]	cnt_13_s0/Q
5.023	0.273	tNET	FF	1	R8C8[3][A]	n45_s2/I0
5.838	0.814	tINS	FF	6	R8C8[3][A]	n45_s2/F
6.805	0.967	tNET	FF	1	R9C11[2][B]	n112_s20/I1
7.570	0.765	tINS	FF	2	R9C11[2][B]	n112_s20/F
7.578	0.008	tNET	FF	1	R9C11[3][B]	n38_s3/I2
8.342	0.765	tINS	FF	22	R9C11[3][B]	n38_s3/F
8.735	0.393	tNET	FF	1	R9C10[0][A]	n52_s1/I0
9.500	0.765	tINS	FF	1	R9C10[0][A]	n52_s1/F
9.500	0.000	tNET	FF	1	R9C10[0][A]	cnt_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R9C10[0][A]	cnt_10_s0/CLK
24.114	-0.296	tSu		1	R9C10[0][A]	cnt_10_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 3.108, 61.078%; route: 1.641, 32.249%; tC2Q: 0.340, 6.673%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path20

Path Summary:

Slack	14.614
Data Arrival Time	9.500
Data Required Time	24.114
From	cnt_13_s0
To	cnt_4_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C8[1][A]	cnt_13_s0/CLK
4.750	0.340	tC2Q	RF	5	R8C8[1][A]	cnt_13_s0/Q
5.023	0.273	tNET	FF	1	R8C8[3][A]	n45_s2/I0
5.838	0.814	tINS	FF	6	R8C8[3][A]	n45_s2/F
6.805	0.967	tNET	FF	1	R9C11[2][B]	n112_s20/I1
7.570	0.765	tINS	FF	2	R9C11[2][B]	n112_s20/F
7.578	0.008	tNET	FF	1	R9C11[3][B]	n38_s3/I2
8.342	0.765	tINS	FF	22	R9C11[3][B]	n38_s3/F
8.735	0.393	tNET	FF	1	R9C10[1][B]	n58_s1/I0
9.500	0.765	tINS	FF	1	R9C10[1][B]	n58_s1/F
9.500	0.000	tNET	FF	1	R9C10[1][B]	cnt_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R9C10[1][B]	cnt_4_s0/CLK
24.114	-0.296	tSu		1	R9C10[1][B]	cnt_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 3.108, 61.078%; route: 1.641, 32.249%; tC2Q: 0.340, 6.673%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path21

Path Summary:

Slack	14.695
Data Arrival Time	9.419
Data Required Time	24.114
From	cnt_13_s0
To	cnt_20_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C8[1][A]	cnt_13_s0/CLK
4.750	0.340	tC2Q	RF	5	R8C8[1][A]	cnt_13_s0/Q
5.023	0.273	tNET	FF	1	R8C8[3][A]	n45_s2/I0
5.838	0.814	tINS	FF	6	R8C8[3][A]	n45_s2/F
6.805	0.967	tNET	FF	1	R9C11[2][B]	n112_s20/I1
7.570	0.765	tINS	FF	2	R9C11[2][B]	n112_s20/F
7.578	0.008	tNET	FF	1	R9C11[3][B]	n38_s3/I2
8.338	0.760	tINS	FR	22	R9C11[3][B]	n38_s3/F
8.654	0.316	tNET	RR	1	R9C12[1][B]	n42_s1/I2
9.419	0.765	tINS	RF	1	R9C12[1][B]	n42_s1/F
9.419	0.000	tNET	FF	1	R9C12[1][B]	cnt_20_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R9C12[1][B]	cnt_20_s0/CLK
24.114	-0.296	tSu		1	R9C12[1][B]	cnt_20_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 3.104, 61.979%; route: 1.565, 31.240%; tC2Q: 0.340, 6.781%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path22

Path Summary:

Slack	14.987
Data Arrival Time	9.127
Data Required Time	24.114
From	cnt_13_s0
To	cnt_12_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C8[1][A]	cnt_13_s0/CLK
4.750	0.340	tC2Q	RF	5	R8C8[1][A]	cnt_13_s0/Q
5.023	0.273	tNET	FF	1	R8C8[3][A]	n45_s2/I0
5.838	0.814	tINS	FF	6	R8C8[3][A]	n45_s2/F
6.805	0.967	tNET	FF	1	R9C11[2][B]	n112_s20/I1
7.570	0.765	tINS	FF	2	R9C11[2][B]	n112_s20/F
7.578	0.008	tNET	FF	1	R9C11[3][B]	n38_s3/I2
8.342	0.765	tINS	FF	22	R9C11[3][B]	n38_s3/F
8.363	0.020	tNET	FF	1	R9C11[1][B]	n50_s1/I1
9.127	0.765	tINS	FF	1	R9C11[1][B]	n50_s1/F
9.127	0.000	tNET	FF	1	R9C11[1][B]	cnt_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R9C11[1][B]	cnt_12_s0/CLK
24.114	-0.296	tSu		1	R9C11[1][B]	cnt_12_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 3.108, 65.902%; route: 1.269, 26.898%; tC2Q: 0.340, 7.200%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path23

Path Summary:

Slack	15.465
Data Arrival Time	8.650
Data Required Time	24.114
From	cnt_13_s0
To	cnt_22_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C8[1][A]	cnt_13_s0/CLK
4.750	0.340	tC2Q	RF	5	R8C8[1][A]	cnt_13_s0/Q
5.023	0.273	tNET	FF	1	R8C8[3][A]	n45_s2/I0
5.838	0.814	tINS	FF	6	R8C8[3][A]	n45_s2/F
6.449	0.612	tNET	FF	1	R9C10[3][A]	n43_s2/I2
7.264	0.814	tINS	FF	2	R9C10[3][A]	n43_s2/F
7.272	0.008	tNET	FF	1	R9C10[2][B]	n40_s8/I3
7.881	0.609	tINS	FF	1	R9C10[2][B]	n40_s8/F
7.885	0.004	tNET	FF	1	R9C10[1][A]	n40_s1/I1
8.650	0.765	tINS	FF	1	R9C10[1][A]	n40_s1/F
8.650	0.000	tNET	FF	1	R9C10[1][A]	cnt_22_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R9C10[1][A]	cnt_22_s0/CLK
24.114	-0.296	tSu		1	R9C10[1][A]	cnt_22_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 3.003, 70.832%; route: 0.897, 21.156%; tC2Q: 0.340, 8.012%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path24

Path Summary:

Slack	15.466
Data Arrival Time	8.912
Data Required Time	24.378
From	cnt_13_s0
To	led_s3
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C8[1][A]	cnt_13_s0/CLK
4.750	0.340	tC2Q	RF	5	R8C8[1][A]	cnt_13_s0/Q
5.023	0.273	tNET	FF	1	R8C8[3][A]	n45_s2/I0
5.838	0.814	tINS	FF	6	R8C8[3][A]	n45_s2/F
6.805	0.967	tNET	FF	1	R9C11[2][B]	n112_s20/I1
7.565	0.760	tINS	FR	2	R9C11[2][B]	n112_s20/F
7.877	0.312	tNET	RR	1	R9C12[2][A]	n112_s19/I0
8.663	0.786	tINS	RR	2	R9C12[2][A]	n112_s19/F
8.912	0.249	tNET	RR	1	R9C12[0][B]	led_s3/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R9C12[0][B]	led_s3/CLK
24.378	-0.032	tSu		1	R9C12[0][B]	led_s3

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.361, 52.442%; route: 1.801, 40.013%; tC2Q: 0.340, 7.544%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path25

Path Summary:

Slack	15.466
Data Arrival Time	8.912
Data Required Time	24.378
From	cnt_13_s0
To	led1_s3
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C8[1][A]	cnt_13_s0/CLK
4.750	0.340	tC2Q	RF	5	R8C8[1][A]	cnt_13_s0/Q
5.023	0.273	tNET	FF	1	R8C8[3][A]	n45_s2/I0
5.838	0.814	tINS	FF	6	R8C8[3][A]	n45_s2/F
6.805	0.967	tNET	FF	1	R9C11[2][B]	n112_s20/I1
7.565	0.760	tINS	FR	2	R9C11[2][B]	n112_s20/F
7.877	0.312	tNET	RR	1	R9C12[2][A]	n112_s19/I0
8.663	0.786	tINS	RR	2	R9C12[2][A]	n112_s19/F
8.912	0.249	tNET	RR	1	R9C12[0][A]	led1_s3/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	27	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R9C12[0][A]	led1_s3/CLK
24.378	-0.032	tSu		1	R9C12[0][A]	led1_s3

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.361, 52.442%; route: 1.801, 40.013%; tC2Q: 0.340, 7.544%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	led1_s3
To	led1_s3
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C12[0][A]	led1_s3/CLK
3.510	0.247	tC2Q	RR	2	R9C12[0][A]	led1_s3/Q
3.512	0.002	tNET	RR	1	R9C12[0][A]	n116_s2/I0
3.788	0.276	tINS	RF	1	R9C12[0][A]	n116_s2/F
3.788	0.000	tNET	FF	1	R9C12[0][A]	led1_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C12[0][A]	led1_s3/CLK
3.263	0.000	tHld		1	R9C12[0][A]	led1_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path2

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	cnt_2_s0
To	cnt_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C9[0][A]	cnt_2_s0/CLK
3.510	0.247	tC2Q	RR	3	R8C9[0][A]	cnt_2_s0/Q
3.512	0.002	tNET	RR	1	R8C9[0][A]	n60_s2/I1
3.788	0.276	tINS	RF	1	R8C9[0][A]	n60_s2/F
3.788	0.000	tNET	FF	1	R8C9[0][A]	cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C9[0][A]	cnt_2_s0/CLK
3.263	0.000	tHld		1	R8C9[0][A]	cnt_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path3

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	cnt_5_s0
To	cnt_5_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C10[0][A]	cnt_5_s0/CLK
3.510	0.247	tC2Q	RR	4	R8C10[0][A]	cnt_5_s0/Q
3.512	0.002	tNET	RR	1	R8C10[0][A]	n57_s1/I3
3.788	0.276	tINS	RF	1	R8C10[0][A]	n57_s1/F
3.788	0.000	tNET	FF	1	R8C10[0][A]	cnt_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C10[0][A]	cnt_5_s0/CLK
3.263	0.000	tHld		1	R8C10[0][A]	cnt_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path4

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	cnt_13_s0
To	cnt_13_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C8[1][A]	cnt_13_s0/CLK
3.510	0.247	tC2Q	RR	5	R8C8[1][A]	cnt_13_s0/Q
3.512	0.002	tNET	RR	1	R8C8[1][A]	n49_s1/I1
3.788	0.276	tINS	RF	1	R8C8[1][A]	n49_s1/F
3.788	0.000	tNET	FF	1	R8C8[1][A]	cnt_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C8[1][A]	cnt_13_s0/CLK
3.263	0.000	tHld		1	R8C8[1][A]	cnt_13_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path5

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	cnt_14_s0
To	cnt_14_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C8[0][A]	cnt_14_s0/CLK
3.510	0.247	tC2Q	RR	4	R8C8[0][A]	cnt_14_s0/Q
3.512	0.002	tNET	RR	1	R8C8[0][A]	n48_s1/I3
3.788	0.276	tINS	RF	1	R8C8[0][A]	n48_s1/F
3.788	0.000	tNET	FF	1	R8C8[0][A]	cnt_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C8[0][A]	cnt_14_s0/CLK
3.263	0.000	tHld		1	R8C8[0][A]	cnt_14_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path6

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	cnt_22_s0
To	cnt_22_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C10[1][A]	cnt_22_s0/CLK
3.510	0.247	tC2Q	RR	3	R9C10[1][A]	cnt_22_s0/Q
3.512	0.002	tNET	RR	1	R9C10[1][A]	n40_s1/I3
3.788	0.276	tINS	RF	1	R9C10[1][A]	n40_s1/F
3.788	0.000	tNET	FF	1	R9C10[1][A]	cnt_22_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C10[1][A]	cnt_22_s0/CLK
3.263	0.000	tHld		1	R9C10[1][A]	cnt_22_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path7

Path Summary:

Slack	0.525
Data Arrival Time	3.788
Data Required Time	3.263
From	cnt_1_s0
To	cnt_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C9[1][A]	cnt_1_s0/CLK
3.510	0.247	tC2Q	RR	4	R8C9[1][A]	cnt_1_s0/Q
3.513	0.003	tNET	RR	1	R8C9[1][A]	n61_s1/I2
3.788	0.276	tINS	RF	1	R8C9[1][A]	n61_s1/F
3.788	0.000	tNET	FF	1	R8C9[1][A]	cnt_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C9[1][A]	cnt_1_s0/CLK
3.263	0.000	tHld		1	R8C9[1][A]	cnt_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path8

Path Summary:

Slack	0.525
Data Arrival Time	3.788
Data Required Time	3.263
From	cnt_10_s0
To	cnt_10_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C10[0][A]	cnt_10_s0/CLK
3.510	0.247	tC2Q	RR	4	R9C10[0][A]	cnt_10_s0/Q
3.513	0.003	tNET	RR	1	R9C10[0][A]	n52_s1/I1
3.788	0.276	tINS	RF	1	R9C10[0][A]	n52_s1/F
3.788	0.000	tNET	FF	1	R9C10[0][A]	cnt_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C10[0][A]	cnt_10_s0/CLK
3.263	0.000	tHld		1	R9C10[0][A]	cnt_10_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path9

Path Summary:

Slack	0.525
Data Arrival Time	3.788
Data Required Time	3.263
From	cnt_17_s0
To	cnt_17_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C10[1][A]	cnt_17_s0/CLK
3.510	0.247	tC2Q	RR	5	R8C10[1][A]	cnt_17_s0/Q
3.513	0.003	tNET	RR	1	R8C10[1][A]	n45_s1/I3
3.788	0.276	tINS	RF	1	R8C10[1][A]	n45_s1/F
3.788	0.000	tNET	FF	1	R8C10[1][A]	cnt_17_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C10[1][A]	cnt_17_s0/CLK
3.263	0.000	tHld		1	R8C10[1][A]	cnt_17_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path10

Path Summary:

Slack	0.525
Data Arrival Time	3.788
Data Required Time	3.263
From	cnt_23_s0
To	cnt_23_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C12[1][A]	cnt_23_s0/CLK
3.510	0.247	tC2Q	RR	4	R8C12[1][A]	cnt_23_s0/Q
3.513	0.003	tNET	RR	1	R8C12[1][A]	n39_s1/I1
3.788	0.276	tINS	RF	1	R8C12[1][A]	n39_s1/F
3.788	0.000	tNET	FF	1	R8C12[1][A]	cnt_23_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C12[1][A]	cnt_23_s0/CLK
3.263	0.000	tHld		1	R8C12[1][A]	cnt_23_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path11

Path Summary:

Slack	0.526
Data Arrival Time	3.789
Data Required Time	3.263
From	cnt_8_s0
To	cnt_8_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C11[1][A]	cnt_8_s0/CLK
3.510	0.247	tC2Q	RR	5	R8C11[1][A]	cnt_8_s0/Q
3.514	0.003	tNET	RR	1	R8C11[1][A]	n54_s2/I1
3.789	0.276	tINS	RF	1	R8C11[1][A]	n54_s2/F
3.789	0.000	tNET	FF	1	R8C11[1][A]	cnt_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C11[1][A]	cnt_8_s0/CLK
3.263	0.000	tHld		1	R8C11[1][A]	cnt_8_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path12

Path Summary:

Slack	0.526
Data Arrival Time	3.789
Data Required Time	3.263
From	cnt_21_s0
To	cnt_21_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C11[0][A]	cnt_21_s0/CLK
3.510	0.247	tC2Q	RR	4	R8C11[0][A]	cnt_21_s0/Q
3.514	0.003	tNET	RR	1	R8C11[0][A]	n41_s1/I3
3.789	0.276	tINS	RF	1	R8C11[0][A]	n41_s1/F
3.789	0.000	tNET	FF	1	R8C11[0][A]	cnt_21_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C11[0][A]	cnt_21_s0/CLK
3.263	0.000	tHld		1	R8C11[0][A]	cnt_21_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path13

Path Summary:

Slack	0.699
Data Arrival Time	3.962
Data Required Time	3.263
From	cnt_10_s0
To	cnt_11_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C10[0][A]	cnt_10_s0/CLK
3.510	0.247	tC2Q	RF	4	R9C10[0][A]	cnt_10_s0/Q
3.686	0.176	tNET	FF	1	R9C10[0][B]	n51_s1/I0
3.962	0.276	tINS	FF	1	R9C10[0][B]	n51_s1/F
3.962	0.000	tNET	FF	1	R9C10[0][B]	cnt_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C10[0][B]	cnt_11_s0/CLK
3.263	0.000	tHld		1	R9C10[0][B]	cnt_11_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 39.447%; route: 0.176, 25.207%; tC2Q: 0.247, 35.347%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path14

Path Summary:

Slack	0.704
Data Arrival Time	3.967
Data Required Time	3.263
From	cnt_23_s0
To	cnt_24_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C12[1][A]	cnt_23_s0/CLK
3.510	0.247	tC2Q	RF	4	R8C12[1][A]	cnt_23_s0/Q
3.692	0.181	tNET	FF	1	R8C12[1][B]	n38_s1/I0
3.967	0.276	tINS	FF	1	R8C12[1][B]	n38_s1/F
3.967	0.000	tNET	FF	1	R8C12[1][B]	cnt_24_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C12[1][B]	cnt_24_s0/CLK
3.263	0.000	tHld		1	R8C12[1][B]	cnt_24_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 39.155%; route: 0.181, 25.760%; tC2Q: 0.247, 35.085%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path15

Path Summary:

Slack	0.785
Data Arrival Time	4.048
Data Required Time	3.263
From	led_s3
To	led_s3
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C12[0][B]	led_s3/CLK
3.510	0.247	tC2Q	RR	2	R9C12[0][B]	led_s3/Q
3.512	0.002	tNET	RR	1	R9C12[0][B]	n115_s2/I0
4.048	0.536	tINS	RR	1	R9C12[0][B]	n115_s2/F
4.048	0.000	tNET	RR	1	R9C12[0][B]	led_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C12[0][B]	led_s3/CLK
3.263	0.000	tHld		1	R9C12[0][B]	led_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.536, 68.322%; route: 0.002, 0.223%; tC2Q: 0.247, 31.456%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path16

Path Summary:

Slack	0.785
Data Arrival Time	4.048
Data Required Time	3.263
From	cnt_3_s0
To	cnt_3_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C9[1][B]	cnt_3_s0/CLK
3.510	0.247	tC2Q	RR	2	R8C9[1][B]	cnt_3_s0/Q
3.512	0.002	tNET	RR	1	R8C9[1][B]	n59_s1/I3
4.048	0.536	tINS	RR	1	R8C9[1][B]	n59_s1/F
4.048	0.000	tNET	RR	1	R8C9[1][B]	cnt_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C9[1][B]	cnt_3_s0/CLK
3.263	0.000	tHld		1	R8C9[1][B]	cnt_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.536, 68.322%; route: 0.002, 0.223%; tC2Q: 0.247, 31.456%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path17

Path Summary:

Slack	0.785
Data Arrival Time	4.048
Data Required Time	3.263
From	cnt_15_s0
To	cnt_15_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C8[0][B]	cnt_15_s0/CLK
3.510	0.247	tC2Q	RR	3	R8C8[0][B]	cnt_15_s0/Q
3.512	0.002	tNET	RR	1	R8C8[0][B]	n47_s1/I3
4.048	0.536	tINS	RR	1	R8C8[0][B]	n47_s1/F
4.048	0.000	tNET	RR	1	R8C8[0][B]	cnt_15_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C8[0][B]	cnt_15_s0/CLK
3.263	0.000	tHld		1	R8C8[0][B]	cnt_15_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.536, 68.322%; route: 0.002, 0.223%; tC2Q: 0.247, 31.456%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path18

Path Summary:

Slack	0.785
Data Arrival Time	4.048
Data Required Time	3.263
From	cnt_16_s0
To	cnt_16_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C8[1][B]	cnt_16_s0/CLK
3.510	0.247	tC2Q	RR	2	R8C8[1][B]	cnt_16_s0/Q
3.512	0.002	tNET	RR	1	R8C8[1][B]	n46_s1/I3
4.048	0.536	tINS	RR	1	R8C8[1][B]	n46_s1/F
4.048	0.000	tNET	RR	1	R8C8[1][B]	cnt_16_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C8[1][B]	cnt_16_s0/CLK
3.263	0.000	tHld		1	R8C8[1][B]	cnt_16_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.536, 68.322%; route: 0.002, 0.223%; tC2Q: 0.247, 31.456%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path19

Path Summary:

Slack	0.786
Data Arrival Time	4.049
Data Required Time	3.263
From	cnt_4_s0
To	cnt_4_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C10[1][B]	cnt_4_s0/CLK
3.510	0.247	tC2Q	RR	5	R9C10[1][B]	cnt_4_s0/Q
3.513	0.003	tNET	RR	1	R9C10[1][B]	n58_s1/I1
4.049	0.536	tINS	RR	1	R9C10[1][B]	n58_s1/F
4.049	0.000	tNET	RR	1	R9C10[1][B]	cnt_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C10[1][B]	cnt_4_s0/CLK
3.263	0.000	tHld		1	R9C10[1][B]	cnt_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.536, 68.246%; route: 0.003, 0.334%; tC2Q: 0.247, 31.421%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path20

Path Summary:

Slack	0.786
Data Arrival Time	4.049
Data Required Time	3.263
From	cnt_6_s0
To	cnt_6_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C12[0][B]	cnt_6_s0/CLK
3.510	0.247	tC2Q	RR	5	R8C12[0][B]	cnt_6_s0/Q
3.513	0.003	tNET	RR	1	R8C12[0][B]	n56_s1/I1
4.049	0.536	tINS	RR	1	R8C12[0][B]	n56_s1/F
4.049	0.000	tNET	RR	1	R8C12[0][B]	cnt_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C12[0][B]	cnt_6_s0/CLK
3.263	0.000	tHld		1	R8C12[0][B]	cnt_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.536, 68.246%; route: 0.003, 0.334%; tC2Q: 0.247, 31.421%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path21

Path Summary:

Slack	0.786
Data Arrival Time	4.049
Data Required Time	3.263
From	cnt_9_s0
To	cnt_9_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C11[1][B]	cnt_9_s0/CLK
3.510	0.247	tC2Q	RR	4	R8C11[1][B]	cnt_9_s0/Q
3.513	0.003	tNET	RR	1	R8C11[1][B]	n53_s1/I3
4.049	0.536	tINS	RR	1	R8C11[1][B]	n53_s1/F
4.049	0.000	tNET	RR	1	R8C11[1][B]	cnt_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C11[1][B]	cnt_9_s0/CLK
3.263	0.000	tHld		1	R8C11[1][B]	cnt_9_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.536, 68.246%; route: 0.003, 0.334%; tC2Q: 0.247, 31.421%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path22

Path Summary:

Slack	0.786
Data Arrival Time	4.049
Data Required Time	3.263
From	cnt_12_s0
To	cnt_12_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C11[1][B]	cnt_12_s0/CLK
3.510	0.247	tC2Q	RR	3	R9C11[1][B]	cnt_12_s0/Q
3.513	0.003	tNET	RR	1	R9C11[1][B]	n50_s1/I2
4.049	0.536	tINS	RR	1	R9C11[1][B]	n50_s1/F
4.049	0.000	tNET	RR	1	R9C11[1][B]	cnt_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C11[1][B]	cnt_12_s0/CLK
3.263	0.000	tHld		1	R9C11[1][B]	cnt_12_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.536, 68.246%; route: 0.003, 0.334%; tC2Q: 0.247, 31.421%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path23

Path Summary:

Slack	0.787
Data Arrival Time	4.050
Data Required Time	3.263
From	cnt_0_s0
To	cnt_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C10[2][B]	cnt_0_s0/CLK
3.510	0.247	tC2Q	RR	5	R8C10[2][B]	cnt_0_s0/Q
3.512	0.002	tNET	RR	1	R8C10[2][B]	n62_s2/I0
4.050	0.538	tINS	RR	1	R8C10[2][B]	n62_s2/F
4.050	0.000	tNET	RR	1	R8C10[2][B]	cnt_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C10[2][B]	cnt_0_s0/CLK
3.263	0.000	tHld		1	R8C10[2][B]	cnt_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.538, 68.381%; route: 0.002, 0.222%; tC2Q: 0.247, 31.396%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path24

Path Summary:

Slack	0.787
Data Arrival Time	4.050
Data Required Time	3.263
From	cnt_20_s0
To	cnt_20_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C12[1][B]	cnt_20_s0/CLK
3.510	0.247	tC2Q	RR	5	R9C12[1][B]	cnt_20_s0/Q
3.514	0.003	tNET	RR	1	R9C12[1][B]	n42_s1/I3
4.050	0.536	tINS	RR	1	R9C12[1][B]	n42_s1/F
4.050	0.000	tNET	RR	1	R9C12[1][B]	cnt_20_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C12[1][B]	cnt_20_s0/CLK
3.263	0.000	tHld		1	R9C12[1][B]	cnt_20_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.536, 68.170%; route: 0.003, 0.445%; tC2Q: 0.247, 31.386%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path25

Path Summary:

Slack	0.787
Data Arrival Time	4.050
Data Required Time	3.263
From	cnt_18_s0
To	cnt_18_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C11[0][B]	cnt_18_s0/CLK
3.510	0.247	tC2Q	RR	6	R8C11[0][B]	cnt_18_s0/Q
3.514	0.003	tNET	RR	1	R8C11[0][B]	n44_s1/I3
4.050	0.536	tINS	RR	1	R8C11[0][B]	n44_s1/F
4.050	0.000	tNET	RR	1	R8C11[0][B]	cnt_18_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	27	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C11[0][B]	cnt_18_s0/CLK
3.263	0.000	tHld		1	R8C11[0][B]	cnt_18_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.536, 68.170%; route: 0.003, 0.445%; tC2Q: 0.247, 31.386%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	clk
Objects:	cnt_24_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	cnt_24_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	cnt_24_s0/CLK

MPW2

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	clk
Objects:	cnt_23_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	cnt_23_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	cnt_23_s0/CLK

MPW3

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	clk
Objects:	cnt_21_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	cnt_21_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	cnt_21_s0/CLK

MPW4

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	clk
Objects:	cnt_17_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	cnt_17_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	cnt_17_s0/CLK

MPW5

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	clk
Objects:	cnt_9_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	cnt_9_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	cnt_9_s0/CLK

MPW6

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	clk
Objects:	cnt_10_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	cnt_10_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	cnt_10_s0/CLK

MPW7

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	clk
Objects:	cnt_18_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	cnt_18_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	cnt_18_s0/CLK

MPW8

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	clk
Objects:	cnt_11_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	cnt_11_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	cnt_11_s0/CLK

MPW9

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	clk
Objects:	led1_s3

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	led1_s3/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	led1_s3/CLK

MPW10

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	clk
Objects:	cnt_12_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	cnt_12_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	cnt_12_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
27	clk_d	13.838	0.195
22	n38_7	13.838	1.470
10	n40_6	14.855	0.982
8	n57_6	14.296	0.608
6	n45_6	13.838	0.971
6	cnt[18]	15.679	0.621
5	cnt[20]	15.201	0.371
5	cnt[13]	13.838	0.273
5	cnt[17]	14.613	0.613
5	cnt[19]	15.332	0.375

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R9C10	75.00%
R8C10	70.83%
R8C11	69.44%
R9C12	56.94%
R8C8	54.17%
R8C9	44.44%
R8C12	43.06%
R9C11	31.94%
R9C8	6.94%
R1C3	5.56%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command