Synthesis Messages

Report Title	GowinSynthesis Report
Design File	/home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_1P5/EXAMPLE CODE/Button_filtering_counterl_Led/src/key_filter.v /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_1P5/EXAMPLE CODE/Button_filtering_counterl_Led/src/key_led_top.v /home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_1P5/EXAMPLE CODE/Button_filtering_counterl_Led/src/led_ctrl.v
GowinSynthesis Constraints File	---
Tool Version	V1.9.11
Part Number	GW1N-UV1P5QN48XFC7/I6
Device	GW1N-1P5
Device Version	C
Created Time	Fri Mar 7 22:44:26 2025
Legal Announcement	Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module	key_led_top
Synthesis Process	Running parser:     CPU time = 0h 0m 0.056s, Elapsed time = 0h 0m 0.048s, Peak memory usage = 311.227MB Running netlist conversion:     CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization:     Optimizing Phase 0: CPU time = 0h 0m 0.002s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 311.227MB     Optimizing Phase 1: CPU time = 0h 0m 0.002s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 311.227MB     Optimizing Phase 2: CPU time = 0h 0m 0.006s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 311.227MB Running inference:     Inferring Phase 0: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0s, Peak memory usage = 311.227MB     Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 311.227MB     Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 311.227MB     Inferring Phase 3: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0s, Peak memory usage = 311.227MB Running technical mapping:     Tech-Mapping Phase 0: CPU time = 0h 0m 0.005s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 311.227MB     Tech-Mapping Phase 1: CPU time = 0h 0m 0.002s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 311.227MB     Tech-Mapping Phase 2: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0s, Peak memory usage = 311.227MB     Tech-Mapping Phase 3: CPU time = 0h 0m 0.441s, Elapsed time = 0h 0m 0.434s, Peak memory usage = 311.227MB     Tech-Mapping Phase 4: CPU time = 0h 0m 0.075s, Elapsed time = 0h 0m 0.073s, Peak memory usage = 311.227MB Generate output files:     CPU time = 0h 0m 0.033s, Elapsed time = 0h 0m 0.031s, Peak memory usage = 311.227MB
Total Time and Memory Usage	CPU time = 0h 0m 0.625s, Elapsed time = 0h 0m 0.595s, Peak memory usage = 311.227MB

Resource

Resource Usage Summary

Resource	Usage
I/O Port	6
I/O Buf	6
IBUF	4
OBUF	2
Register	66
DFFP	4
DFFC	54
DFFCE	8
LUT	108
LUT2	10
LUT3	31
LUT4	67
INV	2
INV	2

Resource Utilization Summary

Resource	Usage	Utilization
Logic	110(110 LUT, 0 ALU) / 1584	7%
Register	66 / 1704	4%
--Register as Latch	0 / 1704	0%
--Register as FF	66 / 1704	4%
BSRAM	0 / 4	0%

Timing

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Object
1	Clk	Base	20.000	50.000	0.000	10.000			Clk_ibuf/I

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	Clk	50.000(MHz)	168.789(MHz)	4	TOP

Detail Timing Paths Information

Path 1

Path Summary:

Slack	14.075
Data Arrival Time	6.166
Data Required Time	20.242
From	key_filter1/cnt_5_s0
To	key_filter1/cnt_9_s0
Launch Clk	Clk[R]
Latch Clk	Clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				Clk
0.000	0.000	tCL	RR	1	Clk_ibuf/I
0.000	0.000	tINS	RR	66	Clk_ibuf/O
0.538	0.538	tNET	RR	1	key_filter1/cnt_5_s0/CLK
0.878	0.340	tC2Q	RF	3	key_filter1/cnt_5_s0/Q
1.589	0.711	tNET	FF	1	key_filter1/n103_s3/I1
2.403	0.814	tINS	FF	4	key_filter1/n103_s3/F
3.115	0.711	tNET	FF	1	key_filter1/n103_s2/I1
3.929	0.814	tINS	FF	2	key_filter1/n103_s2/F
4.640	0.711	tNET	FF	1	key_filter1/n102_s1/I1
5.455	0.814	tINS	FF	1	key_filter1/n102_s1/F
6.166	0.711	tNET	FF	1	key_filter1/cnt_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	0.000				Clk
20.000	0.000	tCL	RR	1	Clk_ibuf/I
20.000	0.000	tINS	RR	66	Clk_ibuf/O
20.538	0.538	tNET	RR	1	key_filter1/cnt_9_s0/CLK
20.242	-0.296	tSu		1	key_filter1/cnt_9_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	4
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay:	cell: 2.443, 43.408%; route: 2.845, 50.558%; tC2Q: 0.340, 6.034%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 2

Path Summary:

Slack	14.075
Data Arrival Time	6.166
Data Required Time	20.242
From	key_filter1/cnt_1_s0
To	key_filter1/cnt_13_s0
Launch Clk	Clk[R]
Latch Clk	Clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				Clk
0.000	0.000	tCL	RR	1	Clk_ibuf/I
0.000	0.000	tINS	RR	66	Clk_ibuf/O
0.538	0.538	tNET	RR	1	key_filter1/cnt_1_s0/CLK
0.878	0.340	tC2Q	RF	4	key_filter1/cnt_1_s0/Q
1.589	0.711	tNET	FF	1	key_filter1/n107_s2/I1
2.403	0.814	tINS	FF	7	key_filter1/n107_s2/F
3.115	0.711	tNET	FF	1	key_filter1/n98_s2/I1
3.929	0.814	tINS	FF	7	key_filter1/n98_s2/F
4.640	0.711	tNET	FF	1	key_filter1/n98_s1/I1
5.455	0.814	tINS	FF	1	key_filter1/n98_s1/F
6.166	0.711	tNET	FF	1	key_filter1/cnt_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	0.000				Clk
20.000	0.000	tCL	RR	1	Clk_ibuf/I
20.000	0.000	tINS	RR	66	Clk_ibuf/O
20.538	0.538	tNET	RR	1	key_filter1/cnt_13_s0/CLK
20.242	-0.296	tSu		1	key_filter1/cnt_13_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	4
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay:	cell: 2.443, 43.408%; route: 2.845, 50.558%; tC2Q: 0.340, 6.034%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 3

Path Summary:

Slack	14.075
Data Arrival Time	6.166
Data Required Time	20.242
From	key_filter1/cnt_1_s0
To	key_filter1/cnt_14_s0
Launch Clk	Clk[R]
Latch Clk	Clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				Clk
0.000	0.000	tCL	RR	1	Clk_ibuf/I
0.000	0.000	tINS	RR	66	Clk_ibuf/O
0.538	0.538	tNET	RR	1	key_filter1/cnt_1_s0/CLK
0.878	0.340	tC2Q	RF	4	key_filter1/cnt_1_s0/Q
1.589	0.711	tNET	FF	1	key_filter1/n107_s2/I1
2.403	0.814	tINS	FF	7	key_filter1/n107_s2/F
3.115	0.711	tNET	FF	1	key_filter1/n98_s2/I1
3.929	0.814	tINS	FF	7	key_filter1/n98_s2/F
4.640	0.711	tNET	FF	1	key_filter1/n97_s1/I1
5.455	0.814	tINS	FF	1	key_filter1/n97_s1/F
6.166	0.711	tNET	FF	1	key_filter1/cnt_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	0.000				Clk
20.000	0.000	tCL	RR	1	Clk_ibuf/I
20.000	0.000	tINS	RR	66	Clk_ibuf/O
20.538	0.538	tNET	RR	1	key_filter1/cnt_14_s0/CLK
20.242	-0.296	tSu		1	key_filter1/cnt_14_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	4
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay:	cell: 2.443, 43.408%; route: 2.845, 50.558%; tC2Q: 0.340, 6.034%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 4

Path Summary:

Slack	14.075
Data Arrival Time	6.166
Data Required Time	20.242
From	key_filter1/cnt_14_s0
To	key_filter1/cnt_18_s0
Launch Clk	Clk[R]
Latch Clk	Clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				Clk
0.000	0.000	tCL	RR	1	Clk_ibuf/I
0.000	0.000	tINS	RR	66	Clk_ibuf/O
0.538	0.538	tNET	RR	1	key_filter1/cnt_14_s0/CLK
0.878	0.340	tC2Q	RF	5	key_filter1/cnt_14_s0/Q
1.589	0.711	tNET	FF	1	key_filter1/n94_s2/I1
2.403	0.814	tINS	FF	3	key_filter1/n94_s2/F
3.115	0.711	tNET	FF	1	key_filter1/n93_s2/I1
3.929	0.814	tINS	FF	1	key_filter1/n93_s2/F
4.640	0.711	tNET	FF	1	key_filter1/n93_s1/I1
5.455	0.814	tINS	FF	1	key_filter1/n93_s1/F
6.166	0.711	tNET	FF	1	key_filter1/cnt_18_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	0.000				Clk
20.000	0.000	tCL	RR	1	Clk_ibuf/I
20.000	0.000	tINS	RR	66	Clk_ibuf/O
20.538	0.538	tNET	RR	1	key_filter1/cnt_18_s0/CLK
20.242	-0.296	tSu		1	key_filter1/cnt_18_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	4
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay:	cell: 2.443, 43.408%; route: 2.845, 50.558%; tC2Q: 0.340, 6.034%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 5

Path Summary:

Slack	14.075
Data Arrival Time	6.166
Data Required Time	20.242
From	key_filter0/cnt_5_s0
To	key_filter0/cnt_9_s0
Launch Clk	Clk[R]
Latch Clk	Clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				Clk
0.000	0.000	tCL	RR	1	Clk_ibuf/I
0.000	0.000	tINS	RR	66	Clk_ibuf/O
0.538	0.538	tNET	RR	1	key_filter0/cnt_5_s0/CLK
0.878	0.340	tC2Q	RF	3	key_filter0/cnt_5_s0/Q
1.589	0.711	tNET	FF	1	key_filter0/n92_s5/I1
2.403	0.814	tINS	FF	4	key_filter0/n92_s5/F
3.115	0.711	tNET	FF	1	key_filter0/n100_s3/I1
3.929	0.814	tINS	FF	3	key_filter0/n100_s3/F
4.640	0.711	tNET	FF	1	key_filter0/n102_s1/I1
5.455	0.814	tINS	FF	1	key_filter0/n102_s1/F
6.166	0.711	tNET	FF	1	key_filter0/cnt_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	0.000				Clk
20.000	0.000	tCL	RR	1	Clk_ibuf/I
20.000	0.000	tINS	RR	66	Clk_ibuf/O
20.538	0.538	tNET	RR	1	key_filter0/cnt_9_s0/CLK
20.242	-0.296	tSu		1	key_filter0/cnt_9_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	4
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay:	cell: 2.443, 43.408%; route: 2.845, 50.558%; tC2Q: 0.340, 6.034%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%