Timing Messages

Report Title	Timing Analysis Report
Design File	C:\Users\ADMIN\Desktop\onekiwi_fpga_board-main\fpga_1P5\EXAMPLE CODE\UART_transmit_receive_multiple_byte\impl\gwsynthesis\uart_loopback.vg
Physical Constraints File	C:\Users\ADMIN\Desktop\onekiwi_fpga_board-main\fpga_1P5\EXAMPLE CODE\UART_transmit_receive_multiple_byte\src\uart_loopback.cst
Timing Constraint File	---
Tool Version	V1.9.11.03 (64-bit)
Part Number	GW1N-UV1P5QN48XFC7/I6
Device	GW1N-1P5
Device Version	C
Created Time	Wed Jul 30 11:57:27 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 1.71V 85C C7/I6
Hold Delay Model	Fast 3.6V 0C C7/I6
Numbers of Paths Analyzed	695
Numbers of Endpoints Analyzed	652
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	Clk	Base	20.000	50.000	0.000	10.000			Clk_ibuf/I

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	Clk	50.000(MHz)	136.567(MHz)	5	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
Clk	Setup	0.000	0
Clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	12.678	uart_data_rx/uart_byte_rx/bps_cnt_6_s1/Q	uart_data_rx/uart_byte_rx/data_byte_pre[6]_1_s0/CE	Clk:[R]	Clk:[R]	20.000	0.000	7.290
2	12.678	uart_data_rx/uart_byte_rx/bps_cnt_6_s1/Q	uart_data_rx/uart_byte_rx/data_byte_pre[6]_2_s0/CE	Clk:[R]	Clk:[R]	20.000	0.000	7.290
3	12.943	uart_data_rx/uart_byte_rx/bps_cnt_2_s1/Q	uart_data_rx/uart_byte_rx/bps_cnt_0_s1/CE	Clk:[R]	Clk:[R]	20.000	0.000	7.025
4	12.943	uart_data_rx/uart_byte_rx/bps_cnt_2_s1/Q	uart_data_rx/uart_byte_rx/bps_cnt_3_s1/CE	Clk:[R]	Clk:[R]	20.000	0.000	7.025
5	12.943	uart_data_rx/uart_byte_rx/bps_cnt_2_s1/Q	uart_data_rx/uart_byte_rx/bps_cnt_6_s1/CE	Clk:[R]	Clk:[R]	20.000	0.000	7.025
6	12.943	uart_data_rx/uart_byte_rx/bps_cnt_2_s1/Q	uart_data_rx/uart_byte_rx/bps_cnt_7_s1/CE	Clk:[R]	Clk:[R]	20.000	0.000	7.025
7	12.946	uart_data_rx/uart_byte_rx/bps_cnt_2_s1/Q	uart_data_rx/uart_byte_rx/bps_cnt_2_s1/CE	Clk:[R]	Clk:[R]	20.000	0.000	7.022
8	12.950	uart_data_rx/uart_byte_rx/bps_cnt_6_s1/Q	uart_data_rx/uart_byte_rx/data_byte_pre[6]_0_s0/CE	Clk:[R]	Clk:[R]	20.000	0.000	7.018
9	13.138	uart_data_rx/timeout_cnt_8_s0/Q	uart_data_rx/timeout_flag_s1/CE	Clk:[R]	Clk:[R]	20.000	0.000	6.830
10	13.219	uart_data_rx/uart_byte_rx/bps_cnt_2_s1/Q	uart_data_rx/uart_byte_rx/bps_cnt_1_s1/CE	Clk:[R]	Clk:[R]	20.000	0.000	6.749
11	13.219	uart_data_rx/uart_byte_rx/bps_cnt_2_s1/Q	uart_data_rx/uart_byte_rx/bps_cnt_4_s1/CE	Clk:[R]	Clk:[R]	20.000	0.000	6.749
12	13.552	uart_data_rx/uart_byte_rx/bps_cnt_2_s1/Q	uart_data_rx/uart_byte_rx/bps_cnt_5_s1/CE	Clk:[R]	Clk:[R]	20.000	0.000	6.416
13	13.892	uart_data_rx/timeout_cnt_8_s0/Q	uart_data_rx/timeout_cnt_0_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	5.812
14	13.892	uart_data_rx/timeout_cnt_8_s0/Q	uart_data_rx/timeout_cnt_11_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	5.812
15	13.929	uart_data_rx/uart_byte_rx/bps_cnt_6_s1/Q	uart_data_rx/uart_byte_rx/STOP_BIT_0_s0/CE	Clk:[R]	Clk:[R]	20.000	0.000	6.039
16	13.929	uart_data_rx/uart_byte_rx/bps_cnt_6_s1/Q	uart_data_rx/uart_byte_rx/STOP_BIT_1_s0/CE	Clk:[R]	Clk:[R]	20.000	0.000	6.039
17	13.929	uart_data_rx/uart_byte_rx/bps_cnt_6_s1/Q	uart_data_rx/uart_byte_rx/STOP_BIT_2_s0/CE	Clk:[R]	Clk:[R]	20.000	0.000	6.039
18	13.990	uart_data_rx/timeout_cnt_8_s0/Q	uart_data_rx/timeout_cnt_10_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	5.714
19	13.991	uart_data_rx/uart_byte_rx/bps_cnt_2_s1/Q	uart_data_rx/uart_byte_rx/uart_state_s1/CE	Clk:[R]	Clk:[R]	20.000	0.000	5.977
20	13.992	uart_data_rx/timeout_cnt_8_s0/Q	uart_data_rx/timeout_cnt_16_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	5.711
21	13.997	uart_data_rx/timeout_cnt_8_s0/Q	uart_data_rx/timeout_cnt_1_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	5.706
22	14.000	uart_data_rx/timeout_cnt_8_s0/Q	uart_data_rx/timeout_flag_s1/D	Clk:[R]	Clk:[R]	20.000	0.000	5.703
23	14.039	uart_data_rx/timeout_cnt_8_s0/Q	uart_data_rx/timeout_cnt_7_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	5.664
24	14.039	uart_data_rx/timeout_cnt_8_s0/Q	uart_data_rx/timeout_cnt_9_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	5.664
25	14.050	uart_data_rx/timeout_cnt_8_s0/Q	uart_data_rx/timeout_cnt_5_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	5.654

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.524	uart_data_tx/uart_byte_tx/div_cnt_3_s0/Q	uart_data_tx/uart_byte_tx/div_cnt_3_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.524
2	0.524	uart_data_tx/uart_byte_tx/div_cnt_14_s0/Q	uart_data_tx/uart_byte_tx/div_cnt_14_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.524
3	0.524	uart_data_tx/byte_send_en_s4/Q	uart_data_tx/byte_send_en_s4/D	Clk:[R]	Clk:[R]	0.000	0.000	0.524
4	0.524	uart_data_tx/data_byte_7_s2/Q	uart_data_tx/data_byte_7_s2/D	Clk:[R]	Clk:[R]	0.000	0.000	0.524
5	0.524	uart_data_tx/data_byte_0_s2/Q	uart_data_tx/data_byte_0_s2/D	Clk:[R]	Clk:[R]	0.000	0.000	0.524
6	0.524	uart_data_tx/data_byte_2_s2/Q	uart_data_tx/data_byte_2_s2/D	Clk:[R]	Clk:[R]	0.000	0.000	0.524
7	0.524	uart_data_tx/data_byte_6_s3/Q	uart_data_tx/data_byte_6_s3/D	Clk:[R]	Clk:[R]	0.000	0.000	0.524
8	0.524	uart_data_tx/cnt_7_s1/Q	uart_data_tx/cnt_7_s1/D	Clk:[R]	Clk:[R]	0.000	0.000	0.524
9	0.524	uart_data_rx/uart_byte_rx/STOP_BIT_2_s0/Q	uart_data_rx/uart_byte_rx/STOP_BIT_2_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.524
10	0.524	uart_data_rx/uart_byte_rx/data_byte_pre[0]_2_s0/Q	uart_data_rx/uart_byte_rx/data_byte_pre[0]_2_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.524
11	0.524	uart_data_rx/uart_byte_rx/data_byte_pre[2]_1_s0/Q	uart_data_rx/uart_byte_rx/data_byte_pre[2]_1_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.524
12	0.524	uart_data_rx/uart_byte_rx/data_byte_pre[3]_1_s0/Q	uart_data_rx/uart_byte_rx/data_byte_pre[3]_1_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.524
13	0.524	uart_data_rx/uart_byte_rx/data_byte_pre[5]_0_s0/Q	uart_data_rx/uart_byte_rx/data_byte_pre[5]_0_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.524
14	0.524	uart_data_rx/uart_byte_rx/data_byte_pre[5]_2_s0/Q	uart_data_rx/uart_byte_rx/data_byte_pre[5]_2_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.524
15	0.524	uart_data_rx/uart_byte_rx/START_BIT_2_s0/Q	uart_data_rx/uart_byte_rx/START_BIT_2_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.524
16	0.524	uart_data_rx/uart_byte_rx/div_cnt_7_s0/Q	uart_data_rx/uart_byte_rx/div_cnt_7_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.524
17	0.524	uart_data_rx/uart_byte_rx/div_cnt_9_s0/Q	uart_data_rx/uart_byte_rx/div_cnt_9_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.524
18	0.524	uart_data_rx/uart_byte_rx/div_cnt_14_s0/Q	uart_data_rx/uart_byte_rx/div_cnt_14_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.524
19	0.524	uart_data_rx/uart_byte_rx/div_cnt_15_s0/Q	uart_data_rx/uart_byte_rx/div_cnt_15_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.524
20	0.524	uart_data_rx/state_1_s2/Q	uart_data_rx/state_1_s2/D	Clk:[R]	Clk:[R]	0.000	0.000	0.524
21	0.524	uart_data_rx/to_state_s4/Q	uart_data_rx/to_state_s4/D	Clk:[R]	Clk:[R]	0.000	0.000	0.524
22	0.524	uart_data_rx/timeout_cnt_2_s0/Q	uart_data_rx/timeout_cnt_2_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.524
23	0.524	uart_data_rx/timeout_cnt_17_s0/Q	uart_data_rx/timeout_cnt_17_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.524
24	0.525	uart_data_tx/uart_byte_tx/div_cnt_1_s0/Q	uart_data_tx/uart_byte_tx/div_cnt_1_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.525
25	0.525	uart_data_tx/uart_byte_tx/div_cnt_9_s0/Q	uart_data_tx/uart_byte_tx/div_cnt_9_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.525

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	6.948	7.874	0.926	High Pulse Width	Clk	uart_data_rx/timeout_cnt_17_s0
2	6.948	7.874	0.926	High Pulse Width	Clk	uart_data_rx/timeout_cnt_16_s0
3	6.948	7.874	0.926	High Pulse Width	Clk	uart_data_rx/timeout_cnt_14_s0
4	6.948	7.874	0.926	High Pulse Width	Clk	uart_data_rx/timeout_cnt_10_s0
5	6.948	7.874	0.926	High Pulse Width	Clk	uart_data_rx/timeout_cnt_2_s0
6	6.948	7.874	0.926	High Pulse Width	Clk	uart_data_rx/data_r_18_s0
7	6.948	7.874	0.926	High Pulse Width	Clk	uart_data_rx/data_18_s0
8	6.948	7.874	0.926	High Pulse Width	Clk	uart_data_rx/uart_byte_rx/data_byte_pre[4]_1_s0
9	6.948	7.874	0.926	High Pulse Width	Clk	uart_data_rx/uart_byte_rx/data_byte_pre[4]_2_s0
10	6.948	7.874	0.926	High Pulse Width	Clk	uart_data_rx/data_19_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	12.678
Data Arrival Time	11.701
Data Required Time	24.378
From	uart_data_rx/uart_byte_rx/bps_cnt_6_s1
To	uart_data_rx/uart_byte_rx/data_byte_pre[6]_1_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R5C11[0][B]	uart_data_rx/uart_byte_rx/bps_cnt_6_s1/CLK
4.750	0.340	tC2Q	RF	15	R5C11[0][B]	uart_data_rx/uart_byte_rx/bps_cnt_6_s1/Q
5.128	0.378	tNET	FF	1	R6C11[3][A]	uart_data_rx/uart_byte_rx/START_BIT_2_s5/I1
5.893	0.765	tINS	FF	1	R6C11[3][A]	uart_data_rx/uart_byte_rx/START_BIT_2_s5/F
5.897	0.004	tNET	FF	1	R6C11[3][B]	uart_data_rx/uart_byte_rx/bps_cnt_7_s5/I3
6.491	0.594	tINS	FR	3	R6C11[3][B]	uart_data_rx/uart_byte_rx/bps_cnt_7_s5/F
6.808	0.316	tNET	RR	1	R5C11[3][B]	uart_data_rx/uart_byte_rx/START_BIT_2_s3/I2
7.572	0.765	tINS	RF	10	R5C11[3][B]	uart_data_rx/uart_byte_rx/START_BIT_2_s3/F
9.515	1.943	tNET	FF	1	R9C14[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[6]_2_s2/I1
10.301	0.786	tINS	FR	3	R9C14[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[6]_2_s2/F
11.701	1.400	tNET	RR	1	R9C12[2][B]	uart_data_rx/uart_byte_rx/data_byte_pre[6]_1_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R9C12[2][B]	uart_data_rx/uart_byte_rx/data_byte_pre[6]_1_s0/CLK
24.378	-0.032	tSu		1	R9C12[2][B]	uart_data_rx/uart_byte_rx/data_byte_pre[6]_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.910, 39.915%; route: 4.041, 55.426%; tC2Q: 0.340, 4.659%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path2

Path Summary:

Slack	12.678
Data Arrival Time	11.701
Data Required Time	24.378
From	uart_data_rx/uart_byte_rx/bps_cnt_6_s1
To	uart_data_rx/uart_byte_rx/data_byte_pre[6]_2_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R5C11[0][B]	uart_data_rx/uart_byte_rx/bps_cnt_6_s1/CLK
4.750	0.340	tC2Q	RF	15	R5C11[0][B]	uart_data_rx/uart_byte_rx/bps_cnt_6_s1/Q
5.128	0.378	tNET	FF	1	R6C11[3][A]	uart_data_rx/uart_byte_rx/START_BIT_2_s5/I1
5.893	0.765	tINS	FF	1	R6C11[3][A]	uart_data_rx/uart_byte_rx/START_BIT_2_s5/F
5.897	0.004	tNET	FF	1	R6C11[3][B]	uart_data_rx/uart_byte_rx/bps_cnt_7_s5/I3
6.491	0.594	tINS	FR	3	R6C11[3][B]	uart_data_rx/uart_byte_rx/bps_cnt_7_s5/F
6.808	0.316	tNET	RR	1	R5C11[3][B]	uart_data_rx/uart_byte_rx/START_BIT_2_s3/I2
7.572	0.765	tINS	RF	10	R5C11[3][B]	uart_data_rx/uart_byte_rx/START_BIT_2_s3/F
9.515	1.943	tNET	FF	1	R9C14[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[6]_2_s2/I1
10.301	0.786	tINS	FR	3	R9C14[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[6]_2_s2/F
11.701	1.400	tNET	RR	1	R9C12[2][A]	uart_data_rx/uart_byte_rx/data_byte_pre[6]_2_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R9C12[2][A]	uart_data_rx/uart_byte_rx/data_byte_pre[6]_2_s0/CLK
24.378	-0.032	tSu		1	R9C12[2][A]	uart_data_rx/uart_byte_rx/data_byte_pre[6]_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.910, 39.915%; route: 4.041, 55.426%; tC2Q: 0.340, 4.659%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path3

Path Summary:

Slack	12.943
Data Arrival Time	11.436
Data Required Time	24.378
From	uart_data_rx/uart_byte_rx/bps_cnt_2_s1
To	uart_data_rx/uart_byte_rx/bps_cnt_0_s1
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R6C11[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_2_s1/CLK
4.750	0.340	tC2Q	RF	9	R6C11[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_2_s1/Q
5.717	0.967	tNET	FF	1	R6C13[1][B]	uart_data_rx/uart_byte_rx/n152_s3/I0
6.477	0.760	tINS	FR	1	R6C13[1][B]	uart_data_rx/uart_byte_rx/n152_s3/F
6.788	0.310	tNET	RR	1	R6C12[0][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s6/I3
7.397	0.609	tINS	RF	2	R6C12[0][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s6/F
7.996	0.599	tNET	FF	1	R5C11[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s4/I1
8.811	0.814	tINS	FF	4	R5C11[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s4/F
9.789	0.979	tNET	FF	1	R6C13[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s3/I3
10.576	0.786	tINS	FR	8	R6C13[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s3/F
11.436	0.860	tNET	RR	1	R5C11[1][B]	uart_data_rx/uart_byte_rx/bps_cnt_0_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R5C11[1][B]	uart_data_rx/uart_byte_rx/bps_cnt_0_s1/CLK
24.378	-0.032	tSu		1	R5C11[1][B]	uart_data_rx/uart_byte_rx/bps_cnt_0_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.970, 42.276%; route: 3.715, 52.889%; tC2Q: 0.340, 4.834%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path4

Path Summary:

Slack	12.943
Data Arrival Time	11.436
Data Required Time	24.378
From	uart_data_rx/uart_byte_rx/bps_cnt_2_s1
To	uart_data_rx/uart_byte_rx/bps_cnt_3_s1
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R6C11[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_2_s1/CLK
4.750	0.340	tC2Q	RF	9	R6C11[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_2_s1/Q
5.717	0.967	tNET	FF	1	R6C13[1][B]	uart_data_rx/uart_byte_rx/n152_s3/I0
6.477	0.760	tINS	FR	1	R6C13[1][B]	uart_data_rx/uart_byte_rx/n152_s3/F
6.788	0.310	tNET	RR	1	R6C12[0][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s6/I3
7.397	0.609	tINS	RF	2	R6C12[0][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s6/F
7.996	0.599	tNET	FF	1	R5C11[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s4/I1
8.811	0.814	tINS	FF	4	R5C11[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s4/F
9.789	0.979	tNET	FF	1	R6C13[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s3/I3
10.576	0.786	tINS	FR	8	R6C13[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s3/F
11.436	0.860	tNET	RR	1	R5C11[0][A]	uart_data_rx/uart_byte_rx/bps_cnt_3_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R5C11[0][A]	uart_data_rx/uart_byte_rx/bps_cnt_3_s1/CLK
24.378	-0.032	tSu		1	R5C11[0][A]	uart_data_rx/uart_byte_rx/bps_cnt_3_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.970, 42.276%; route: 3.715, 52.889%; tC2Q: 0.340, 4.834%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path5

Path Summary:

Slack	12.943
Data Arrival Time	11.436
Data Required Time	24.378
From	uart_data_rx/uart_byte_rx/bps_cnt_2_s1
To	uart_data_rx/uart_byte_rx/bps_cnt_6_s1
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R6C11[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_2_s1/CLK
4.750	0.340	tC2Q	RF	9	R6C11[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_2_s1/Q
5.717	0.967	tNET	FF	1	R6C13[1][B]	uart_data_rx/uart_byte_rx/n152_s3/I0
6.477	0.760	tINS	FR	1	R6C13[1][B]	uart_data_rx/uart_byte_rx/n152_s3/F
6.788	0.310	tNET	RR	1	R6C12[0][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s6/I3
7.397	0.609	tINS	RF	2	R6C12[0][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s6/F
7.996	0.599	tNET	FF	1	R5C11[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s4/I1
8.811	0.814	tINS	FF	4	R5C11[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s4/F
9.789	0.979	tNET	FF	1	R6C13[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s3/I3
10.576	0.786	tINS	FR	8	R6C13[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s3/F
11.436	0.860	tNET	RR	1	R5C11[0][B]	uart_data_rx/uart_byte_rx/bps_cnt_6_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R5C11[0][B]	uart_data_rx/uart_byte_rx/bps_cnt_6_s1/CLK
24.378	-0.032	tSu		1	R5C11[0][B]	uart_data_rx/uart_byte_rx/bps_cnt_6_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.970, 42.276%; route: 3.715, 52.889%; tC2Q: 0.340, 4.834%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path6

Path Summary:

Slack	12.943
Data Arrival Time	11.436
Data Required Time	24.378
From	uart_data_rx/uart_byte_rx/bps_cnt_2_s1
To	uart_data_rx/uart_byte_rx/bps_cnt_7_s1
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R6C11[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_2_s1/CLK
4.750	0.340	tC2Q	RF	9	R6C11[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_2_s1/Q
5.717	0.967	tNET	FF	1	R6C13[1][B]	uart_data_rx/uart_byte_rx/n152_s3/I0
6.477	0.760	tINS	FR	1	R6C13[1][B]	uart_data_rx/uart_byte_rx/n152_s3/F
6.788	0.310	tNET	RR	1	R6C12[0][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s6/I3
7.397	0.609	tINS	RF	2	R6C12[0][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s6/F
7.996	0.599	tNET	FF	1	R5C11[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s4/I1
8.811	0.814	tINS	FF	4	R5C11[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s4/F
9.789	0.979	tNET	FF	1	R6C13[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s3/I3
10.576	0.786	tINS	FR	8	R6C13[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s3/F
11.436	0.860	tNET	RR	1	R5C11[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R5C11[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s1/CLK
24.378	-0.032	tSu		1	R5C11[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.970, 42.276%; route: 3.715, 52.889%; tC2Q: 0.340, 4.834%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path7

Path Summary:

Slack	12.946
Data Arrival Time	11.432
Data Required Time	24.378
From	uart_data_rx/uart_byte_rx/bps_cnt_2_s1
To	uart_data_rx/uart_byte_rx/bps_cnt_2_s1
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R6C11[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_2_s1/CLK
4.750	0.340	tC2Q	RF	9	R6C11[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_2_s1/Q
5.717	0.967	tNET	FF	1	R6C13[1][B]	uart_data_rx/uart_byte_rx/n152_s3/I0
6.477	0.760	tINS	FR	1	R6C13[1][B]	uart_data_rx/uart_byte_rx/n152_s3/F
6.788	0.310	tNET	RR	1	R6C12[0][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s6/I3
7.397	0.609	tINS	RF	2	R6C12[0][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s6/F
7.996	0.599	tNET	FF	1	R5C11[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s4/I1
8.811	0.814	tINS	FF	4	R5C11[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s4/F
9.789	0.979	tNET	FF	1	R6C13[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s3/I3
10.576	0.786	tINS	FR	8	R6C13[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s3/F
11.432	0.857	tNET	RR	1	R6C11[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_2_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R6C11[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_2_s1/CLK
24.378	-0.032	tSu		1	R6C11[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_2_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.970, 42.297%; route: 3.712, 52.866%; tC2Q: 0.340, 4.837%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path8

Path Summary:

Slack	12.950
Data Arrival Time	11.428
Data Required Time	24.378
From	uart_data_rx/uart_byte_rx/bps_cnt_6_s1
To	uart_data_rx/uart_byte_rx/data_byte_pre[6]_0_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R5C11[0][B]	uart_data_rx/uart_byte_rx/bps_cnt_6_s1/CLK
4.750	0.340	tC2Q	RF	15	R5C11[0][B]	uart_data_rx/uart_byte_rx/bps_cnt_6_s1/Q
5.128	0.378	tNET	FF	1	R6C11[3][A]	uart_data_rx/uart_byte_rx/START_BIT_2_s5/I1
5.893	0.765	tINS	FF	1	R6C11[3][A]	uart_data_rx/uart_byte_rx/START_BIT_2_s5/F
5.897	0.004	tNET	FF	1	R6C11[3][B]	uart_data_rx/uart_byte_rx/bps_cnt_7_s5/I3
6.491	0.594	tINS	FR	3	R6C11[3][B]	uart_data_rx/uart_byte_rx/bps_cnt_7_s5/F
6.808	0.316	tNET	RR	1	R5C11[3][B]	uart_data_rx/uart_byte_rx/START_BIT_2_s3/I2
7.572	0.765	tINS	RF	10	R5C11[3][B]	uart_data_rx/uart_byte_rx/START_BIT_2_s3/F
9.515	1.943	tNET	FF	1	R9C14[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[6]_2_s2/I1
10.301	0.786	tINS	FR	3	R9C14[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[6]_2_s2/F
11.428	1.128	tNET	RR	1	R9C14[1][B]	uart_data_rx/uart_byte_rx/data_byte_pre[6]_0_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R9C14[1][B]	uart_data_rx/uart_byte_rx/data_byte_pre[6]_0_s0/CLK
24.378	-0.032	tSu		1	R9C14[1][B]	uart_data_rx/uart_byte_rx/data_byte_pre[6]_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.910, 41.464%; route: 3.768, 53.696%; tC2Q: 0.340, 4.839%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path9

Path Summary:

Slack	13.138
Data Arrival Time	11.241
Data Required Time	24.378
From	uart_data_rx/timeout_cnt_8_s0
To	uart_data_rx/timeout_flag_s1
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R11C14[2][A]	uart_data_rx/timeout_cnt_8_s0/CLK
4.750	0.340	tC2Q	RF	5	R11C14[2][A]	uart_data_rx/timeout_cnt_8_s0/Q
5.610	0.860	tNET	FF	1	R12C15[3][B]	uart_data_rx/n98_s103/I1
6.219	0.609	tINS	FF	1	R12C15[3][B]	uart_data_rx/n98_s103/F
6.582	0.363	tNET	FF	1	R12C14[3][A]	uart_data_rx/n98_s98/I3
7.343	0.760	tINS	FR	1	R12C14[3][A]	uart_data_rx/n98_s98/F
7.653	0.310	tNET	RR	1	R12C13[3][B]	uart_data_rx/n98_s109/I0
8.418	0.765	tINS	RF	19	R12C13[3][B]	uart_data_rx/n98_s109/F
9.650	1.232	tNET	FF	1	R11C10[1][A]	uart_data_rx/timeout_flag_s3/I2
10.113	0.463	tINS	FR	1	R11C10[1][A]	uart_data_rx/timeout_flag_s3/F
11.241	1.128	tNET	RR	1	R11C10[1][B]	uart_data_rx/timeout_flag_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R11C10[1][B]	uart_data_rx/timeout_flag_s1/CLK
24.378	-0.032	tSu		1	R11C10[1][B]	uart_data_rx/timeout_flag_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.597, 38.025%; route: 3.893, 57.002%; tC2Q: 0.340, 4.972%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path10

Path Summary:

Slack	13.219
Data Arrival Time	11.160
Data Required Time	24.378
From	uart_data_rx/uart_byte_rx/bps_cnt_2_s1
To	uart_data_rx/uart_byte_rx/bps_cnt_1_s1
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R6C11[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_2_s1/CLK
4.750	0.340	tC2Q	RF	9	R6C11[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_2_s1/Q
5.717	0.967	tNET	FF	1	R6C13[1][B]	uart_data_rx/uart_byte_rx/n152_s3/I0
6.477	0.760	tINS	FR	1	R6C13[1][B]	uart_data_rx/uart_byte_rx/n152_s3/F
6.788	0.310	tNET	RR	1	R6C12[0][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s6/I3
7.397	0.609	tINS	RF	2	R6C12[0][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s6/F
7.996	0.599	tNET	FF	1	R5C11[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s4/I1
8.811	0.814	tINS	FF	4	R5C11[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s4/F
9.789	0.979	tNET	FF	1	R6C13[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s3/I3
10.576	0.786	tINS	FR	8	R6C13[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s3/F
11.160	0.584	tNET	RR	1	R7C12[1][B]	uart_data_rx/uart_byte_rx/bps_cnt_1_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R7C12[1][B]	uart_data_rx/uart_byte_rx/bps_cnt_1_s1/CLK
24.378	-0.032	tSu		1	R7C12[1][B]	uart_data_rx/uart_byte_rx/bps_cnt_1_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.970, 44.004%; route: 3.440, 50.964%; tC2Q: 0.340, 5.032%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path11

Path Summary:

Slack	13.219
Data Arrival Time	11.160
Data Required Time	24.378
From	uart_data_rx/uart_byte_rx/bps_cnt_2_s1
To	uart_data_rx/uart_byte_rx/bps_cnt_4_s1
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R6C11[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_2_s1/CLK
4.750	0.340	tC2Q	RF	9	R6C11[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_2_s1/Q
5.717	0.967	tNET	FF	1	R6C13[1][B]	uart_data_rx/uart_byte_rx/n152_s3/I0
6.477	0.760	tINS	FR	1	R6C13[1][B]	uart_data_rx/uart_byte_rx/n152_s3/F
6.788	0.310	tNET	RR	1	R6C12[0][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s6/I3
7.397	0.609	tINS	RF	2	R6C12[0][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s6/F
7.996	0.599	tNET	FF	1	R5C11[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s4/I1
8.811	0.814	tINS	FF	4	R5C11[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s4/F
9.789	0.979	tNET	FF	1	R6C13[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s3/I3
10.576	0.786	tINS	FR	8	R6C13[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s3/F
11.160	0.584	tNET	RR	1	R7C12[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_4_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R7C12[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_4_s1/CLK
24.378	-0.032	tSu		1	R7C12[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_4_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.970, 44.004%; route: 3.440, 50.964%; tC2Q: 0.340, 5.032%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path12

Path Summary:

Slack	13.552
Data Arrival Time	10.826
Data Required Time	24.378
From	uart_data_rx/uart_byte_rx/bps_cnt_2_s1
To	uart_data_rx/uart_byte_rx/bps_cnt_5_s1
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R6C11[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_2_s1/CLK
4.750	0.340	tC2Q	RF	9	R6C11[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_2_s1/Q
5.717	0.967	tNET	FF	1	R6C13[1][B]	uart_data_rx/uart_byte_rx/n152_s3/I0
6.477	0.760	tINS	FR	1	R6C13[1][B]	uart_data_rx/uart_byte_rx/n152_s3/F
6.788	0.310	tNET	RR	1	R6C12[0][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s6/I3
7.397	0.609	tINS	RF	2	R6C12[0][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s6/F
7.996	0.599	tNET	FF	1	R5C11[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s4/I1
8.811	0.814	tINS	FF	4	R5C11[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s4/F
9.789	0.979	tNET	FF	1	R6C13[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s3/I3
10.576	0.786	tINS	FR	8	R6C13[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s3/F
10.826	0.251	tNET	RR	1	R6C13[2][B]	uart_data_rx/uart_byte_rx/bps_cnt_5_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R6C13[2][B]	uart_data_rx/uart_byte_rx/bps_cnt_5_s1/CLK
24.378	-0.032	tSu		1	R6C13[2][B]	uart_data_rx/uart_byte_rx/bps_cnt_5_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.970, 46.292%; route: 3.106, 48.415%; tC2Q: 0.340, 5.294%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path13

Path Summary:

Slack	13.892
Data Arrival Time	10.222
Data Required Time	24.114
From	uart_data_rx/timeout_cnt_8_s0
To	uart_data_rx/timeout_cnt_0_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R11C14[2][A]	uart_data_rx/timeout_cnt_8_s0/CLK
4.750	0.340	tC2Q	RF	5	R11C14[2][A]	uart_data_rx/timeout_cnt_8_s0/Q
5.610	0.860	tNET	FF	1	R12C15[3][B]	uart_data_rx/n98_s103/I1
6.219	0.609	tINS	FF	1	R12C15[3][B]	uart_data_rx/n98_s103/F
6.582	0.363	tNET	FF	1	R12C14[3][A]	uart_data_rx/n98_s98/I3
7.343	0.760	tINS	FR	1	R12C14[3][A]	uart_data_rx/n98_s98/F
7.653	0.310	tNET	RR	1	R12C13[3][B]	uart_data_rx/n98_s109/I0
8.418	0.765	tINS	RF	19	R12C13[3][B]	uart_data_rx/n98_s109/F
9.408	0.990	tNET	FF	1	R11C11[1][A]	uart_data_rx/n195_s2/I0
10.222	0.814	tINS	FF	1	R11C11[1][A]	uart_data_rx/n195_s2/F
10.222	0.000	tNET	FF	1	R11C11[1][A]	uart_data_rx/timeout_cnt_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R11C11[1][A]	uart_data_rx/timeout_cnt_0_s0/CLK
24.114	-0.296	tSu		1	R11C11[1][A]	uart_data_rx/timeout_cnt_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.948, 50.734%; route: 2.524, 43.422%; tC2Q: 0.340, 5.844%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path14

Path Summary:

Slack	13.892
Data Arrival Time	10.222
Data Required Time	24.114
From	uart_data_rx/timeout_cnt_8_s0
To	uart_data_rx/timeout_cnt_11_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R11C14[2][A]	uart_data_rx/timeout_cnt_8_s0/CLK
4.750	0.340	tC2Q	RF	5	R11C14[2][A]	uart_data_rx/timeout_cnt_8_s0/Q
5.610	0.860	tNET	FF	1	R12C15[3][B]	uart_data_rx/n98_s103/I1
6.219	0.609	tINS	FF	1	R12C15[3][B]	uart_data_rx/n98_s103/F
6.582	0.363	tNET	FF	1	R12C14[3][A]	uart_data_rx/n98_s98/I3
7.343	0.760	tINS	FR	1	R12C14[3][A]	uart_data_rx/n98_s98/F
7.653	0.310	tNET	RR	1	R12C13[3][B]	uart_data_rx/n98_s109/I0
8.418	0.765	tINS	RF	19	R12C13[3][B]	uart_data_rx/n98_s109/F
9.408	0.990	tNET	FF	1	R11C11[0][B]	uart_data_rx/n184_s2/I1
10.222	0.814	tINS	FF	1	R11C11[0][B]	uart_data_rx/n184_s2/F
10.222	0.000	tNET	FF	1	R11C11[0][B]	uart_data_rx/timeout_cnt_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R11C11[0][B]	uart_data_rx/timeout_cnt_11_s0/CLK
24.114	-0.296	tSu		1	R11C11[0][B]	uart_data_rx/timeout_cnt_11_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.948, 50.734%; route: 2.524, 43.422%; tC2Q: 0.340, 5.844%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path15

Path Summary:

Slack	13.929
Data Arrival Time	10.450
Data Required Time	24.378
From	uart_data_rx/uart_byte_rx/bps_cnt_6_s1
To	uart_data_rx/uart_byte_rx/STOP_BIT_0_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R5C11[0][B]	uart_data_rx/uart_byte_rx/bps_cnt_6_s1/CLK
4.750	0.340	tC2Q	RF	15	R5C11[0][B]	uart_data_rx/uart_byte_rx/bps_cnt_6_s1/Q
5.128	0.378	tNET	FF	1	R6C11[3][A]	uart_data_rx/uart_byte_rx/START_BIT_2_s5/I1
5.893	0.765	tINS	FF	1	R6C11[3][A]	uart_data_rx/uart_byte_rx/START_BIT_2_s5/F
5.897	0.004	tNET	FF	1	R6C11[3][B]	uart_data_rx/uart_byte_rx/bps_cnt_7_s5/I3
6.491	0.594	tINS	FR	3	R6C11[3][B]	uart_data_rx/uart_byte_rx/bps_cnt_7_s5/F
6.808	0.316	tNET	RR	1	R5C11[3][B]	uart_data_rx/uart_byte_rx/START_BIT_2_s3/I2
7.572	0.765	tINS	RF	10	R5C11[3][B]	uart_data_rx/uart_byte_rx/START_BIT_2_s3/F
8.797	1.224	tNET	FF	1	R7C13[0][B]	uart_data_rx/uart_byte_rx/STOP_BIT_2_s2/I1
9.557	0.760	tINS	FR	3	R7C13[0][B]	uart_data_rx/uart_byte_rx/STOP_BIT_2_s2/F
10.450	0.893	tNET	RR	1	R7C13[1][B]	uart_data_rx/uart_byte_rx/STOP_BIT_0_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R7C13[1][B]	uart_data_rx/uart_byte_rx/STOP_BIT_0_s0/CLK
24.378	-0.032	tSu		1	R7C13[1][B]	uart_data_rx/uart_byte_rx/STOP_BIT_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.884, 47.755%; route: 2.816, 46.622%; tC2Q: 0.340, 5.624%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path16

Path Summary:

Slack	13.929
Data Arrival Time	10.450
Data Required Time	24.378
From	uart_data_rx/uart_byte_rx/bps_cnt_6_s1
To	uart_data_rx/uart_byte_rx/STOP_BIT_1_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R5C11[0][B]	uart_data_rx/uart_byte_rx/bps_cnt_6_s1/CLK
4.750	0.340	tC2Q	RF	15	R5C11[0][B]	uart_data_rx/uart_byte_rx/bps_cnt_6_s1/Q
5.128	0.378	tNET	FF	1	R6C11[3][A]	uart_data_rx/uart_byte_rx/START_BIT_2_s5/I1
5.893	0.765	tINS	FF	1	R6C11[3][A]	uart_data_rx/uart_byte_rx/START_BIT_2_s5/F
5.897	0.004	tNET	FF	1	R6C11[3][B]	uart_data_rx/uart_byte_rx/bps_cnt_7_s5/I3
6.491	0.594	tINS	FR	3	R6C11[3][B]	uart_data_rx/uart_byte_rx/bps_cnt_7_s5/F
6.808	0.316	tNET	RR	1	R5C11[3][B]	uart_data_rx/uart_byte_rx/START_BIT_2_s3/I2
7.572	0.765	tINS	RF	10	R5C11[3][B]	uart_data_rx/uart_byte_rx/START_BIT_2_s3/F
8.797	1.224	tNET	FF	1	R7C13[0][B]	uart_data_rx/uart_byte_rx/STOP_BIT_2_s2/I1
9.557	0.760	tINS	FR	3	R7C13[0][B]	uart_data_rx/uart_byte_rx/STOP_BIT_2_s2/F
10.450	0.893	tNET	RR	1	R7C13[2][B]	uart_data_rx/uart_byte_rx/STOP_BIT_1_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R7C13[2][B]	uart_data_rx/uart_byte_rx/STOP_BIT_1_s0/CLK
24.378	-0.032	tSu		1	R7C13[2][B]	uart_data_rx/uart_byte_rx/STOP_BIT_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.884, 47.755%; route: 2.816, 46.622%; tC2Q: 0.340, 5.624%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path17

Path Summary:

Slack	13.929
Data Arrival Time	10.450
Data Required Time	24.378
From	uart_data_rx/uart_byte_rx/bps_cnt_6_s1
To	uart_data_rx/uart_byte_rx/STOP_BIT_2_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R5C11[0][B]	uart_data_rx/uart_byte_rx/bps_cnt_6_s1/CLK
4.750	0.340	tC2Q	RF	15	R5C11[0][B]	uart_data_rx/uart_byte_rx/bps_cnt_6_s1/Q
5.128	0.378	tNET	FF	1	R6C11[3][A]	uart_data_rx/uart_byte_rx/START_BIT_2_s5/I1
5.893	0.765	tINS	FF	1	R6C11[3][A]	uart_data_rx/uart_byte_rx/START_BIT_2_s5/F
5.897	0.004	tNET	FF	1	R6C11[3][B]	uart_data_rx/uart_byte_rx/bps_cnt_7_s5/I3
6.491	0.594	tINS	FR	3	R6C11[3][B]	uart_data_rx/uart_byte_rx/bps_cnt_7_s5/F
6.808	0.316	tNET	RR	1	R5C11[3][B]	uart_data_rx/uart_byte_rx/START_BIT_2_s3/I2
7.572	0.765	tINS	RF	10	R5C11[3][B]	uart_data_rx/uart_byte_rx/START_BIT_2_s3/F
8.797	1.224	tNET	FF	1	R7C13[0][B]	uart_data_rx/uart_byte_rx/STOP_BIT_2_s2/I1
9.557	0.760	tINS	FR	3	R7C13[0][B]	uart_data_rx/uart_byte_rx/STOP_BIT_2_s2/F
10.450	0.893	tNET	RR	1	R7C13[1][A]	uart_data_rx/uart_byte_rx/STOP_BIT_2_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R7C13[1][A]	uart_data_rx/uart_byte_rx/STOP_BIT_2_s0/CLK
24.378	-0.032	tSu		1	R7C13[1][A]	uart_data_rx/uart_byte_rx/STOP_BIT_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.884, 47.755%; route: 2.816, 46.622%; tC2Q: 0.340, 5.624%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path18

Path Summary:

Slack	13.990
Data Arrival Time	10.124
Data Required Time	24.114
From	uart_data_rx/timeout_cnt_8_s0
To	uart_data_rx/timeout_cnt_10_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R11C14[2][A]	uart_data_rx/timeout_cnt_8_s0/CLK
4.750	0.340	tC2Q	RF	5	R11C14[2][A]	uart_data_rx/timeout_cnt_8_s0/Q
5.610	0.860	tNET	FF	1	R12C15[3][B]	uart_data_rx/n98_s103/I1
6.219	0.609	tINS	FF	1	R12C15[3][B]	uart_data_rx/n98_s103/F
6.582	0.363	tNET	FF	1	R12C14[3][A]	uart_data_rx/n98_s98/I3
7.343	0.760	tINS	FR	1	R12C14[3][A]	uart_data_rx/n98_s98/F
7.653	0.310	tNET	RR	1	R12C13[3][B]	uart_data_rx/n98_s109/I0
8.418	0.765	tINS	RF	19	R12C13[3][B]	uart_data_rx/n98_s109/F
9.310	0.892	tNET	FF	1	R12C15[0][A]	uart_data_rx/n185_s2/I1
10.124	0.814	tINS	FF	1	R12C15[0][A]	uart_data_rx/n185_s2/F
10.124	0.000	tNET	FF	1	R12C15[0][A]	uart_data_rx/timeout_cnt_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R12C15[0][A]	uart_data_rx/timeout_cnt_10_s0/CLK
24.114	-0.296	tSu		1	R12C15[0][A]	uart_data_rx/timeout_cnt_10_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.948, 51.602%; route: 2.426, 42.454%; tC2Q: 0.340, 5.944%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path19

Path Summary:

Slack	13.991
Data Arrival Time	10.388
Data Required Time	24.378
From	uart_data_rx/uart_byte_rx/bps_cnt_2_s1
To	uart_data_rx/uart_byte_rx/uart_state_s1
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R6C11[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_2_s1/CLK
4.750	0.340	tC2Q	RF	9	R6C11[1][A]	uart_data_rx/uart_byte_rx/bps_cnt_2_s1/Q
5.717	0.967	tNET	FF	1	R6C13[1][B]	uart_data_rx/uart_byte_rx/n152_s3/I0
6.477	0.760	tINS	FR	1	R6C13[1][B]	uart_data_rx/uart_byte_rx/n152_s3/F
6.788	0.310	tNET	RR	1	R6C12[0][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s6/I3
7.397	0.609	tINS	RF	2	R6C12[0][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s6/F
7.996	0.599	tNET	FF	1	R5C11[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s4/I1
8.811	0.814	tINS	FF	4	R5C11[3][A]	uart_data_rx/uart_byte_rx/bps_cnt_7_s4/F
9.544	0.734	tNET	FF	1	R6C13[0][B]	uart_data_rx/uart_byte_rx/uart_state_s3/I2
10.139	0.594	tINS	FR	1	R6C13[0][B]	uart_data_rx/uart_byte_rx/uart_state_s3/F
10.388	0.249	tNET	RR	1	R6C13[0][A]	uart_data_rx/uart_byte_rx/uart_state_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R6C13[0][A]	uart_data_rx/uart_byte_rx/uart_state_s1/CLK
24.378	-0.032	tSu		1	R6C13[0][A]	uart_data_rx/uart_byte_rx/uart_state_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.778, 46.477%; route: 2.860, 47.841%; tC2Q: 0.340, 5.682%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path20

Path Summary:

Slack	13.992
Data Arrival Time	10.122
Data Required Time	24.114
From	uart_data_rx/timeout_cnt_8_s0
To	uart_data_rx/timeout_cnt_16_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R11C14[2][A]	uart_data_rx/timeout_cnt_8_s0/CLK
4.750	0.340	tC2Q	RF	5	R11C14[2][A]	uart_data_rx/timeout_cnt_8_s0/Q
5.610	0.860	tNET	FF	1	R12C15[3][B]	uart_data_rx/n98_s103/I1
6.219	0.609	tINS	FF	1	R12C15[3][B]	uart_data_rx/n98_s103/F
6.582	0.363	tNET	FF	1	R12C14[3][A]	uart_data_rx/n98_s98/I3
7.343	0.760	tINS	FR	1	R12C14[3][A]	uart_data_rx/n98_s98/F
7.653	0.310	tNET	RR	1	R12C13[3][B]	uart_data_rx/n98_s109/I0
8.418	0.765	tINS	RF	19	R12C13[3][B]	uart_data_rx/n98_s109/F
9.658	1.240	tNET	FF	1	R11C15[1][B]	uart_data_rx/n179_s2/I1
10.122	0.464	tINS	FF	1	R11C15[1][B]	uart_data_rx/n179_s2/F
10.122	0.000	tNET	FF	1	R11C15[1][B]	uart_data_rx/timeout_cnt_16_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R11C15[1][B]	uart_data_rx/timeout_cnt_16_s0/CLK
24.114	-0.296	tSu		1	R11C15[1][B]	uart_data_rx/timeout_cnt_16_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.598, 45.488%; route: 2.774, 48.565%; tC2Q: 0.340, 5.947%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path21

Path Summary:

Slack	13.997
Data Arrival Time	10.117
Data Required Time	24.114
From	uart_data_rx/timeout_cnt_8_s0
To	uart_data_rx/timeout_cnt_1_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R11C14[2][A]	uart_data_rx/timeout_cnt_8_s0/CLK
4.750	0.340	tC2Q	RF	5	R11C14[2][A]	uart_data_rx/timeout_cnt_8_s0/Q
5.610	0.860	tNET	FF	1	R12C15[3][B]	uart_data_rx/n98_s103/I1
6.219	0.609	tINS	FF	1	R12C15[3][B]	uart_data_rx/n98_s103/F
6.582	0.363	tNET	FF	1	R12C14[3][A]	uart_data_rx/n98_s98/I3
7.343	0.760	tINS	FR	1	R12C14[3][A]	uart_data_rx/n98_s98/F
7.653	0.310	tNET	RR	1	R12C13[3][B]	uart_data_rx/n98_s109/I0
8.418	0.765	tINS	RF	19	R12C13[3][B]	uart_data_rx/n98_s109/F
9.653	1.235	tNET	FF	1	R11C11[2][A]	uart_data_rx/n194_s2/I0
10.117	0.464	tINS	FF	1	R11C11[2][A]	uart_data_rx/n194_s2/F
10.117	0.000	tNET	FF	1	R11C11[2][A]	uart_data_rx/timeout_cnt_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R11C11[2][A]	uart_data_rx/timeout_cnt_1_s0/CLK
24.114	-0.296	tSu		1	R11C11[2][A]	uart_data_rx/timeout_cnt_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.598, 45.528%; route: 2.769, 48.520%; tC2Q: 0.340, 5.952%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path22

Path Summary:

Slack	14.000
Data Arrival Time	10.114
Data Required Time	24.114
From	uart_data_rx/timeout_cnt_8_s0
To	uart_data_rx/timeout_flag_s1
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R11C14[2][A]	uart_data_rx/timeout_cnt_8_s0/CLK
4.750	0.340	tC2Q	RF	5	R11C14[2][A]	uart_data_rx/timeout_cnt_8_s0/Q
5.610	0.860	tNET	FF	1	R12C15[3][B]	uart_data_rx/n98_s103/I1
6.219	0.609	tINS	FF	1	R12C15[3][B]	uart_data_rx/n98_s103/F
6.582	0.363	tNET	FF	1	R12C14[3][A]	uart_data_rx/n98_s98/I3
7.343	0.760	tINS	FR	1	R12C14[3][A]	uart_data_rx/n98_s98/F
7.653	0.310	tNET	RR	1	R12C13[3][B]	uart_data_rx/n98_s109/I0
8.418	0.765	tINS	RF	19	R12C13[3][B]	uart_data_rx/n98_s109/F
10.114	1.696	tNET	FF	1	R11C10[1][B]	uart_data_rx/timeout_flag_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R11C10[1][B]	uart_data_rx/timeout_flag_s1/CLK
24.114	-0.296	tSu		1	R11C10[1][B]	uart_data_rx/timeout_flag_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.134, 37.418%; route: 3.230, 56.627%; tC2Q: 0.340, 5.955%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path23

Path Summary:

Slack	14.039
Data Arrival Time	10.075
Data Required Time	24.114
From	uart_data_rx/timeout_cnt_8_s0
To	uart_data_rx/timeout_cnt_7_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R11C14[2][A]	uart_data_rx/timeout_cnt_8_s0/CLK
4.750	0.340	tC2Q	RF	5	R11C14[2][A]	uart_data_rx/timeout_cnt_8_s0/Q
5.610	0.860	tNET	FF	1	R12C15[3][B]	uart_data_rx/n98_s103/I1
6.219	0.609	tINS	FF	1	R12C15[3][B]	uart_data_rx/n98_s103/F
6.582	0.363	tNET	FF	1	R12C14[3][A]	uart_data_rx/n98_s98/I3
7.343	0.760	tINS	FR	1	R12C14[3][A]	uart_data_rx/n98_s98/F
7.653	0.310	tNET	RR	1	R12C13[3][B]	uart_data_rx/n98_s109/I0
8.418	0.765	tINS	RF	19	R12C13[3][B]	uart_data_rx/n98_s109/F
9.310	0.892	tNET	FF	1	R12C15[1][B]	uart_data_rx/n188_s2/I1
10.075	0.765	tINS	FF	1	R12C15[1][B]	uart_data_rx/n188_s2/F
10.075	0.000	tNET	FF	1	R12C15[1][B]	uart_data_rx/timeout_cnt_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R12C15[1][B]	uart_data_rx/timeout_cnt_7_s0/CLK
24.114	-0.296	tSu		1	R12C15[1][B]	uart_data_rx/timeout_cnt_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.899, 51.177%; route: 2.426, 42.827%; tC2Q: 0.340, 5.996%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path24

Path Summary:

Slack	14.039
Data Arrival Time	10.075
Data Required Time	24.114
From	uart_data_rx/timeout_cnt_8_s0
To	uart_data_rx/timeout_cnt_9_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R11C14[2][A]	uart_data_rx/timeout_cnt_8_s0/CLK
4.750	0.340	tC2Q	RF	5	R11C14[2][A]	uart_data_rx/timeout_cnt_8_s0/Q
5.610	0.860	tNET	FF	1	R12C15[3][B]	uart_data_rx/n98_s103/I1
6.219	0.609	tINS	FF	1	R12C15[3][B]	uart_data_rx/n98_s103/F
6.582	0.363	tNET	FF	1	R12C14[3][A]	uart_data_rx/n98_s98/I3
7.343	0.760	tINS	FR	1	R12C14[3][A]	uart_data_rx/n98_s98/F
7.653	0.310	tNET	RR	1	R12C13[3][B]	uart_data_rx/n98_s109/I0
8.418	0.765	tINS	RF	19	R12C13[3][B]	uart_data_rx/n98_s109/F
9.310	0.892	tNET	FF	1	R12C15[1][A]	uart_data_rx/n186_s2/I1
10.075	0.765	tINS	FF	1	R12C15[1][A]	uart_data_rx/n186_s2/F
10.075	0.000	tNET	FF	1	R12C15[1][A]	uart_data_rx/timeout_cnt_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R12C15[1][A]	uart_data_rx/timeout_cnt_9_s0/CLK
24.114	-0.296	tSu		1	R12C15[1][A]	uart_data_rx/timeout_cnt_9_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.899, 51.177%; route: 2.426, 42.827%; tC2Q: 0.340, 5.996%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path25

Path Summary:

Slack	14.050
Data Arrival Time	10.064
Data Required Time	24.114
From	uart_data_rx/timeout_cnt_8_s0
To	uart_data_rx/timeout_cnt_5_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R11C14[2][A]	uart_data_rx/timeout_cnt_8_s0/CLK
4.750	0.340	tC2Q	RF	5	R11C14[2][A]	uart_data_rx/timeout_cnt_8_s0/Q
5.610	0.860	tNET	FF	1	R12C15[3][B]	uart_data_rx/n98_s103/I1
6.219	0.609	tINS	FF	1	R12C15[3][B]	uart_data_rx/n98_s103/F
6.582	0.363	tNET	FF	1	R12C14[3][A]	uart_data_rx/n98_s98/I3
7.343	0.760	tINS	FR	1	R12C14[3][A]	uart_data_rx/n98_s98/F
7.653	0.310	tNET	RR	1	R12C13[3][B]	uart_data_rx/n98_s109/I0
8.418	0.765	tINS	RF	19	R12C13[3][B]	uart_data_rx/n98_s109/F
9.299	0.882	tNET	FF	1	R11C14[1][B]	uart_data_rx/n190_s2/I1
10.064	0.765	tINS	FF	1	R11C14[1][B]	uart_data_rx/n190_s2/F
10.064	0.000	tNET	FF	1	R11C14[1][B]	uart_data_rx/timeout_cnt_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	244	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R11C14[1][B]	uart_data_rx/timeout_cnt_5_s0/CLK
24.114	-0.296	tSu		1	R11C14[1][B]	uart_data_rx/timeout_cnt_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.899, 51.274%; route: 2.415, 42.719%; tC2Q: 0.340, 6.007%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_data_tx/uart_byte_tx/div_cnt_3_s0
To	uart_data_tx/uart_byte_tx/div_cnt_3_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C5[0][A]	uart_data_tx/uart_byte_tx/div_cnt_3_s0/CLK
3.510	0.247	tC2Q	RR	4	R8C5[0][A]	uart_data_tx/uart_byte_tx/div_cnt_3_s0/Q
3.512	0.002	tNET	RR	1	R8C5[0][A]	uart_data_tx/uart_byte_tx/n122_s2/I2
3.788	0.276	tINS	RF	1	R8C5[0][A]	uart_data_tx/uart_byte_tx/n122_s2/F
3.788	0.000	tNET	FF	1	R8C5[0][A]	uart_data_tx/uart_byte_tx/div_cnt_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C5[0][A]	uart_data_tx/uart_byte_tx/div_cnt_3_s0/CLK
3.263	0.000	tHld		1	R8C5[0][A]	uart_data_tx/uart_byte_tx/div_cnt_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path2

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_data_tx/uart_byte_tx/div_cnt_14_s0
To	uart_data_tx/uart_byte_tx/div_cnt_14_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C5[0][A]	uart_data_tx/uart_byte_tx/div_cnt_14_s0/CLK
3.510	0.247	tC2Q	RR	3	R7C5[0][A]	uart_data_tx/uart_byte_tx/div_cnt_14_s0/Q
3.512	0.002	tNET	RR	1	R7C5[0][A]	uart_data_tx/uart_byte_tx/n111_s2/I2
3.788	0.276	tINS	RF	1	R7C5[0][A]	uart_data_tx/uart_byte_tx/n111_s2/F
3.788	0.000	tNET	FF	1	R7C5[0][A]	uart_data_tx/uart_byte_tx/div_cnt_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C5[0][A]	uart_data_tx/uart_byte_tx/div_cnt_14_s0/CLK
3.263	0.000	tHld		1	R7C5[0][A]	uart_data_tx/uart_byte_tx/div_cnt_14_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path3

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_data_tx/byte_send_en_s4
To	uart_data_tx/byte_send_en_s4
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C6[0][A]	uart_data_tx/byte_send_en_s4/CLK
3.510	0.247	tC2Q	RR	11	R9C6[0][A]	uart_data_tx/byte_send_en_s4/Q
3.512	0.002	tNET	RR	1	R9C6[0][A]	uart_data_tx/data_byte_6_s6/I2
3.788	0.276	tINS	RF	1	R9C6[0][A]	uart_data_tx/data_byte_6_s6/F
3.788	0.000	tNET	FF	1	R9C6[0][A]	uart_data_tx/byte_send_en_s4/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C6[0][A]	uart_data_tx/byte_send_en_s4/CLK
3.263	0.000	tHld		1	R9C6[0][A]	uart_data_tx/byte_send_en_s4

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path4

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_data_tx/data_byte_7_s2
To	uart_data_tx/data_byte_7_s2
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C7[0][A]	uart_data_tx/data_byte_7_s2/CLK
3.510	0.247	tC2Q	RR	2	R9C7[0][A]	uart_data_tx/data_byte_7_s2/Q
3.512	0.002	tNET	RR	1	R9C7[0][A]	uart_data_tx/n82_s6/I2
3.788	0.276	tINS	RF	1	R9C7[0][A]	uart_data_tx/n82_s6/F
3.788	0.000	tNET	FF	1	R9C7[0][A]	uart_data_tx/data_byte_7_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C7[0][A]	uart_data_tx/data_byte_7_s2/CLK
3.263	0.000	tHld		1	R9C7[0][A]	uart_data_tx/data_byte_7_s2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path5

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_data_tx/data_byte_0_s2
To	uart_data_tx/data_byte_0_s2
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C7[0][A]	uart_data_tx/data_byte_0_s2/CLK
3.510	0.247	tC2Q	RR	2	R11C7[0][A]	uart_data_tx/data_byte_0_s2/Q
3.512	0.002	tNET	RR	1	R11C7[0][A]	uart_data_tx/n89_s6/I2
3.788	0.276	tINS	RF	1	R11C7[0][A]	uart_data_tx/n89_s6/F
3.788	0.000	tNET	FF	1	R11C7[0][A]	uart_data_tx/data_byte_0_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C7[0][A]	uart_data_tx/data_byte_0_s2/CLK
3.263	0.000	tHld		1	R11C7[0][A]	uart_data_tx/data_byte_0_s2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path6

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_data_tx/data_byte_2_s2
To	uart_data_tx/data_byte_2_s2
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C7[1][A]	uart_data_tx/data_byte_2_s2/CLK
3.510	0.247	tC2Q	RR	2	R11C7[1][A]	uart_data_tx/data_byte_2_s2/Q
3.512	0.002	tNET	RR	1	R11C7[1][A]	uart_data_tx/n87_s6/I2
3.788	0.276	tINS	RF	1	R11C7[1][A]	uart_data_tx/n87_s6/F
3.788	0.000	tNET	FF	1	R11C7[1][A]	uart_data_tx/data_byte_2_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C7[1][A]	uart_data_tx/data_byte_2_s2/CLK
3.263	0.000	tHld		1	R11C7[1][A]	uart_data_tx/data_byte_2_s2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path7

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_data_tx/data_byte_6_s3
To	uart_data_tx/data_byte_6_s3
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C6[0][A]	uart_data_tx/data_byte_6_s3/CLK
3.510	0.247	tC2Q	RR	2	R11C6[0][A]	uart_data_tx/data_byte_6_s3/Q
3.512	0.002	tNET	RR	1	R11C6[0][A]	uart_data_tx/n83_s6/I2
3.788	0.276	tINS	RF	1	R11C6[0][A]	uart_data_tx/n83_s6/F
3.788	0.000	tNET	FF	1	R11C6[0][A]	uart_data_tx/data_byte_6_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C6[0][A]	uart_data_tx/data_byte_6_s3/CLK
3.263	0.000	tHld		1	R11C6[0][A]	uart_data_tx/data_byte_6_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path8

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_data_tx/cnt_7_s1
To	uart_data_tx/cnt_7_s1
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R6C6[1][A]	uart_data_tx/cnt_7_s1/CLK
3.510	0.247	tC2Q	RR	3	R6C6[1][A]	uart_data_tx/cnt_7_s1/Q
3.512	0.002	tNET	RR	1	R6C6[1][A]	uart_data_tx/n72_s9/I0
3.788	0.276	tINS	RF	1	R6C6[1][A]	uart_data_tx/n72_s9/F
3.788	0.000	tNET	FF	1	R6C6[1][A]	uart_data_tx/cnt_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R6C6[1][A]	uart_data_tx/cnt_7_s1/CLK
3.263	0.000	tHld		1	R6C6[1][A]	uart_data_tx/cnt_7_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path9

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_data_rx/uart_byte_rx/STOP_BIT_2_s0
To	uart_data_rx/uart_byte_rx/STOP_BIT_2_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C13[1][A]	uart_data_rx/uart_byte_rx/STOP_BIT_2_s0/CLK
3.510	0.247	tC2Q	RR	2	R7C13[1][A]	uart_data_rx/uart_byte_rx/STOP_BIT_2_s0/Q
3.512	0.002	tNET	RR	1	R7C13[1][A]	uart_data_rx/uart_byte_rx/n589_s5/I2
3.788	0.276	tINS	RF	1	R7C13[1][A]	uart_data_rx/uart_byte_rx/n589_s5/F
3.788	0.000	tNET	FF	1	R7C13[1][A]	uart_data_rx/uart_byte_rx/STOP_BIT_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C13[1][A]	uart_data_rx/uart_byte_rx/STOP_BIT_2_s0/CLK
3.263	0.000	tHld		1	R7C13[1][A]	uart_data_rx/uart_byte_rx/STOP_BIT_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path10

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_data_rx/uart_byte_rx/data_byte_pre[0]_2_s0
To	uart_data_rx/uart_byte_rx/data_byte_pre[0]_2_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C11[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[0]_2_s0/CLK
3.510	0.247	tC2Q	RR	2	R8C11[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[0]_2_s0/Q
3.512	0.002	tNET	RR	1	R8C11[1][A]	uart_data_rx/uart_byte_rx/n580_s5/I2
3.788	0.276	tINS	RF	1	R8C11[1][A]	uart_data_rx/uart_byte_rx/n580_s5/F
3.788	0.000	tNET	FF	1	R8C11[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[0]_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C11[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[0]_2_s0/CLK
3.263	0.000	tHld		1	R8C11[1][A]	uart_data_rx/uart_byte_rx/data_byte_pre[0]_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path11

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_data_rx/uart_byte_rx/data_byte_pre[2]_1_s0
To	uart_data_rx/uart_byte_rx/data_byte_pre[2]_1_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R5C13[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[2]_1_s0/CLK
3.510	0.247	tC2Q	RR	2	R5C13[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[2]_1_s0/Q
3.512	0.002	tNET	RR	1	R5C13[0][A]	uart_data_rx/uart_byte_rx/n565_s6/I0
3.788	0.276	tINS	RF	1	R5C13[0][A]	uart_data_rx/uart_byte_rx/n565_s6/F
3.788	0.000	tNET	FF	1	R5C13[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[2]_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R5C13[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[2]_1_s0/CLK
3.263	0.000	tHld		1	R5C13[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[2]_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path12

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_data_rx/uart_byte_rx/data_byte_pre[3]_1_s0
To	uart_data_rx/uart_byte_rx/data_byte_pre[3]_1_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C11[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[3]_1_s0/CLK
3.510	0.247	tC2Q	RR	2	R8C11[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[3]_1_s0/Q
3.512	0.002	tNET	RR	1	R8C11[0][A]	uart_data_rx/uart_byte_rx/n556_s6/I0
3.788	0.276	tINS	RF	1	R8C11[0][A]	uart_data_rx/uart_byte_rx/n556_s6/F
3.788	0.000	tNET	FF	1	R8C11[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[3]_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C11[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[3]_1_s0/CLK
3.263	0.000	tHld		1	R8C11[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[3]_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path13

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_data_rx/uart_byte_rx/data_byte_pre[5]_0_s0
To	uart_data_rx/uart_byte_rx/data_byte_pre[5]_0_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R6C11[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[5]_0_s0/CLK
3.510	0.247	tC2Q	RR	3	R6C11[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[5]_0_s0/Q
3.512	0.002	tNET	RR	1	R6C11[0][A]	uart_data_rx/uart_byte_rx/n541_s5/I1
3.788	0.276	tINS	RF	1	R6C11[0][A]	uart_data_rx/uart_byte_rx/n541_s5/F
3.788	0.000	tNET	FF	1	R6C11[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[5]_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R6C11[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[5]_0_s0/CLK
3.263	0.000	tHld		1	R6C11[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[5]_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path14

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_data_rx/uart_byte_rx/data_byte_pre[5]_2_s0
To	uart_data_rx/uart_byte_rx/data_byte_pre[5]_2_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C12[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[5]_2_s0/CLK
3.510	0.247	tC2Q	RR	2	R7C12[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[5]_2_s0/Q
3.512	0.002	tNET	RR	1	R7C12[0][A]	uart_data_rx/uart_byte_rx/n535_s5/I2
3.788	0.276	tINS	RF	1	R7C12[0][A]	uart_data_rx/uart_byte_rx/n535_s5/F
3.788	0.000	tNET	FF	1	R7C12[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[5]_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C12[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[5]_2_s0/CLK
3.263	0.000	tHld		1	R7C12[0][A]	uart_data_rx/uart_byte_rx/data_byte_pre[5]_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path15

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_data_rx/uart_byte_rx/START_BIT_2_s0
To	uart_data_rx/uart_byte_rx/START_BIT_2_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R6C12[1][A]	uart_data_rx/uart_byte_rx/START_BIT_2_s0/CLK
3.510	0.247	tC2Q	RR	2	R6C12[1][A]	uart_data_rx/uart_byte_rx/START_BIT_2_s0/Q
3.512	0.002	tNET	RR	1	R6C12[1][A]	uart_data_rx/uart_byte_rx/n508_s5/I2
3.788	0.276	tINS	RF	1	R6C12[1][A]	uart_data_rx/uart_byte_rx/n508_s5/F
3.788	0.000	tNET	FF	1	R6C12[1][A]	uart_data_rx/uart_byte_rx/START_BIT_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R6C12[1][A]	uart_data_rx/uart_byte_rx/START_BIT_2_s0/CLK
3.263	0.000	tHld		1	R6C12[1][A]	uart_data_rx/uart_byte_rx/START_BIT_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path16

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_data_rx/uart_byte_rx/div_cnt_7_s0
To	uart_data_rx/uart_byte_rx/div_cnt_7_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C12[0][A]	uart_data_rx/uart_byte_rx/div_cnt_7_s0/CLK
3.510	0.247	tC2Q	RR	7	R9C12[0][A]	uart_data_rx/uart_byte_rx/div_cnt_7_s0/Q
3.512	0.002	tNET	RR	1	R9C12[0][A]	uart_data_rx/uart_byte_rx/n97_s2/I0
3.788	0.276	tINS	RF	1	R9C12[0][A]	uart_data_rx/uart_byte_rx/n97_s2/F
3.788	0.000	tNET	FF	1	R9C12[0][A]	uart_data_rx/uart_byte_rx/div_cnt_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C12[0][A]	uart_data_rx/uart_byte_rx/div_cnt_7_s0/CLK
3.263	0.000	tHld		1	R9C12[0][A]	uart_data_rx/uart_byte_rx/div_cnt_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path17

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_data_rx/uart_byte_rx/div_cnt_9_s0
To	uart_data_rx/uart_byte_rx/div_cnt_9_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C14[0][A]	uart_data_rx/uart_byte_rx/div_cnt_9_s0/CLK
3.510	0.247	tC2Q	RR	4	R8C14[0][A]	uart_data_rx/uart_byte_rx/div_cnt_9_s0/Q
3.512	0.002	tNET	RR	1	R8C14[0][A]	uart_data_rx/uart_byte_rx/n95_s2/I2
3.788	0.276	tINS	RF	1	R8C14[0][A]	uart_data_rx/uart_byte_rx/n95_s2/F
3.788	0.000	tNET	FF	1	R8C14[0][A]	uart_data_rx/uart_byte_rx/div_cnt_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C14[0][A]	uart_data_rx/uart_byte_rx/div_cnt_9_s0/CLK
3.263	0.000	tHld		1	R8C14[0][A]	uart_data_rx/uart_byte_rx/div_cnt_9_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path18

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_data_rx/uart_byte_rx/div_cnt_14_s0
To	uart_data_rx/uart_byte_rx/div_cnt_14_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C13[0][A]	uart_data_rx/uart_byte_rx/div_cnt_14_s0/CLK
3.510	0.247	tC2Q	RR	3	R8C13[0][A]	uart_data_rx/uart_byte_rx/div_cnt_14_s0/Q
3.512	0.002	tNET	RR	1	R8C13[0][A]	uart_data_rx/uart_byte_rx/n90_s2/I2
3.788	0.276	tINS	RF	1	R8C13[0][A]	uart_data_rx/uart_byte_rx/n90_s2/F
3.788	0.000	tNET	FF	1	R8C13[0][A]	uart_data_rx/uart_byte_rx/div_cnt_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C13[0][A]	uart_data_rx/uart_byte_rx/div_cnt_14_s0/CLK
3.263	0.000	tHld		1	R8C13[0][A]	uart_data_rx/uart_byte_rx/div_cnt_14_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path19

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_data_rx/uart_byte_rx/div_cnt_15_s0
To	uart_data_rx/uart_byte_rx/div_cnt_15_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C12[1][A]	uart_data_rx/uart_byte_rx/div_cnt_15_s0/CLK
3.510	0.247	tC2Q	RR	2	R9C12[1][A]	uart_data_rx/uart_byte_rx/div_cnt_15_s0/Q
3.512	0.002	tNET	RR	1	R9C12[1][A]	uart_data_rx/uart_byte_rx/n89_s2/I2
3.788	0.276	tINS	RF	1	R9C12[1][A]	uart_data_rx/uart_byte_rx/n89_s2/F
3.788	0.000	tNET	FF	1	R9C12[1][A]	uart_data_rx/uart_byte_rx/div_cnt_15_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C12[1][A]	uart_data_rx/uart_byte_rx/div_cnt_15_s0/CLK
3.263	0.000	tHld		1	R9C12[1][A]	uart_data_rx/uart_byte_rx/div_cnt_15_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path20

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_data_rx/state_1_s2
To	uart_data_rx/state_1_s2
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C10[0][A]	uart_data_rx/state_1_s2/CLK
3.510	0.247	tC2Q	RR	15	R9C10[0][A]	uart_data_rx/state_1_s2/Q
3.512	0.002	tNET	RR	1	R9C10[0][A]	uart_data_rx/n442_s9/I0
3.788	0.276	tINS	RF	1	R9C10[0][A]	uart_data_rx/n442_s9/F
3.788	0.000	tNET	FF	1	R9C10[0][A]	uart_data_rx/state_1_s2/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C10[0][A]	uart_data_rx/state_1_s2/CLK
3.263	0.000	tHld		1	R9C10[0][A]	uart_data_rx/state_1_s2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path21

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_data_rx/to_state_s4
To	uart_data_rx/to_state_s4
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C15[0][A]	uart_data_rx/to_state_s4/CLK
3.510	0.247	tC2Q	RR	19	R11C15[0][A]	uart_data_rx/to_state_s4/Q
3.512	0.002	tNET	RR	1	R11C15[0][A]	uart_data_rx/n92_s4/I1
3.788	0.276	tINS	RF	1	R11C15[0][A]	uart_data_rx/n92_s4/F
3.788	0.000	tNET	FF	1	R11C15[0][A]	uart_data_rx/to_state_s4/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C15[0][A]	uart_data_rx/to_state_s4/CLK
3.263	0.000	tHld		1	R11C15[0][A]	uart_data_rx/to_state_s4

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path22

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_data_rx/timeout_cnt_2_s0
To	uart_data_rx/timeout_cnt_2_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R12C12[0][A]	uart_data_rx/timeout_cnt_2_s0/CLK
3.510	0.247	tC2Q	RR	4	R12C12[0][A]	uart_data_rx/timeout_cnt_2_s0/Q
3.512	0.002	tNET	RR	1	R12C12[0][A]	uart_data_rx/n193_s2/I2
3.788	0.276	tINS	RF	1	R12C12[0][A]	uart_data_rx/n193_s2/F
3.788	0.000	tNET	FF	1	R12C12[0][A]	uart_data_rx/timeout_cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R12C12[0][A]	uart_data_rx/timeout_cnt_2_s0/CLK
3.263	0.000	tHld		1	R12C12[0][A]	uart_data_rx/timeout_cnt_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path23

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_data_rx/timeout_cnt_17_s0
To	uart_data_rx/timeout_cnt_17_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C13[0][A]	uart_data_rx/timeout_cnt_17_s0/CLK
3.510	0.247	tC2Q	RR	3	R11C13[0][A]	uart_data_rx/timeout_cnt_17_s0/Q
3.512	0.002	tNET	RR	1	R11C13[0][A]	uart_data_rx/n178_s5/I2
3.788	0.276	tINS	RF	1	R11C13[0][A]	uart_data_rx/n178_s5/F
3.788	0.000	tNET	FF	1	R11C13[0][A]	uart_data_rx/timeout_cnt_17_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C13[0][A]	uart_data_rx/timeout_cnt_17_s0/CLK
3.263	0.000	tHld		1	R11C13[0][A]	uart_data_rx/timeout_cnt_17_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path24

Path Summary:

Slack	0.525
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_data_tx/uart_byte_tx/div_cnt_1_s0
To	uart_data_tx/uart_byte_tx/div_cnt_1_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C5[1][A]	uart_data_tx/uart_byte_tx/div_cnt_1_s0/CLK
3.510	0.247	tC2Q	RR	5	R7C5[1][A]	uart_data_tx/uart_byte_tx/div_cnt_1_s0/Q
3.513	0.003	tNET	RR	1	R7C5[1][A]	uart_data_tx/uart_byte_tx/n124_s2/I1
3.788	0.276	tINS	RF	1	R7C5[1][A]	uart_data_tx/uart_byte_tx/n124_s2/F
3.788	0.000	tNET	FF	1	R7C5[1][A]	uart_data_tx/uart_byte_tx/div_cnt_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C5[1][A]	uart_data_tx/uart_byte_tx/div_cnt_1_s0/CLK
3.263	0.000	tHld		1	R7C5[1][A]	uart_data_tx/uart_byte_tx/div_cnt_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path25

Path Summary:

Slack	0.525
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_data_tx/uart_byte_tx/div_cnt_9_s0
To	uart_data_tx/uart_byte_tx/div_cnt_9_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C6[1][A]	uart_data_tx/uart_byte_tx/div_cnt_9_s0/CLK
3.510	0.247	tC2Q	RR	6	R7C6[1][A]	uart_data_tx/uart_byte_tx/div_cnt_9_s0/Q
3.513	0.003	tNET	RR	1	R7C6[1][A]	uart_data_tx/uart_byte_tx/n116_s2/I0
3.788	0.276	tINS	RF	1	R7C6[1][A]	uart_data_tx/uart_byte_tx/n116_s2/F
3.788	0.000	tNET	FF	1	R7C6[1][A]	uart_data_tx/uart_byte_tx/div_cnt_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	244	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C6[1][A]	uart_data_tx/uart_byte_tx/div_cnt_9_s0/CLK
3.263	0.000	tHld		1	R7C6[1][A]	uart_data_tx/uart_byte_tx/div_cnt_9_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	Clk
Objects:	uart_data_rx/timeout_cnt_17_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
4.411	0.181	tNET	RR	uart_data_rx/timeout_cnt_17_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
12.285	0.145	tNET	FF	uart_data_rx/timeout_cnt_17_s0/CLK

MPW2

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	Clk
Objects:	uart_data_rx/timeout_cnt_16_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
4.411	0.181	tNET	RR	uart_data_rx/timeout_cnt_16_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
12.285	0.145	tNET	FF	uart_data_rx/timeout_cnt_16_s0/CLK

MPW3

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	Clk
Objects:	uart_data_rx/timeout_cnt_14_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
4.411	0.181	tNET	RR	uart_data_rx/timeout_cnt_14_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
12.285	0.145	tNET	FF	uart_data_rx/timeout_cnt_14_s0/CLK

MPW4

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	Clk
Objects:	uart_data_rx/timeout_cnt_10_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
4.411	0.181	tNET	RR	uart_data_rx/timeout_cnt_10_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
12.285	0.145	tNET	FF	uart_data_rx/timeout_cnt_10_s0/CLK

MPW5

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	Clk
Objects:	uart_data_rx/timeout_cnt_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
4.411	0.181	tNET	RR	uart_data_rx/timeout_cnt_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
12.285	0.145	tNET	FF	uart_data_rx/timeout_cnt_2_s0/CLK

MPW6

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	Clk
Objects:	uart_data_rx/data_r_18_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
4.411	0.181	tNET	RR	uart_data_rx/data_r_18_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
12.285	0.145	tNET	FF	uart_data_rx/data_r_18_s0/CLK

MPW7

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	Clk
Objects:	uart_data_rx/data_18_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
4.411	0.181	tNET	RR	uart_data_rx/data_18_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
12.285	0.145	tNET	FF	uart_data_rx/data_18_s0/CLK

MPW8

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	Clk
Objects:	uart_data_rx/uart_byte_rx/data_byte_pre[4]_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
4.411	0.181	tNET	RR	uart_data_rx/uart_byte_rx/data_byte_pre[4]_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
12.285	0.145	tNET	FF	uart_data_rx/uart_byte_rx/data_byte_pre[4]_1_s0/CLK

MPW9

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	Clk
Objects:	uart_data_rx/uart_byte_rx/data_byte_pre[4]_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
4.411	0.181	tNET	RR	uart_data_rx/uart_byte_rx/data_byte_pre[4]_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
12.285	0.145	tNET	FF	uart_data_rx/uart_byte_rx/data_byte_pre[4]_2_s0/CLK

MPW10

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	Clk
Objects:	uart_data_rx/data_19_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
4.411	0.181	tNET	RR	uart_data_rx/data_19_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
12.285	0.145	tNET	FF	uart_data_rx/data_19_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
244	Clk_d	12.678	0.195
56	uart_data_rx/byte_rx_done	16.025	1.953
43	uart_data_tx/state[0]	15.914	1.681
41	uart_data_rx/state[0]	16.414	1.025
38	led_d[0]	16.324	2.225
34	uart_data_rx/n450_11	16.143	1.348
32	uart_data_rx/data_r_31_8	16.445	1.223
31	uart_data_rx/uart_byte_rx/uart_rx_sync2	16.640	1.709
24	uart_data_tx/data_r_23_8	16.794	0.611
23	uart_data_tx/state[1]	15.392	1.727

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R2C2	100.00%
R2C3	100.00%
R2C10	100.00%
R2C11	100.00%
R3C9	100.00%
R5C5	100.00%
R16C7	100.00%
R16C8	100.00%
R16C5	100.00%
R16C6	100.00%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command