Pin Messages

Report Title Pin Report
Design File C:\Users\ADMIN\Desktop\onekiwi_fpga_board-main\fpga_1P5\EXAMPLE CODE\UART_transmit_receive_multiple_byte\impl\gwsynthesis\uart_loopback.vg
Physical Constraints File C:\Users\ADMIN\Desktop\onekiwi_fpga_board-main\fpga_1P5\EXAMPLE CODE\UART_transmit_receive_multiple_byte\src\uart_loopback.cst
Timing Constraints File ---
Tool Version V1.9.11.03 (64-bit)
Part Number GW1N-UV1P5QN48XFC7/I6
Device GW1N-1P5
Device Version C
Created Time Wed Jul 30 11:57:27 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Pin Details

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site CFG IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor BankVccio
Clk - 4/5 Y in IOL6[A] GCLKT_7 LVCMOS18 NA NONE ON NONE NA NA NA NA 1.8
Rst_n - 35/1 Y in IOR1[B] - LVCMOS18 NA NONE ON NONE NA NA OFF NA 1.8
uart_rx - 33/1 Y in IOR11[B] GCLKC_2 LVCMOS18 NA NONE ON NONE NA NA OFF NA 1.8
led[0] - 28/1 Y out IOR15[B] - LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
led[1] - 27/1 Y out IOR17[A] - LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
uart_tx - 34/1 Y out IOR11[A] GCLKT_2 LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8

All Package Pins:

Loc./Bank Signal Dir. Site CFG IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor Bank Vccio
48/0 - out IOT7[A] TDO LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
47/0 - in IOT7[B] TDI LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
45/0 - in IOT9[A] TCK LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
44/0 - in IOT9[B] TMS LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
43/0 - in IOT14[A] GCLKT_1 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
42/0 - in IOT14[B] GCLKC_1 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
41/0 - in IOT15[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
40/0 - in IOT15[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
38/0 - in IOT18[A] READY LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
37/0 - in IOT18[B] DONE LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
14/2 - in IOB2[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
15/2 - in IOB2[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
16/2 - in IOB5[A] SCLK LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
17/2 - in IOB5[B] SO LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
18/2 - in IOB7[A] GCLKT_4 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
19/2 - in IOB7[B] GCLKC_4 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
20/2 - in IOB9[A] GCLKT_3 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
21/2 - in IOB9[B] GCLKC_3 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
23/2 - in IOB18[A] SSPI_CS_N LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
24/2 - in IOB18[B] SI LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
2/5 - in IOL4[A] LPLL_T_fb LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
3/5 - in IOL4[B] LPLL_C_fb LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
4/5 Clk in IOL6[A] GCLKT_7 LVCMOS18 NA NONE ON NONE NA NA NA NA 1.8
5/5 - in IOL6[B] GCLKC_7 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
7/4 - in IOL11[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
8/4 - in IOL11[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
9/4 - in IOL12[A] GCLKT_6 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
10/4 - in IOL12[B] GCLKC_6 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
11/3 - in IOL17[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
12/3 - in IOL17[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
36/1 - in IOR1[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
35/1 Rst_n in IOR1[B] - LVCMOS18 NA NONE ON NONE NA NA OFF NA 1.8
34/1 uart_tx out IOR11[A] GCLKT_2 LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
33/1 uart_rx in IOR11[B] GCLKC_2 LVCMOS18 NA NONE ON NONE NA NA OFF NA 1.8
32/1 - in IOR13[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
31/1 - in IOR13[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
29/1 - in IOR15[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
28/1 led[0] out IOR15[B] - LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
27/1 led[1] out IOR17[A] - LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
26/1 - in IOR17[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8