Synthesis Messages

Report Title	GowinSynthesis Report
Design File	C:\quanggit_lab\example_code\UART_tX_1BYTE\src\uart_byte_tx.v C:\quanggit_lab\example_code\UART_tX_1BYTE\src\uart_tx_test.v
GowinSynthesis Constraints File	---
Tool Version	V1.9.11.03 (64-bit)
Part Number	GW1N-UV1P5QN48XFC7/I6
Device	GW1N-1P5
Device Version	C
Created Time	Mon Jul 21 10:14:47 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module	uart_tx_test
Synthesis Process	Running parser:     CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.041s, Peak memory usage = 246.461MB Running netlist conversion:     CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization:     Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 246.461MB     Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 246.461MB     Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 246.461MB Running inference:     Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 246.461MB     Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 246.461MB     Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 246.461MB     Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 246.461MB Running technical mapping:     Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 246.461MB     Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 246.461MB     Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 246.461MB     Tech-Mapping Phase 3: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.281s, Peak memory usage = 246.461MB     Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.066s, Peak memory usage = 246.461MB Generate output files:     CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 246.461MB
Total Time and Memory Usage	CPU time = 0h 0m 0.232s, Elapsed time = 0h 0m 0.399s, Peak memory usage = 246.461MB

Resource

Resource Usage Summary

Resource	Usage
I/O Port	4
I/O Buf	4
IBUF	2
OBUF	2
Register	67
DFFP	1
DFFC	47
DFFCE	19
LUT	96
LUT2	12
LUT3	29
LUT4	55
ALU	7
ALU	7
INV	3
INV	3

Resource Utilization Summary

Resource	Usage	Utilization
Logic	106(99 LUT, 7 ALU) / 1584	7%
Register	67 / 1704	4%
--Register as Latch	0 / 1704	0%
--Register as FF	67 / 1704	4%
BSRAM	0 / 4	0%

Timing

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Object
1	clk	Base	20.000	50.000	0.000	10.000			clk_ibuf/I

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk	50.000(MHz)	133.891(MHz)	4	TOP

Detail Timing Paths Information

Path 1

Path Summary:

Slack	12.531
Data Arrival Time	7.710
Data Required Time	20.242
From	uart_byte_tx/data_byte_reg_5_s0
To	uart_byte_tx/uart_tx_s0
Launch Clk	clk[R]
Latch Clk	clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.000	0.000	tINS	RR	67	clk_ibuf/O
0.538	0.538	tNET	RR	1	uart_byte_tx/data_byte_reg_5_s0/CLK
0.878	0.340	tC2Q	RF	1	uart_byte_tx/data_byte_reg_5_s0/Q
1.589	0.711	tNET	FF	1	uart_byte_tx/n177_s34/I1
2.403	0.814	tINS	FF	1	uart_byte_tx/n177_s34/F
3.115	0.711	tNET	FF	1	uart_byte_tx/n177_s22/I1
3.225	0.110	tINS	FF	1	uart_byte_tx/n177_s22/O
3.936	0.711	tNET	FF	1	uart_byte_tx/n177_s35/I0
4.701	0.765	tINS	FF	1	uart_byte_tx/n177_s35/F
5.413	0.711	tNET	FF	1	uart_byte_tx/n177_s26/I0
5.523	0.110	tINS	FF	1	uart_byte_tx/n177_s26/O
6.234	0.711	tNET	FF	1	uart_byte_tx/n177_s28/I0
6.999	0.765	tINS	FF	1	uart_byte_tx/n177_s28/F
7.710	0.711	tNET	FF	1	uart_byte_tx/uart_tx_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	0.000				clk
20.000	0.000	tCL	RR	1	clk_ibuf/I
20.000	0.000	tINS	RR	67	clk_ibuf/O
20.538	0.538	tNET	RR	1	uart_byte_tx/uart_tx_s0/CLK
20.242	-0.296	tSu		1	uart_byte_tx/uart_tx_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	4
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay:	cell: 2.565, 35.757%; route: 4.268, 59.508%; tC2Q: 0.340, 4.735%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 2

Path Summary:

Slack	12.550
Data Arrival Time	7.692
Data Required Time	20.242
From	cnt_5_s0
To	cnt_23_s0
Launch Clk	clk[R]
Latch Clk	clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.000	0.000	tINS	RR	67	clk_ibuf/O
0.538	0.538	tNET	RR	1	cnt_5_s0/CLK
0.878	0.340	tC2Q	RF	3	cnt_5_s0/Q
1.589	0.711	tNET	FF	1	n70_s4/I1
2.403	0.814	tINS	FF	4	n70_s4/F
3.115	0.711	tNET	FF	1	n61_s3/I1
3.929	0.814	tINS	FF	7	n61_s3/F
4.640	0.711	tNET	FF	1	n54_s3/I1
5.455	0.814	tINS	FF	3	n54_s3/F
6.166	0.711	tNET	FF	1	n56_s2/I1
6.980	0.814	tINS	FF	1	n56_s2/F
7.692	0.711	tNET	FF	1	cnt_23_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	0.000				clk
20.000	0.000	tCL	RR	1	clk_ibuf/I
20.000	0.000	tINS	RR	67	clk_ibuf/O
20.538	0.538	tNET	RR	1	cnt_23_s0/CLK
20.242	-0.296	tSu		1	cnt_23_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay:	cell: 3.257, 45.534%; route: 3.557, 49.719%; tC2Q: 0.340, 4.747%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 3

Path Summary:

Slack	12.599
Data Arrival Time	7.642
Data Required Time	20.242
From	cnt_5_s0
To	cnt_25_s0
Launch Clk	clk[R]
Latch Clk	clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.000	0.000	tINS	RR	67	clk_ibuf/O
0.538	0.538	tNET	RR	1	cnt_5_s0/CLK
0.878	0.340	tC2Q	RF	3	cnt_5_s0/Q
1.589	0.711	tNET	FF	1	n70_s4/I1
2.403	0.814	tINS	FF	4	n70_s4/F
3.115	0.711	tNET	FF	1	n61_s3/I1
3.929	0.814	tINS	FF	7	n61_s3/F
4.640	0.711	tNET	FF	1	n54_s3/I1
5.455	0.814	tINS	FF	3	n54_s3/F
6.166	0.711	tNET	FF	1	n54_s2/I0
6.931	0.765	tINS	FF	1	n54_s2/F
7.642	0.711	tNET	FF	1	cnt_25_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	0.000				clk
20.000	0.000	tCL	RR	1	clk_ibuf/I
20.000	0.000	tINS	RR	67	clk_ibuf/O
20.538	0.538	tNET	RR	1	cnt_25_s0/CLK
20.242	-0.296	tSu		1	cnt_25_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay:	cell: 3.208, 45.153%; route: 3.557, 50.066%; tC2Q: 0.340, 4.781%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 4

Path Summary:

Slack	12.599
Data Arrival Time	7.642
Data Required Time	20.242
From	cnt_5_s0
To	cnt_12_s0
Launch Clk	clk[R]
Latch Clk	clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.000	0.000	tINS	RR	67	clk_ibuf/O
0.538	0.538	tNET	RR	1	cnt_5_s0/CLK
0.878	0.340	tC2Q	RF	3	cnt_5_s0/Q
1.589	0.711	tNET	FF	1	n70_s4/I1
2.403	0.814	tINS	FF	4	n70_s4/F
3.115	0.711	tNET	FF	1	n68_s3/I1
3.929	0.814	tINS	FF	3	n68_s3/F
4.640	0.711	tNET	FF	1	n67_s3/I0
5.405	0.765	tINS	FF	1	n67_s3/F
6.116	0.711	tNET	FF	1	n67_s2/I1
6.931	0.814	tINS	FF	1	n67_s2/F
7.642	0.711	tNET	FF	1	cnt_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	0.000				clk
20.000	0.000	tCL	RR	1	clk_ibuf/I
20.000	0.000	tINS	RR	67	clk_ibuf/O
20.538	0.538	tNET	RR	1	cnt_12_s0/CLK
20.242	-0.296	tSu		1	cnt_12_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay:	cell: 3.208, 45.153%; route: 3.557, 50.066%; tC2Q: 0.340, 4.781%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 5

Path Summary:

Slack	12.599
Data Arrival Time	7.642
Data Required Time	20.242
From	cnt_5_s0
To	cnt_15_s0
Launch Clk	clk[R]
Latch Clk	clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.000	0.000	tINS	RR	67	clk_ibuf/O
0.538	0.538	tNET	RR	1	cnt_5_s0/CLK
0.878	0.340	tC2Q	RF	3	cnt_5_s0/Q
1.589	0.711	tNET	FF	1	n70_s4/I1
2.403	0.814	tINS	FF	4	n70_s4/F
3.115	0.711	tNET	FF	1	n61_s3/I1
3.929	0.814	tINS	FF	7	n61_s3/F
4.640	0.711	tNET	FF	1	n64_s3/I0
5.405	0.765	tINS	FF	1	n64_s3/F
6.116	0.711	tNET	FF	1	n64_s2/I1
6.931	0.814	tINS	FF	1	n64_s2/F
7.642	0.711	tNET	FF	1	cnt_15_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	0.000				clk
20.000	0.000	tCL	RR	1	clk_ibuf/I
20.000	0.000	tINS	RR	67	clk_ibuf/O
20.538	0.538	tNET	RR	1	cnt_15_s0/CLK
20.242	-0.296	tSu		1	cnt_15_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay:	cell: 3.208, 45.153%; route: 3.557, 50.066%; tC2Q: 0.340, 4.781%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.538, 100.000%