Timing Messages

Report Title	Timing Analysis Report
Design File	C:\quanggit_lab\example_code\UART_RX_1BYTE\impl\gwsynthesis\uart_rx.vg
Physical Constraints File	C:\quanggit_lab\example_code\UART_RX_1BYTE\src\uart_rx.cst
Timing Constraint File	---
Tool Version	V1.9.11.03 (64-bit)
Part Number	GW1N-UV1P5QN48XFC7/I6
Device	GW1N-1P5
Device Version	C
Created Time	Mon Jul 21 10:56:34 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 1.71V 85C C7/I6
Hold Delay Model	Fast 3.6V 0C C7/I6
Numbers of Paths Analyzed	285
Numbers of Endpoints Analyzed	285
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	clk	Base	20.000	50.000	0.000	10.000			clk_ibuf/I

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk	50.000(MHz)	175.902(MHz)	4	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk	Setup	0.000	0
clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	14.315	uart_byte_rx/div_cnt_12_s0/Q	uart_byte_rx/div_cnt_5_s0/D	clk:[R]	clk:[R]	20.000	0.000	5.389
2	14.471	uart_byte_rx/div_cnt_12_s0/Q	uart_byte_rx/div_cnt_2_s0/D	clk:[R]	clk:[R]	20.000	0.000	5.233
3	14.476	uart_byte_rx/div_cnt_0_s0/Q	uart_byte_rx/div_cnt_15_s0/D	clk:[R]	clk:[R]	20.000	0.000	5.227
4	14.567	uart_byte_rx/div_cnt_12_s0/Q	uart_byte_rx/div_cnt_7_s0/D	clk:[R]	clk:[R]	20.000	0.000	5.136
5	14.662	uart_byte_rx/bps_cnt_4_s1/Q	uart_byte_rx/rx_done_s0/D	clk:[R]	clk:[R]	20.000	0.000	5.041
6	14.681	uart_byte_rx/bps_cnt_1_s1/Q	uart_byte_rx/data_byte_pre[3]_1_s0/D	clk:[R]	clk:[R]	20.000	0.000	5.023
7	14.703	uart_byte_tx/data_byte_reg_3_s0/Q	uart_byte_tx/uart_tx_s0/D	clk:[R]	clk:[R]	20.000	0.000	5.000
8	14.927	uart_byte_rx/div_cnt_0_s0/Q	uart_byte_rx/div_cnt_14_s0/D	clk:[R]	clk:[R]	20.000	0.000	4.777
9	14.929	uart_byte_rx/bps_cnt_1_s1/Q	uart_byte_rx/data_byte_pre[1]_1_s0/D	clk:[R]	clk:[R]	20.000	0.000	4.775
10	14.930	uart_byte_rx/div_cnt_12_s0/Q	uart_byte_rx/bps_clk_s0/D	clk:[R]	clk:[R]	20.000	0.000	4.774
11	15.018	uart_byte_rx/bps_cnt_1_s1/Q	uart_byte_rx/data_byte_pre[3]_0_s0/CE	clk:[R]	clk:[R]	20.000	0.000	4.950
12	15.018	uart_byte_rx/bps_cnt_1_s1/Q	uart_byte_rx/data_byte_pre[3]_1_s0/CE	clk:[R]	clk:[R]	20.000	0.000	4.950
13	15.060	uart_byte_tx/div_cnt_0_s0/Q	uart_byte_tx/div_cnt_5_s0/D	clk:[R]	clk:[R]	20.000	0.000	4.644
14	15.134	uart_byte_rx/bps_cnt_1_s1/Q	uart_byte_rx/data_byte_pre[1]_2_s0/D	clk:[R]	clk:[R]	20.000	0.000	4.570
15	15.199	uart_byte_rx/div_cnt_12_s0/Q	uart_byte_rx/div_cnt_3_s0/D	clk:[R]	clk:[R]	20.000	0.000	4.504
16	15.219	uart_byte_rx/bps_cnt_1_s1/Q	uart_byte_rx/data_byte_pre[1]_0_s0/CE	clk:[R]	clk:[R]	20.000	0.000	4.749
17	15.219	uart_byte_rx/bps_cnt_1_s1/Q	uart_byte_rx/data_byte_pre[1]_1_s0/CE	clk:[R]	clk:[R]	20.000	0.000	4.749
18	15.219	uart_byte_rx/bps_cnt_1_s1/Q	uart_byte_rx/data_byte_pre[1]_2_s0/CE	clk:[R]	clk:[R]	20.000	0.000	4.749
19	15.226	uart_byte_rx/bps_cnt_1_s1/Q	uart_byte_rx/data_byte_pre[0]_0_s0/CE	clk:[R]	clk:[R]	20.000	0.000	4.742
20	15.231	uart_byte_rx/bps_cnt_1_s1/Q	uart_byte_rx/data_byte_pre[1]_0_s0/D	clk:[R]	clk:[R]	20.000	0.000	4.473
21	15.231	uart_byte_rx/div_cnt_0_s0/Q	uart_byte_rx/div_cnt_13_s0/D	clk:[R]	clk:[R]	20.000	0.000	4.473
22	15.270	uart_byte_rx/bps_cnt_1_s1/Q	uart_byte_rx/data_byte_pre[7]_2_s0/D	clk:[R]	clk:[R]	20.000	0.000	4.434
23	15.276	uart_byte_tx/div_cnt_0_s0/Q	uart_byte_tx/div_cnt_12_s0/D	clk:[R]	clk:[R]	20.000	0.000	4.428
24	15.276	uart_byte_tx/div_cnt_0_s0/Q	uart_byte_tx/div_cnt_15_s0/D	clk:[R]	clk:[R]	20.000	0.000	4.428
25	15.276	uart_byte_rx/bps_cnt_1_s1/Q	uart_byte_rx/data_byte_pre[3]_0_s0/D	clk:[R]	clk:[R]	20.000	0.000	4.427

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.415	uart_byte_rx/rx_done_s0/Q	data_byte_tx_7_s0/CE	clk:[R]	clk:[R]	0.000	0.000	0.424
2	0.524	uart_byte_rx/STOP_BIT_0_s0/Q	uart_byte_rx/STOP_BIT_0_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.524
3	0.524	uart_byte_rx/STOP_BIT_2_s0/Q	uart_byte_rx/STOP_BIT_2_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.524
4	0.524	uart_byte_rx/data_byte_pre[1]_0_s0/Q	uart_byte_rx/data_byte_pre[1]_0_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.524
5	0.524	uart_byte_rx/data_byte_pre[1]_1_s0/Q	uart_byte_rx/data_byte_pre[1]_1_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.524
6	0.524	uart_byte_rx/data_byte_pre[2]_0_s0/Q	uart_byte_rx/data_byte_pre[2]_0_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.524
7	0.524	uart_byte_rx/data_byte_pre[2]_1_s0/Q	uart_byte_rx/data_byte_pre[2]_1_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.524
8	0.524	uart_byte_rx/data_byte_pre[3]_1_s0/Q	uart_byte_rx/data_byte_pre[3]_1_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.524
9	0.524	uart_byte_rx/data_byte_pre[4]_0_s0/Q	uart_byte_rx/data_byte_pre[4]_0_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.524
10	0.524	uart_byte_rx/data_byte_pre[4]_1_s0/Q	uart_byte_rx/data_byte_pre[4]_1_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.524
11	0.524	uart_byte_rx/data_byte_pre[5]_0_s0/Q	uart_byte_rx/data_byte_pre[5]_0_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.524
12	0.524	uart_byte_rx/data_byte_pre[5]_1_s0/Q	uart_byte_rx/data_byte_pre[5]_1_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.524
13	0.524	uart_byte_rx/data_byte_pre[6]_0_s0/Q	uart_byte_rx/data_byte_pre[6]_0_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.524
14	0.524	uart_byte_rx/data_byte_pre[6]_1_s0/Q	uart_byte_rx/data_byte_pre[6]_1_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.524
15	0.524	uart_byte_rx/data_byte_pre[7]_2_s0/Q	uart_byte_rx/data_byte_pre[7]_2_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.524
16	0.524	uart_byte_rx/START_BIT_0_s0/Q	uart_byte_rx/START_BIT_0_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.524
17	0.524	uart_byte_rx/START_BIT_1_s0/Q	uart_byte_rx/START_BIT_1_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.524
18	0.524	uart_byte_rx/div_cnt_10_s0/Q	uart_byte_rx/div_cnt_10_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.524
19	0.524	uart_byte_tx/div_cnt_15_s0/Q	uart_byte_tx/div_cnt_15_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.524
20	0.525	uart_byte_rx/bps_cnt_0_s1/Q	uart_byte_rx/bps_cnt_0_s1/D	clk:[R]	clk:[R]	0.000	0.000	0.525
21	0.525	uart_byte_rx/data_byte_pre[0]_0_s0/Q	uart_byte_rx/data_byte_pre[0]_0_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.525
22	0.525	uart_byte_rx/div_cnt_6_s0/Q	uart_byte_rx/div_cnt_6_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.525
23	0.525	uart_byte_tx/bps_cnt_3_s1/Q	uart_byte_tx/bps_cnt_3_s1/D	clk:[R]	clk:[R]	0.000	0.000	0.525
24	0.525	uart_byte_tx/div_cnt_8_s0/Q	uart_byte_tx/div_cnt_8_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.525
25	0.525	uart_byte_tx/div_cnt_14_s0/Q	uart_byte_tx/div_cnt_14_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.525

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	6.948	7.874	0.926	High Pulse Width	clk	data_byte_tx_6_s0
2	6.948	7.874	0.926	High Pulse Width	clk	data_byte_tx_5_s0
3	6.948	7.874	0.926	High Pulse Width	clk	data_byte_tx_3_s0
4	6.948	7.874	0.926	High Pulse Width	clk	send_en_s0
5	6.948	7.874	0.926	High Pulse Width	clk	uart_byte_tx/data_byte_reg_1_s0
6	6.948	7.874	0.926	High Pulse Width	clk	uart_byte_tx/div_cnt_1_s0
7	6.948	7.874	0.926	High Pulse Width	clk	uart_byte_rx/START_BIT_0_s0
8	6.948	7.874	0.926	High Pulse Width	clk	uart_byte_rx/START_BIT_1_s0
9	6.948	7.874	0.926	High Pulse Width	clk	uart_byte_tx/div_cnt_2_s0
10	6.948	7.874	0.926	High Pulse Width	clk	uart_byte_rx/START_BIT_2_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	14.315
Data Arrival Time	9.799
Data Required Time	24.114
From	uart_byte_rx/div_cnt_12_s0
To	uart_byte_rx/div_cnt_5_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C7[2][B]	uart_byte_rx/div_cnt_12_s0/CLK
4.750	0.340	tC2Q	RF	5	R8C7[2][B]	uart_byte_rx/div_cnt_12_s0/Q
5.609	0.858	tNET	FF	1	R8C5[3][A]	uart_byte_rx/n124_s4/I0
6.203	0.594	tINS	FR	1	R8C5[3][A]	uart_byte_rx/n124_s4/F
6.513	0.310	tNET	RR	1	R8C6[3][B]	uart_byte_rx/n124_s2/I2
7.328	0.814	tINS	RF	7	R8C6[3][B]	uart_byte_rx/n124_s2/F
9.034	1.707	tNET	FF	1	R7C5[2][B]	uart_byte_rx/n99_s2/I1
9.799	0.765	tINS	FF	1	R7C5[2][B]	uart_byte_rx/n99_s2/F
9.799	0.000	tNET	FF	1	R7C5[2][B]	uart_byte_rx/div_cnt_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R7C5[2][B]	uart_byte_rx/div_cnt_5_s0/CLK
24.114	-0.296	tSu		1	R7C5[2][B]	uart_byte_rx/div_cnt_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.173, 40.333%; route: 2.876, 53.365%; tC2Q: 0.340, 6.303%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path2

Path Summary:

Slack	14.471
Data Arrival Time	9.644
Data Required Time	24.114
From	uart_byte_rx/div_cnt_12_s0
To	uart_byte_rx/div_cnt_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C7[2][B]	uart_byte_rx/div_cnt_12_s0/CLK
4.750	0.340	tC2Q	RF	5	R8C7[2][B]	uart_byte_rx/div_cnt_12_s0/Q
5.609	0.858	tNET	FF	1	R8C5[3][A]	uart_byte_rx/n124_s4/I0
6.203	0.594	tINS	FR	1	R8C5[3][A]	uart_byte_rx/n124_s4/F
6.513	0.310	tNET	RR	1	R8C6[3][B]	uart_byte_rx/n124_s2/I2
7.328	0.814	tINS	RF	7	R8C6[3][B]	uart_byte_rx/n124_s2/F
9.034	1.707	tNET	FF	1	R7C5[2][A]	uart_byte_rx/n102_s2/I1
9.644	0.609	tINS	FF	1	R7C5[2][A]	uart_byte_rx/n102_s2/F
9.644	0.000	tNET	FF	1	R7C5[2][A]	uart_byte_rx/div_cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R7C5[2][A]	uart_byte_rx/div_cnt_2_s0/CLK
24.114	-0.296	tSu		1	R7C5[2][A]	uart_byte_rx/div_cnt_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.018, 38.558%; route: 2.876, 54.951%; tC2Q: 0.340, 6.490%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path3

Path Summary:

Slack	14.476
Data Arrival Time	9.638
Data Required Time	24.114
From	uart_byte_rx/div_cnt_0_s0
To	uart_byte_rx/div_cnt_15_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C7[1][B]	uart_byte_rx/div_cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	7	R8C7[1][B]	uart_byte_rx/div_cnt_0_s0/Q
5.610	0.860	tNET	FF	1	R6C6[1][A]	uart_byte_rx/n100_s3/I0
6.220	0.609	tINS	FF	7	R6C6[1][A]	uart_byte_rx/n100_s3/F
7.198	0.978	tNET	FF	1	R8C7[0][A]	uart_byte_rx/n93_s3/I1
7.962	0.765	tINS	FF	5	R8C7[0][A]	uart_byte_rx/n93_s3/F
8.823	0.861	tNET	FF	1	R8C5[2][A]	uart_byte_rx/n89_s2/I0
9.638	0.814	tINS	FF	1	R8C5[2][A]	uart_byte_rx/n89_s2/F
9.638	0.000	tNET	FF	1	R8C5[2][A]	uart_byte_rx/div_cnt_15_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R8C5[2][A]	uart_byte_rx/div_cnt_15_s0/CLK
24.114	-0.296	tSu		1	R8C5[2][A]	uart_byte_rx/div_cnt_15_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.188, 41.861%; route: 2.699, 51.641%; tC2Q: 0.340, 6.497%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path4

Path Summary:

Slack	14.567
Data Arrival Time	9.547
Data Required Time	24.114
From	uart_byte_rx/div_cnt_12_s0
To	uart_byte_rx/div_cnt_7_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C7[2][B]	uart_byte_rx/div_cnt_12_s0/CLK
4.750	0.340	tC2Q	RF	5	R8C7[2][B]	uart_byte_rx/div_cnt_12_s0/Q
5.609	0.858	tNET	FF	1	R8C5[3][A]	uart_byte_rx/n124_s4/I0
6.203	0.594	tINS	FR	1	R8C5[3][A]	uart_byte_rx/n124_s4/F
6.513	0.310	tNET	RR	1	R8C6[3][B]	uart_byte_rx/n124_s2/I2
7.328	0.814	tINS	RF	7	R8C6[3][B]	uart_byte_rx/n124_s2/F
8.782	1.454	tNET	FF	1	R7C5[1][B]	uart_byte_rx/n97_s2/I1
9.547	0.765	tINS	FF	1	R7C5[1][B]	uart_byte_rx/n97_s2/F
9.547	0.000	tNET	FF	1	R7C5[1][B]	uart_byte_rx/div_cnt_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R7C5[1][B]	uart_byte_rx/div_cnt_7_s0/CLK
24.114	-0.296	tSu		1	R7C5[1][B]	uart_byte_rx/div_cnt_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.173, 42.315%; route: 2.623, 51.073%; tC2Q: 0.340, 6.612%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path5

Path Summary:

Slack	14.662
Data Arrival Time	9.452
Data Required Time	24.114
From	uart_byte_rx/bps_cnt_4_s1
To	uart_byte_rx/rx_done_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R7C10[0][A]	uart_byte_rx/bps_cnt_4_s1/CLK
4.750	0.340	tC2Q	RF	12	R7C10[0][A]	uart_byte_rx/bps_cnt_4_s1/Q
5.973	1.223	tNET	FF	1	R5C8[3][B]	uart_byte_rx/n663_s8/I2
6.582	0.609	tINS	FF	4	R5C8[3][B]	uart_byte_rx/n663_s8/F
7.554	0.972	tNET	FF	1	R6C11[2][B]	uart_byte_rx/n663_s6/I1
8.369	0.814	tINS	FF	9	R6C11[2][B]	uart_byte_rx/n663_s6/F
9.452	1.083	tNET	FF	1	R6C12[1][A]	uart_byte_rx/rx_done_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R6C12[1][A]	uart_byte_rx/rx_done_s0/CLK
24.114	-0.296	tSu		1	R6C12[1][A]	uart_byte_rx/rx_done_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	3
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 1.423, 28.235%; route: 3.278, 65.028%; tC2Q: 0.340, 6.737%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path6

Path Summary:

Slack	14.681
Data Arrival Time	9.433
Data Required Time	24.114
From	uart_byte_rx/bps_cnt_1_s1
To	uart_byte_rx/data_byte_pre[3]_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C9[2][B]	uart_byte_rx/bps_cnt_1_s1/CLK
4.750	0.340	tC2Q	RF	7	R8C9[2][B]	uart_byte_rx/bps_cnt_1_s1/Q
5.380	0.630	tNET	FF	1	R6C9[1][A]	uart_byte_rx/START_BIT_2_s5/I0
6.145	0.765	tINS	FF	9	R6C9[1][A]	uart_byte_rx/START_BIT_2_s5/F
7.010	0.865	tNET	FF	1	R7C7[1][B]	uart_byte_rx/data_byte_pre[3]_2_s4/I0
7.775	0.765	tINS	FF	4	R7C7[1][B]	uart_byte_rx/data_byte_pre[3]_2_s4/F
8.619	0.845	tNET	FF	1	R7C5[0][A]	uart_byte_rx/n556_s6/I3
9.433	0.814	tINS	FF	1	R7C5[0][A]	uart_byte_rx/n556_s6/F
9.433	0.000	tNET	FF	1	R7C5[0][A]	uart_byte_rx/data_byte_pre[3]_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R7C5[0][A]	uart_byte_rx/data_byte_pre[3]_1_s0/CLK
24.114	-0.296	tSu		1	R7C5[0][A]	uart_byte_rx/data_byte_pre[3]_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.344, 46.662%; route: 2.339, 46.576%; tC2Q: 0.340, 6.762%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path7

Path Summary:

Slack	14.703
Data Arrival Time	9.411
Data Required Time	24.114
From	uart_byte_tx/data_byte_reg_3_s0
To	uart_byte_tx/uart_tx_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R5C14[1][B]	uart_byte_tx/data_byte_reg_3_s0/CLK
4.750	0.340	tC2Q	RF	1	R5C14[1][B]	uart_byte_tx/data_byte_reg_3_s0/Q
5.345	0.595	tNET	FF	1	R6C15[2][A]	uart_byte_tx/n177_s33/I1
6.105	0.760	tINS	FR	1	R6C15[2][A]	uart_byte_tx/n177_s33/F
6.105	0.000	tNET	RR	1	R6C15[2][A]	uart_byte_tx/n177_s22/I0
6.217	0.111	tINS	RR	1	R6C15[2][A]	uart_byte_tx/n177_s22/O
6.532	0.316	tNET	RR	1	R6C15[3][A]	uart_byte_tx/n177_s35/I0
6.996	0.464	tINS	RF	1	R6C15[3][A]	uart_byte_tx/n177_s35/F
6.996	0.000	tNET	FF	1	R6C15[3][A]	uart_byte_tx/n177_s26/I0
7.106	0.110	tINS	FF	1	R6C15[3][A]	uart_byte_tx/n177_s26/O
7.477	0.370	tNET	FF	1	R6C16[3][B]	uart_byte_tx/n177_s28/I2
8.086	0.609	tINS	FF	1	R6C16[3][B]	uart_byte_tx/n177_s28/F
9.411	1.325	tNET	FF	1	IOR11[A]	uart_byte_tx/uart_tx_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	IOR11[A]	uart_byte_tx/uart_tx_s0/CLK
24.114	-0.296	tSu		1	IOR11[A]	uart_byte_tx/uart_tx_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.055, 41.093%; route: 2.606, 52.115%; tC2Q: 0.340, 6.792%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path8

Path Summary:

Slack	14.927
Data Arrival Time	9.187
Data Required Time	24.114
From	uart_byte_rx/div_cnt_0_s0
To	uart_byte_rx/div_cnt_14_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C7[1][B]	uart_byte_rx/div_cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	7	R8C7[1][B]	uart_byte_rx/div_cnt_0_s0/Q
5.610	0.860	tNET	FF	1	R6C6[1][A]	uart_byte_rx/n100_s3/I0
6.220	0.609	tINS	FF	7	R6C6[1][A]	uart_byte_rx/n100_s3/F
7.198	0.978	tNET	FF	1	R8C7[0][A]	uart_byte_rx/n93_s3/I1
7.962	0.765	tINS	FF	5	R8C7[0][A]	uart_byte_rx/n93_s3/F
8.578	0.616	tNET	FF	1	R8C5[1][B]	uart_byte_rx/n90_s2/I0
9.187	0.609	tINS	FF	1	R8C5[1][B]	uart_byte_rx/n90_s2/F
9.187	0.000	tNET	FF	1	R8C5[1][B]	uart_byte_rx/div_cnt_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R8C5[1][B]	uart_byte_rx/div_cnt_14_s0/CLK
24.114	-0.296	tSu		1	R8C5[1][B]	uart_byte_rx/div_cnt_14_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 1.983, 41.511%; route: 2.454, 51.379%; tC2Q: 0.340, 7.110%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path9

Path Summary:

Slack	14.929
Data Arrival Time	9.186
Data Required Time	24.114
From	uart_byte_rx/bps_cnt_1_s1
To	uart_byte_rx/data_byte_pre[1]_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C9[2][B]	uart_byte_rx/bps_cnt_1_s1/CLK
4.750	0.340	tC2Q	RF	7	R8C9[2][B]	uart_byte_rx/bps_cnt_1_s1/Q
5.380	0.630	tNET	FF	1	R6C9[1][A]	uart_byte_rx/START_BIT_2_s5/I0
6.145	0.765	tINS	FF	9	R6C9[1][A]	uart_byte_rx/START_BIT_2_s5/F
6.751	0.607	tNET	FF	1	R6C10[1][A]	uart_byte_rx/data_byte_pre[1]_2_s3/I1
7.516	0.765	tINS	FF	4	R6C10[1][A]	uart_byte_rx/data_byte_pre[1]_2_s3/F
8.371	0.855	tNET	FF	1	R5C11[1][A]	uart_byte_rx/n574_s6/I3
9.186	0.814	tINS	FF	1	R5C11[1][A]	uart_byte_rx/n574_s6/F
9.186	0.000	tNET	FF	1	R5C11[1][A]	uart_byte_rx/data_byte_pre[1]_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R5C11[1][A]	uart_byte_rx/data_byte_pre[1]_1_s0/CLK
24.114	-0.296	tSu		1	R5C11[1][A]	uart_byte_rx/data_byte_pre[1]_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.344, 49.084%; route: 2.092, 43.803%; tC2Q: 0.340, 7.113%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path10

Path Summary:

Slack	14.930
Data Arrival Time	9.184
Data Required Time	24.114
From	uart_byte_rx/div_cnt_12_s0
To	uart_byte_rx/bps_clk_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C7[2][B]	uart_byte_rx/div_cnt_12_s0/CLK
4.750	0.340	tC2Q	RF	5	R8C7[2][B]	uart_byte_rx/div_cnt_12_s0/Q
5.609	0.858	tNET	FF	1	R8C5[3][A]	uart_byte_rx/n124_s4/I0
6.203	0.594	tINS	FR	1	R8C5[3][A]	uart_byte_rx/n124_s4/F
6.513	0.310	tNET	RR	1	R8C6[3][B]	uart_byte_rx/n124_s2/I2
7.328	0.814	tINS	RF	7	R8C6[3][B]	uart_byte_rx/n124_s2/F
8.420	1.092	tNET	FF	1	R6C6[0][B]	uart_byte_rx/n124_s1/I2
9.184	0.765	tINS	FF	1	R6C6[0][B]	uart_byte_rx/n124_s1/F
9.184	0.000	tNET	FF	1	R6C6[0][B]	uart_byte_rx/bps_clk_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R6C6[0][B]	uart_byte_rx/bps_clk_s0/CLK
24.114	-0.296	tSu		1	R6C6[0][B]	uart_byte_rx/bps_clk_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.173, 45.527%; route: 2.261, 47.358%; tC2Q: 0.340, 7.114%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path11

Path Summary:

Slack	15.018
Data Arrival Time	9.360
Data Required Time	24.378
From	uart_byte_rx/bps_cnt_1_s1
To	uart_byte_rx/data_byte_pre[3]_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C9[2][B]	uart_byte_rx/bps_cnt_1_s1/CLK
4.750	0.340	tC2Q	RF	7	R8C9[2][B]	uart_byte_rx/bps_cnt_1_s1/Q
5.380	0.630	tNET	FF	1	R6C9[1][A]	uart_byte_rx/START_BIT_2_s5/I0
6.145	0.765	tINS	FF	9	R6C9[1][A]	uart_byte_rx/START_BIT_2_s5/F
7.010	0.865	tNET	FF	1	R7C7[1][B]	uart_byte_rx/data_byte_pre[3]_2_s4/I0
7.775	0.765	tINS	FF	4	R7C7[1][B]	uart_byte_rx/data_byte_pre[3]_2_s4/F
8.374	0.599	tNET	FF	1	R7C6[3][A]	uart_byte_rx/data_byte_pre[3]_2_s2/I0
8.837	0.463	tINS	FR	3	R7C6[3][A]	uart_byte_rx/data_byte_pre[3]_2_s2/F
9.360	0.523	tNET	RR	1	R7C5[0][B]	uart_byte_rx/data_byte_pre[3]_0_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R7C5[0][B]	uart_byte_rx/data_byte_pre[3]_0_s0/CLK
24.378	-0.032	tSu		1	R7C5[0][B]	uart_byte_rx/data_byte_pre[3]_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 1.993, 40.257%; route: 2.617, 52.881%; tC2Q: 0.340, 6.862%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path12

Path Summary:

Slack	15.018
Data Arrival Time	9.360
Data Required Time	24.378
From	uart_byte_rx/bps_cnt_1_s1
To	uart_byte_rx/data_byte_pre[3]_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C9[2][B]	uart_byte_rx/bps_cnt_1_s1/CLK
4.750	0.340	tC2Q	RF	7	R8C9[2][B]	uart_byte_rx/bps_cnt_1_s1/Q
5.380	0.630	tNET	FF	1	R6C9[1][A]	uart_byte_rx/START_BIT_2_s5/I0
6.145	0.765	tINS	FF	9	R6C9[1][A]	uart_byte_rx/START_BIT_2_s5/F
7.010	0.865	tNET	FF	1	R7C7[1][B]	uart_byte_rx/data_byte_pre[3]_2_s4/I0
7.775	0.765	tINS	FF	4	R7C7[1][B]	uart_byte_rx/data_byte_pre[3]_2_s4/F
8.374	0.599	tNET	FF	1	R7C6[3][A]	uart_byte_rx/data_byte_pre[3]_2_s2/I0
8.837	0.463	tINS	FR	3	R7C6[3][A]	uart_byte_rx/data_byte_pre[3]_2_s2/F
9.360	0.523	tNET	RR	1	R7C5[0][A]	uart_byte_rx/data_byte_pre[3]_1_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R7C5[0][A]	uart_byte_rx/data_byte_pre[3]_1_s0/CLK
24.378	-0.032	tSu		1	R7C5[0][A]	uart_byte_rx/data_byte_pre[3]_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 1.993, 40.257%; route: 2.617, 52.881%; tC2Q: 0.340, 6.862%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path13

Path Summary:

Slack	15.060
Data Arrival Time	9.054
Data Required Time	24.114
From	uart_byte_tx/div_cnt_0_s0
To	uart_byte_tx/div_cnt_5_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C14[2][B]	uart_byte_tx/div_cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	7	R8C14[2][B]	uart_byte_tx/div_cnt_0_s0/Q
5.018	0.268	tNET	FF	1	R8C14[2][A]	uart_byte_tx/n121_s4/I0
5.832	0.814	tINS	FF	8	R8C14[2][A]	uart_byte_tx/n121_s4/F
7.169	1.337	tNET	FF	1	R5C13[2][A]	uart_byte_tx/n120_s3/I1
7.930	0.760	tINS	FR	1	R5C13[2][A]	uart_byte_tx/n120_s3/F
8.240	0.310	tNET	RR	1	R6C13[1][B]	uart_byte_tx/n120_s2/I2
9.054	0.814	tINS	RF	1	R6C13[1][B]	uart_byte_tx/n120_s2/F
9.054	0.000	tNET	FF	1	R6C13[1][B]	uart_byte_tx/div_cnt_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R6C13[1][B]	uart_byte_tx/div_cnt_5_s0/CLK
24.114	-0.296	tSu		1	R6C13[1][B]	uart_byte_tx/div_cnt_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.389, 51.445%; route: 1.915, 41.242%; tC2Q: 0.340, 7.314%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path14

Path Summary:

Slack	15.134
Data Arrival Time	8.980
Data Required Time	24.114
From	uart_byte_rx/bps_cnt_1_s1
To	uart_byte_rx/data_byte_pre[1]_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C9[2][B]	uart_byte_rx/bps_cnt_1_s1/CLK
4.750	0.340	tC2Q	RF	7	R8C9[2][B]	uart_byte_rx/bps_cnt_1_s1/Q
5.380	0.630	tNET	FF	1	R6C9[1][A]	uart_byte_rx/START_BIT_2_s5/I0
6.145	0.765	tINS	FF	9	R6C9[1][A]	uart_byte_rx/START_BIT_2_s5/F
6.751	0.607	tNET	FF	1	R6C10[1][A]	uart_byte_rx/data_byte_pre[1]_2_s3/I1
7.516	0.765	tINS	FF	4	R6C10[1][A]	uart_byte_rx/data_byte_pre[1]_2_s3/F
8.371	0.855	tNET	FF	1	R5C11[0][B]	uart_byte_rx/n571_s5/I3
8.980	0.609	tINS	FF	1	R5C11[0][B]	uart_byte_rx/n571_s5/F
8.980	0.000	tNET	FF	1	R5C11[0][B]	uart_byte_rx/data_byte_pre[1]_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R5C11[0][B]	uart_byte_rx/data_byte_pre[1]_2_s0/CLK
24.114	-0.296	tSu		1	R5C11[0][B]	uart_byte_rx/data_byte_pre[1]_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.139, 46.797%; route: 2.092, 45.771%; tC2Q: 0.340, 7.432%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path15

Path Summary:

Slack	15.199
Data Arrival Time	8.915
Data Required Time	24.114
From	uart_byte_rx/div_cnt_12_s0
To	uart_byte_rx/div_cnt_3_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C7[2][B]	uart_byte_rx/div_cnt_12_s0/CLK
4.750	0.340	tC2Q	RF	5	R8C7[2][B]	uart_byte_rx/div_cnt_12_s0/Q
5.609	0.858	tNET	FF	1	R8C5[3][A]	uart_byte_rx/n124_s4/I0
6.203	0.594	tINS	FR	1	R8C5[3][A]	uart_byte_rx/n124_s4/F
6.513	0.310	tNET	RR	1	R8C6[3][B]	uart_byte_rx/n124_s2/I2
7.328	0.814	tINS	RF	7	R8C6[3][B]	uart_byte_rx/n124_s2/F
8.306	0.978	tNET	FF	1	R6C7[1][A]	uart_byte_rx/n101_s2/I1
8.915	0.609	tINS	FF	1	R6C7[1][A]	uart_byte_rx/n101_s2/F
8.915	0.000	tNET	FF	1	R6C7[1][A]	uart_byte_rx/div_cnt_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R6C7[1][A]	uart_byte_rx/div_cnt_3_s0/CLK
24.114	-0.296	tSu		1	R6C7[1][A]	uart_byte_rx/div_cnt_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.018, 44.797%; route: 2.147, 47.663%; tC2Q: 0.340, 7.540%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path16

Path Summary:

Slack	15.219
Data Arrival Time	9.160
Data Required Time	24.378
From	uart_byte_rx/bps_cnt_1_s1
To	uart_byte_rx/data_byte_pre[1]_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C9[2][B]	uart_byte_rx/bps_cnt_1_s1/CLK
4.750	0.340	tC2Q	RF	7	R8C9[2][B]	uart_byte_rx/bps_cnt_1_s1/Q
5.380	0.630	tNET	FF	1	R6C9[1][A]	uart_byte_rx/START_BIT_2_s5/I0
6.145	0.765	tINS	FF	9	R6C9[1][A]	uart_byte_rx/START_BIT_2_s5/F
6.751	0.607	tNET	FF	1	R6C10[1][A]	uart_byte_rx/data_byte_pre[1]_2_s3/I1
7.516	0.765	tINS	FF	4	R6C10[1][A]	uart_byte_rx/data_byte_pre[1]_2_s3/F
8.119	0.603	tNET	FF	1	R5C11[2][B]	uart_byte_rx/data_byte_pre[1]_2_s2/I0
8.905	0.786	tINS	FR	3	R5C11[2][B]	uart_byte_rx/data_byte_pre[1]_2_s2/F
9.160	0.255	tNET	RR	1	R5C11[0][A]	uart_byte_rx/data_byte_pre[1]_0_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R5C11[0][A]	uart_byte_rx/data_byte_pre[1]_0_s0/CLK
24.378	-0.032	tSu		1	R5C11[0][A]	uart_byte_rx/data_byte_pre[1]_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.316, 48.759%; route: 2.094, 44.089%; tC2Q: 0.340, 7.151%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path17

Path Summary:

Slack	15.219
Data Arrival Time	9.160
Data Required Time	24.378
From	uart_byte_rx/bps_cnt_1_s1
To	uart_byte_rx/data_byte_pre[1]_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C9[2][B]	uart_byte_rx/bps_cnt_1_s1/CLK
4.750	0.340	tC2Q	RF	7	R8C9[2][B]	uart_byte_rx/bps_cnt_1_s1/Q
5.380	0.630	tNET	FF	1	R6C9[1][A]	uart_byte_rx/START_BIT_2_s5/I0
6.145	0.765	tINS	FF	9	R6C9[1][A]	uart_byte_rx/START_BIT_2_s5/F
6.751	0.607	tNET	FF	1	R6C10[1][A]	uart_byte_rx/data_byte_pre[1]_2_s3/I1
7.516	0.765	tINS	FF	4	R6C10[1][A]	uart_byte_rx/data_byte_pre[1]_2_s3/F
8.119	0.603	tNET	FF	1	R5C11[2][B]	uart_byte_rx/data_byte_pre[1]_2_s2/I0
8.905	0.786	tINS	FR	3	R5C11[2][B]	uart_byte_rx/data_byte_pre[1]_2_s2/F
9.160	0.255	tNET	RR	1	R5C11[1][A]	uart_byte_rx/data_byte_pre[1]_1_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R5C11[1][A]	uart_byte_rx/data_byte_pre[1]_1_s0/CLK
24.378	-0.032	tSu		1	R5C11[1][A]	uart_byte_rx/data_byte_pre[1]_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.316, 48.759%; route: 2.094, 44.089%; tC2Q: 0.340, 7.151%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path18

Path Summary:

Slack	15.219
Data Arrival Time	9.160
Data Required Time	24.378
From	uart_byte_rx/bps_cnt_1_s1
To	uart_byte_rx/data_byte_pre[1]_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C9[2][B]	uart_byte_rx/bps_cnt_1_s1/CLK
4.750	0.340	tC2Q	RF	7	R8C9[2][B]	uart_byte_rx/bps_cnt_1_s1/Q
5.380	0.630	tNET	FF	1	R6C9[1][A]	uart_byte_rx/START_BIT_2_s5/I0
6.145	0.765	tINS	FF	9	R6C9[1][A]	uart_byte_rx/START_BIT_2_s5/F
6.751	0.607	tNET	FF	1	R6C10[1][A]	uart_byte_rx/data_byte_pre[1]_2_s3/I1
7.516	0.765	tINS	FF	4	R6C10[1][A]	uart_byte_rx/data_byte_pre[1]_2_s3/F
8.119	0.603	tNET	FF	1	R5C11[2][B]	uart_byte_rx/data_byte_pre[1]_2_s2/I0
8.905	0.786	tINS	FR	3	R5C11[2][B]	uart_byte_rx/data_byte_pre[1]_2_s2/F
9.160	0.255	tNET	RR	1	R5C11[0][B]	uart_byte_rx/data_byte_pre[1]_2_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R5C11[0][B]	uart_byte_rx/data_byte_pre[1]_2_s0/CLK
24.378	-0.032	tSu		1	R5C11[0][B]	uart_byte_rx/data_byte_pre[1]_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.316, 48.759%; route: 2.094, 44.089%; tC2Q: 0.340, 7.151%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path19

Path Summary:

Slack	15.226
Data Arrival Time	9.153
Data Required Time	24.378
From	uart_byte_rx/bps_cnt_1_s1
To	uart_byte_rx/data_byte_pre[0]_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C9[2][B]	uart_byte_rx/bps_cnt_1_s1/CLK
4.750	0.340	tC2Q	RF	7	R8C9[2][B]	uart_byte_rx/bps_cnt_1_s1/Q
5.380	0.630	tNET	FF	1	R6C9[1][A]	uart_byte_rx/START_BIT_2_s5/I0
6.145	0.765	tINS	FF	9	R6C9[1][A]	uart_byte_rx/START_BIT_2_s5/F
7.010	0.865	tNET	FF	1	R7C8[1][B]	uart_byte_rx/data_byte_pre[0]_2_s3/I1
7.474	0.464	tINS	FF	4	R7C8[1][B]	uart_byte_rx/data_byte_pre[0]_2_s3/F
7.844	0.370	tNET	FF	1	R7C7[3][B]	uart_byte_rx/data_byte_pre[0]_2_s2/I0
8.630	0.786	tINS	FR	3	R7C7[3][B]	uart_byte_rx/data_byte_pre[0]_2_s2/F
9.153	0.523	tNET	RR	1	R7C6[0][A]	uart_byte_rx/data_byte_pre[0]_0_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R7C6[0][A]	uart_byte_rx/data_byte_pre[0]_0_s0/CLK
24.378	-0.032	tSu		1	R7C6[0][A]	uart_byte_rx/data_byte_pre[0]_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.015, 42.486%; route: 2.388, 50.352%; tC2Q: 0.340, 7.162%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path20

Path Summary:

Slack	15.231
Data Arrival Time	8.884
Data Required Time	24.114
From	uart_byte_rx/bps_cnt_1_s1
To	uart_byte_rx/data_byte_pre[1]_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C9[2][B]	uart_byte_rx/bps_cnt_1_s1/CLK
4.750	0.340	tC2Q	RF	7	R8C9[2][B]	uart_byte_rx/bps_cnt_1_s1/Q
5.380	0.630	tNET	FF	1	R6C9[1][A]	uart_byte_rx/START_BIT_2_s5/I0
6.145	0.765	tINS	FF	9	R6C9[1][A]	uart_byte_rx/START_BIT_2_s5/F
6.751	0.607	tNET	FF	1	R6C10[1][A]	uart_byte_rx/data_byte_pre[1]_2_s3/I1
7.516	0.765	tINS	FF	4	R6C10[1][A]	uart_byte_rx/data_byte_pre[1]_2_s3/F
8.119	0.603	tNET	FF	1	R5C11[0][A]	uart_byte_rx/n577_s5/I2
8.884	0.765	tINS	FF	1	R5C11[0][A]	uart_byte_rx/n577_s5/F
8.884	0.000	tNET	FF	1	R5C11[0][A]	uart_byte_rx/data_byte_pre[1]_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R5C11[0][A]	uart_byte_rx/data_byte_pre[1]_0_s0/CLK
24.114	-0.296	tSu		1	R5C11[0][A]	uart_byte_rx/data_byte_pre[1]_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.294, 51.289%; route: 1.839, 41.118%; tC2Q: 0.340, 7.593%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path21

Path Summary:

Slack	15.231
Data Arrival Time	8.883
Data Required Time	24.114
From	uart_byte_rx/div_cnt_0_s0
To	uart_byte_rx/div_cnt_13_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C7[1][B]	uart_byte_rx/div_cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	7	R8C7[1][B]	uart_byte_rx/div_cnt_0_s0/Q
5.610	0.860	tNET	FF	1	R6C6[1][A]	uart_byte_rx/n100_s3/I0
6.220	0.609	tINS	FF	7	R6C6[1][A]	uart_byte_rx/n100_s3/F
7.198	0.978	tNET	FF	1	R8C7[0][A]	uart_byte_rx/n93_s3/I1
7.958	0.760	tINS	FR	5	R8C7[0][A]	uart_byte_rx/n93_s3/F
8.274	0.316	tNET	RR	1	R8C6[1][B]	uart_byte_rx/n91_s2/I0
8.883	0.609	tINS	RF	1	R8C6[1][B]	uart_byte_rx/n91_s2/F
8.883	0.000	tNET	FF	1	R8C6[1][B]	uart_byte_rx/div_cnt_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R8C6[1][B]	uart_byte_rx/div_cnt_13_s0/CLK
24.114	-0.296	tSu		1	R8C6[1][B]	uart_byte_rx/div_cnt_13_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 1.978, 44.235%; route: 2.155, 48.172%; tC2Q: 0.340, 7.593%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path22

Path Summary:

Slack	15.270
Data Arrival Time	8.844
Data Required Time	24.114
From	uart_byte_rx/bps_cnt_1_s1
To	uart_byte_rx/data_byte_pre[7]_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C9[2][B]	uart_byte_rx/bps_cnt_1_s1/CLK
4.750	0.340	tC2Q	RF	7	R8C9[2][B]	uart_byte_rx/bps_cnt_1_s1/Q
5.380	0.630	tNET	FF	1	R6C9[1][A]	uart_byte_rx/START_BIT_2_s5/I0
6.145	0.765	tINS	FF	9	R6C9[1][A]	uart_byte_rx/START_BIT_2_s5/F
7.124	0.979	tNET	FF	1	R7C7[3][A]	uart_byte_rx/data_byte_pre[7]_2_s3/I1
7.718	0.594	tINS	FR	4	R7C7[3][A]	uart_byte_rx/data_byte_pre[7]_2_s3/F
8.030	0.312	tNET	RR	1	R7C6[1][A]	uart_byte_rx/n517_s5/I3
8.844	0.814	tINS	RF	1	R7C6[1][A]	uart_byte_rx/n517_s5/F
8.844	0.000	tNET	FF	1	R7C6[1][A]	uart_byte_rx/data_byte_pre[7]_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R7C6[1][A]	uart_byte_rx/data_byte_pre[7]_2_s0/CLK
24.114	-0.296	tSu		1	R7C6[1][A]	uart_byte_rx/data_byte_pre[7]_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.173, 49.019%; route: 1.921, 43.321%; tC2Q: 0.340, 7.660%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path23

Path Summary:

Slack	15.276
Data Arrival Time	8.838
Data Required Time	24.114
From	uart_byte_tx/div_cnt_0_s0
To	uart_byte_tx/div_cnt_12_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C14[2][B]	uart_byte_tx/div_cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	7	R8C14[2][B]	uart_byte_tx/div_cnt_0_s0/Q
5.018	0.268	tNET	FF	1	R8C14[2][A]	uart_byte_tx/n121_s4/I0
5.832	0.814	tINS	FF	8	R8C14[2][A]	uart_byte_tx/n121_s4/F
6.798	0.966	tNET	FF	1	R6C13[3][B]	uart_byte_tx/n117_s3/I1
7.612	0.814	tINS	FF	5	R6C13[3][B]	uart_byte_tx/n117_s3/F
8.229	0.617	tNET	FF	1	R7C14[2][B]	uart_byte_tx/n113_s2/I0
8.838	0.609	tINS	FF	1	R7C14[2][B]	uart_byte_tx/n113_s2/F
8.838	0.000	tNET	FF	1	R7C14[2][B]	uart_byte_tx/div_cnt_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R7C14[2][B]	uart_byte_tx/div_cnt_12_s0/CLK
24.114	-0.296	tSu		1	R7C14[2][B]	uart_byte_tx/div_cnt_12_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.238, 50.541%; route: 1.850, 41.789%; tC2Q: 0.340, 7.670%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path24

Path Summary:

Slack	15.276
Data Arrival Time	8.838
Data Required Time	24.114
From	uart_byte_tx/div_cnt_0_s0
To	uart_byte_tx/div_cnt_15_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C14[2][B]	uart_byte_tx/div_cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	7	R8C14[2][B]	uart_byte_tx/div_cnt_0_s0/Q
5.018	0.268	tNET	FF	1	R8C14[2][A]	uart_byte_tx/n121_s4/I0
5.832	0.814	tINS	FF	8	R8C14[2][A]	uart_byte_tx/n121_s4/F
6.798	0.966	tNET	FF	1	R6C13[3][B]	uart_byte_tx/n117_s3/I1
7.612	0.814	tINS	FF	5	R6C13[3][B]	uart_byte_tx/n117_s3/F
8.229	0.617	tNET	FF	1	R7C15[0][A]	uart_byte_tx/n110_s2/I0
8.838	0.609	tINS	FF	1	R7C15[0][A]	uart_byte_tx/n110_s2/F
8.838	0.000	tNET	FF	1	R7C15[0][A]	uart_byte_tx/div_cnt_15_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R7C15[0][A]	uart_byte_tx/div_cnt_15_s0/CLK
24.114	-0.296	tSu		1	R7C15[0][A]	uart_byte_tx/div_cnt_15_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.238, 50.541%; route: 1.850, 41.789%; tC2Q: 0.340, 7.670%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path25

Path Summary:

Slack	15.276
Data Arrival Time	8.838
Data Required Time	24.114
From	uart_byte_rx/bps_cnt_1_s1
To	uart_byte_rx/data_byte_pre[3]_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C9[2][B]	uart_byte_rx/bps_cnt_1_s1/CLK
4.750	0.340	tC2Q	RF	7	R8C9[2][B]	uart_byte_rx/bps_cnt_1_s1/Q
5.380	0.630	tNET	FF	1	R6C9[1][A]	uart_byte_rx/START_BIT_2_s5/I0
6.145	0.765	tINS	FF	9	R6C9[1][A]	uart_byte_rx/START_BIT_2_s5/F
7.010	0.865	tNET	FF	1	R7C7[1][B]	uart_byte_rx/data_byte_pre[3]_2_s4/I0
7.775	0.765	tINS	FF	4	R7C7[1][B]	uart_byte_rx/data_byte_pre[3]_2_s4/F
8.374	0.599	tNET	FF	1	R7C5[0][B]	uart_byte_rx/n559_s5/I2
8.838	0.464	tINS	FF	1	R7C5[0][B]	uart_byte_rx/n559_s5/F
8.838	0.000	tNET	FF	1	R7C5[0][B]	uart_byte_rx/data_byte_pre[3]_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	109	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R7C5[0][B]	uart_byte_rx/data_byte_pre[3]_0_s0/CLK
24.114	-0.296	tSu		1	R7C5[0][B]	uart_byte_rx/data_byte_pre[3]_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 1.993, 45.023%; route: 2.094, 47.306%; tC2Q: 0.340, 7.671%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.415
Data Arrival Time	3.687
Data Required Time	3.272
From	uart_byte_rx/rx_done_s0
To	data_byte_tx_7_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R6C12[1][A]	uart_byte_rx/rx_done_s0/CLK
3.510	0.247	tC2Q	RR	10	R6C12[1][A]	uart_byte_rx/rx_done_s0/Q
3.687	0.177	tNET	RR	1	R6C12[2][A]	data_byte_tx_7_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R6C12[2][A]	data_byte_tx_7_s0/CLK
3.272	0.009	tHld		1	R6C12[2][A]	data_byte_tx_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.177, 41.734%; tC2Q: 0.247, 58.266%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path2

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_byte_rx/STOP_BIT_0_s0
To	uart_byte_rx/STOP_BIT_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R6C8[1][A]	uart_byte_rx/STOP_BIT_0_s0/CLK
3.510	0.247	tC2Q	RR	3	R6C8[1][A]	uart_byte_rx/STOP_BIT_0_s0/Q
3.512	0.002	tNET	RR	1	R6C8[1][A]	uart_byte_rx/n595_s5/I1
3.788	0.276	tINS	RF	1	R6C8[1][A]	uart_byte_rx/n595_s5/F
3.788	0.000	tNET	FF	1	R6C8[1][A]	uart_byte_rx/STOP_BIT_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R6C8[1][A]	uart_byte_rx/STOP_BIT_0_s0/CLK
3.263	0.000	tHld		1	R6C8[1][A]	uart_byte_rx/STOP_BIT_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path3

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_byte_rx/STOP_BIT_2_s0
To	uart_byte_rx/STOP_BIT_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R6C8[0][A]	uart_byte_rx/STOP_BIT_2_s0/CLK
3.510	0.247	tC2Q	RR	2	R6C8[0][A]	uart_byte_rx/STOP_BIT_2_s0/Q
3.512	0.002	tNET	RR	1	R6C8[0][A]	uart_byte_rx/n589_s5/I2
3.788	0.276	tINS	RF	1	R6C8[0][A]	uart_byte_rx/n589_s5/F
3.788	0.000	tNET	FF	1	R6C8[0][A]	uart_byte_rx/STOP_BIT_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R6C8[0][A]	uart_byte_rx/STOP_BIT_2_s0/CLK
3.263	0.000	tHld		1	R6C8[0][A]	uart_byte_rx/STOP_BIT_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path4

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_byte_rx/data_byte_pre[1]_0_s0
To	uart_byte_rx/data_byte_pre[1]_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R5C11[0][A]	uart_byte_rx/data_byte_pre[1]_0_s0/CLK
3.510	0.247	tC2Q	RR	3	R5C11[0][A]	uart_byte_rx/data_byte_pre[1]_0_s0/Q
3.512	0.002	tNET	RR	1	R5C11[0][A]	uart_byte_rx/n577_s5/I1
3.788	0.276	tINS	RF	1	R5C11[0][A]	uart_byte_rx/n577_s5/F
3.788	0.000	tNET	FF	1	R5C11[0][A]	uart_byte_rx/data_byte_pre[1]_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R5C11[0][A]	uart_byte_rx/data_byte_pre[1]_0_s0/CLK
3.263	0.000	tHld		1	R5C11[0][A]	uart_byte_rx/data_byte_pre[1]_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path5

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_byte_rx/data_byte_pre[1]_1_s0
To	uart_byte_rx/data_byte_pre[1]_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R5C11[1][A]	uart_byte_rx/data_byte_pre[1]_1_s0/CLK
3.510	0.247	tC2Q	RR	2	R5C11[1][A]	uart_byte_rx/data_byte_pre[1]_1_s0/Q
3.512	0.002	tNET	RR	1	R5C11[1][A]	uart_byte_rx/n574_s6/I0
3.788	0.276	tINS	RF	1	R5C11[1][A]	uart_byte_rx/n574_s6/F
3.788	0.000	tNET	FF	1	R5C11[1][A]	uart_byte_rx/data_byte_pre[1]_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R5C11[1][A]	uart_byte_rx/data_byte_pre[1]_1_s0/CLK
3.263	0.000	tHld		1	R5C11[1][A]	uart_byte_rx/data_byte_pre[1]_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path6

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_byte_rx/data_byte_pre[2]_0_s0
To	uart_byte_rx/data_byte_pre[2]_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C10[1][A]	uart_byte_rx/data_byte_pre[2]_0_s0/CLK
3.510	0.247	tC2Q	RR	3	R7C10[1][A]	uart_byte_rx/data_byte_pre[2]_0_s0/Q
3.512	0.002	tNET	RR	1	R7C10[1][A]	uart_byte_rx/n568_s5/I1
3.788	0.276	tINS	RF	1	R7C10[1][A]	uart_byte_rx/n568_s5/F
3.788	0.000	tNET	FF	1	R7C10[1][A]	uart_byte_rx/data_byte_pre[2]_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C10[1][A]	uart_byte_rx/data_byte_pre[2]_0_s0/CLK
3.263	0.000	tHld		1	R7C10[1][A]	uart_byte_rx/data_byte_pre[2]_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path7

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_byte_rx/data_byte_pre[2]_1_s0
To	uart_byte_rx/data_byte_pre[2]_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C7[1][A]	uart_byte_rx/data_byte_pre[2]_1_s0/CLK
3.510	0.247	tC2Q	RR	2	R7C7[1][A]	uart_byte_rx/data_byte_pre[2]_1_s0/Q
3.512	0.002	tNET	RR	1	R7C7[1][A]	uart_byte_rx/n565_s6/I0
3.788	0.276	tINS	RF	1	R7C7[1][A]	uart_byte_rx/n565_s6/F
3.788	0.000	tNET	FF	1	R7C7[1][A]	uart_byte_rx/data_byte_pre[2]_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C7[1][A]	uart_byte_rx/data_byte_pre[2]_1_s0/CLK
3.263	0.000	tHld		1	R7C7[1][A]	uart_byte_rx/data_byte_pre[2]_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path8

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_byte_rx/data_byte_pre[3]_1_s0
To	uart_byte_rx/data_byte_pre[3]_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C5[0][A]	uart_byte_rx/data_byte_pre[3]_1_s0/CLK
3.510	0.247	tC2Q	RR	2	R7C5[0][A]	uart_byte_rx/data_byte_pre[3]_1_s0/Q
3.512	0.002	tNET	RR	1	R7C5[0][A]	uart_byte_rx/n556_s6/I0
3.788	0.276	tINS	RF	1	R7C5[0][A]	uart_byte_rx/n556_s6/F
3.788	0.000	tNET	FF	1	R7C5[0][A]	uart_byte_rx/data_byte_pre[3]_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C5[0][A]	uart_byte_rx/data_byte_pre[3]_1_s0/CLK
3.263	0.000	tHld		1	R7C5[0][A]	uart_byte_rx/data_byte_pre[3]_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path9

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_byte_rx/data_byte_pre[4]_0_s0
To	uart_byte_rx/data_byte_pre[4]_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R6C11[0][A]	uart_byte_rx/data_byte_pre[4]_0_s0/CLK
3.510	0.247	tC2Q	RR	3	R6C11[0][A]	uart_byte_rx/data_byte_pre[4]_0_s0/Q
3.512	0.002	tNET	RR	1	R6C11[0][A]	uart_byte_rx/n550_s5/I1
3.788	0.276	tINS	RF	1	R6C11[0][A]	uart_byte_rx/n550_s5/F
3.788	0.000	tNET	FF	1	R6C11[0][A]	uart_byte_rx/data_byte_pre[4]_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R6C11[0][A]	uart_byte_rx/data_byte_pre[4]_0_s0/CLK
3.263	0.000	tHld		1	R6C11[0][A]	uart_byte_rx/data_byte_pre[4]_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path10

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_byte_rx/data_byte_pre[4]_1_s0
To	uart_byte_rx/data_byte_pre[4]_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R6C11[1][A]	uart_byte_rx/data_byte_pre[4]_1_s0/CLK
3.510	0.247	tC2Q	RR	2	R6C11[1][A]	uart_byte_rx/data_byte_pre[4]_1_s0/Q
3.512	0.002	tNET	RR	1	R6C11[1][A]	uart_byte_rx/n547_s6/I0
3.788	0.276	tINS	RF	1	R6C11[1][A]	uart_byte_rx/n547_s6/F
3.788	0.000	tNET	FF	1	R6C11[1][A]	uart_byte_rx/data_byte_pre[4]_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R6C11[1][A]	uart_byte_rx/data_byte_pre[4]_1_s0/CLK
3.263	0.000	tHld		1	R6C11[1][A]	uart_byte_rx/data_byte_pre[4]_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path11

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_byte_rx/data_byte_pre[5]_0_s0
To	uart_byte_rx/data_byte_pre[5]_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R5C10[0][A]	uart_byte_rx/data_byte_pre[5]_0_s0/CLK
3.510	0.247	tC2Q	RR	3	R5C10[0][A]	uart_byte_rx/data_byte_pre[5]_0_s0/Q
3.512	0.002	tNET	RR	1	R5C10[0][A]	uart_byte_rx/n541_s5/I1
3.788	0.276	tINS	RF	1	R5C10[0][A]	uart_byte_rx/n541_s5/F
3.788	0.000	tNET	FF	1	R5C10[0][A]	uart_byte_rx/data_byte_pre[5]_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R5C10[0][A]	uart_byte_rx/data_byte_pre[5]_0_s0/CLK
3.263	0.000	tHld		1	R5C10[0][A]	uart_byte_rx/data_byte_pre[5]_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path12

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_byte_rx/data_byte_pre[5]_1_s0
To	uart_byte_rx/data_byte_pre[5]_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R5C10[1][A]	uart_byte_rx/data_byte_pre[5]_1_s0/CLK
3.510	0.247	tC2Q	RR	2	R5C10[1][A]	uart_byte_rx/data_byte_pre[5]_1_s0/Q
3.512	0.002	tNET	RR	1	R5C10[1][A]	uart_byte_rx/n538_s6/I0
3.788	0.276	tINS	RF	1	R5C10[1][A]	uart_byte_rx/n538_s6/F
3.788	0.000	tNET	FF	1	R5C10[1][A]	uart_byte_rx/data_byte_pre[5]_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R5C10[1][A]	uart_byte_rx/data_byte_pre[5]_1_s0/CLK
3.263	0.000	tHld		1	R5C10[1][A]	uart_byte_rx/data_byte_pre[5]_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path13

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_byte_rx/data_byte_pre[6]_0_s0
To	uart_byte_rx/data_byte_pre[6]_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R5C8[0][A]	uart_byte_rx/data_byte_pre[6]_0_s0/CLK
3.510	0.247	tC2Q	RR	3	R5C8[0][A]	uart_byte_rx/data_byte_pre[6]_0_s0/Q
3.512	0.002	tNET	RR	1	R5C8[0][A]	uart_byte_rx/n532_s5/I1
3.788	0.276	tINS	RF	1	R5C8[0][A]	uart_byte_rx/n532_s5/F
3.788	0.000	tNET	FF	1	R5C8[0][A]	uart_byte_rx/data_byte_pre[6]_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R5C8[0][A]	uart_byte_rx/data_byte_pre[6]_0_s0/CLK
3.263	0.000	tHld		1	R5C8[0][A]	uart_byte_rx/data_byte_pre[6]_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path14

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_byte_rx/data_byte_pre[6]_1_s0
To	uart_byte_rx/data_byte_pre[6]_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R5C8[1][A]	uart_byte_rx/data_byte_pre[6]_1_s0/CLK
3.510	0.247	tC2Q	RR	2	R5C8[1][A]	uart_byte_rx/data_byte_pre[6]_1_s0/Q
3.512	0.002	tNET	RR	1	R5C8[1][A]	uart_byte_rx/n529_s6/I0
3.788	0.276	tINS	RF	1	R5C8[1][A]	uart_byte_rx/n529_s6/F
3.788	0.000	tNET	FF	1	R5C8[1][A]	uart_byte_rx/data_byte_pre[6]_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R5C8[1][A]	uart_byte_rx/data_byte_pre[6]_1_s0/CLK
3.263	0.000	tHld		1	R5C8[1][A]	uart_byte_rx/data_byte_pre[6]_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path15

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_byte_rx/data_byte_pre[7]_2_s0
To	uart_byte_rx/data_byte_pre[7]_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C6[1][A]	uart_byte_rx/data_byte_pre[7]_2_s0/CLK
3.510	0.247	tC2Q	RR	2	R7C6[1][A]	uart_byte_rx/data_byte_pre[7]_2_s0/Q
3.512	0.002	tNET	RR	1	R7C6[1][A]	uart_byte_rx/n517_s5/I2
3.788	0.276	tINS	RF	1	R7C6[1][A]	uart_byte_rx/n517_s5/F
3.788	0.000	tNET	FF	1	R7C6[1][A]	uart_byte_rx/data_byte_pre[7]_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C6[1][A]	uart_byte_rx/data_byte_pre[7]_2_s0/CLK
3.263	0.000	tHld		1	R7C6[1][A]	uart_byte_rx/data_byte_pre[7]_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path16

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_byte_rx/START_BIT_0_s0
To	uart_byte_rx/START_BIT_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R6C9[0][A]	uart_byte_rx/START_BIT_0_s0/CLK
3.510	0.247	tC2Q	RR	4	R6C9[0][A]	uart_byte_rx/START_BIT_0_s0/Q
3.512	0.002	tNET	RR	1	R6C9[0][A]	uart_byte_rx/n514_s5/I0
3.788	0.276	tINS	RF	1	R6C9[0][A]	uart_byte_rx/n514_s5/F
3.788	0.000	tNET	FF	1	R6C9[0][A]	uart_byte_rx/START_BIT_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R6C9[0][A]	uart_byte_rx/START_BIT_0_s0/CLK
3.263	0.000	tHld		1	R6C9[0][A]	uart_byte_rx/START_BIT_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path17

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_byte_rx/START_BIT_1_s0
To	uart_byte_rx/START_BIT_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R6C10[0][A]	uart_byte_rx/START_BIT_1_s0/CLK
3.510	0.247	tC2Q	RR	3	R6C10[0][A]	uart_byte_rx/START_BIT_1_s0/Q
3.512	0.002	tNET	RR	1	R6C10[0][A]	uart_byte_rx/n511_s6/I0
3.788	0.276	tINS	RF	1	R6C10[0][A]	uart_byte_rx/n511_s6/F
3.788	0.000	tNET	FF	1	R6C10[0][A]	uart_byte_rx/START_BIT_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R6C10[0][A]	uart_byte_rx/START_BIT_1_s0/CLK
3.263	0.000	tHld		1	R6C10[0][A]	uart_byte_rx/START_BIT_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path18

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_byte_rx/div_cnt_10_s0
To	uart_byte_rx/div_cnt_10_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C7[1][A]	uart_byte_rx/div_cnt_10_s0/CLK
3.510	0.247	tC2Q	RR	3	R8C7[1][A]	uart_byte_rx/div_cnt_10_s0/Q
3.512	0.002	tNET	RR	1	R8C7[1][A]	uart_byte_rx/n94_s2/I2
3.788	0.276	tINS	RF	1	R8C7[1][A]	uart_byte_rx/n94_s2/F
3.788	0.000	tNET	FF	1	R8C7[1][A]	uart_byte_rx/div_cnt_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C7[1][A]	uart_byte_rx/div_cnt_10_s0/CLK
3.263	0.000	tHld		1	R8C7[1][A]	uart_byte_rx/div_cnt_10_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path19

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_byte_tx/div_cnt_15_s0
To	uart_byte_tx/div_cnt_15_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C15[0][A]	uart_byte_tx/div_cnt_15_s0/CLK
3.510	0.247	tC2Q	RR	2	R7C15[0][A]	uart_byte_tx/div_cnt_15_s0/Q
3.512	0.002	tNET	RR	1	R7C15[0][A]	uart_byte_tx/n110_s2/I2
3.788	0.276	tINS	RF	1	R7C15[0][A]	uart_byte_tx/n110_s2/F
3.788	0.000	tNET	FF	1	R7C15[0][A]	uart_byte_tx/div_cnt_15_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C15[0][A]	uart_byte_tx/div_cnt_15_s0/CLK
3.263	0.000	tHld		1	R7C15[0][A]	uart_byte_tx/div_cnt_15_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path20

Path Summary:

Slack	0.525
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_byte_rx/bps_cnt_0_s1
To	uart_byte_rx/bps_cnt_0_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C9[0][A]	uart_byte_rx/bps_cnt_0_s1/CLK
3.510	0.247	tC2Q	RR	6	R8C9[0][A]	uart_byte_rx/bps_cnt_0_s1/Q
3.513	0.003	tNET	RR	1	R8C9[0][A]	uart_byte_rx/n156_s3/I0
3.788	0.276	tINS	RF	1	R8C9[0][A]	uart_byte_rx/n156_s3/F
3.788	0.000	tNET	FF	1	R8C9[0][A]	uart_byte_rx/bps_cnt_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C9[0][A]	uart_byte_rx/bps_cnt_0_s1/CLK
3.263	0.000	tHld		1	R8C9[0][A]	uart_byte_rx/bps_cnt_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path21

Path Summary:

Slack	0.525
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_byte_rx/data_byte_pre[0]_0_s0
To	uart_byte_rx/data_byte_pre[0]_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C6[0][A]	uart_byte_rx/data_byte_pre[0]_0_s0/CLK
3.510	0.247	tC2Q	RR	3	R7C6[0][A]	uart_byte_rx/data_byte_pre[0]_0_s0/Q
3.513	0.003	tNET	RR	1	R7C6[0][A]	uart_byte_rx/n586_s5/I1
3.788	0.276	tINS	RF	1	R7C6[0][A]	uart_byte_rx/n586_s5/F
3.788	0.000	tNET	FF	1	R7C6[0][A]	uart_byte_rx/data_byte_pre[0]_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C6[0][A]	uart_byte_rx/data_byte_pre[0]_0_s0/CLK
3.263	0.000	tHld		1	R7C6[0][A]	uart_byte_rx/data_byte_pre[0]_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path22

Path Summary:

Slack	0.525
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_byte_rx/div_cnt_6_s0
To	uart_byte_rx/div_cnt_6_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C5[0][A]	uart_byte_rx/div_cnt_6_s0/CLK
3.510	0.247	tC2Q	RR	4	R8C5[0][A]	uart_byte_rx/div_cnt_6_s0/Q
3.513	0.003	tNET	RR	1	R8C5[0][A]	uart_byte_rx/n98_s2/I2
3.788	0.276	tINS	RF	1	R8C5[0][A]	uart_byte_rx/n98_s2/F
3.788	0.000	tNET	FF	1	R8C5[0][A]	uart_byte_rx/div_cnt_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C5[0][A]	uart_byte_rx/div_cnt_6_s0/CLK
3.263	0.000	tHld		1	R8C5[0][A]	uart_byte_rx/div_cnt_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path23

Path Summary:

Slack	0.525
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_byte_tx/bps_cnt_3_s1
To	uart_byte_tx/bps_cnt_3_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R6C16[0][A]	uart_byte_tx/bps_cnt_3_s1/CLK
3.510	0.247	tC2Q	RR	4	R6C16[0][A]	uart_byte_tx/bps_cnt_3_s1/Q
3.513	0.003	tNET	RR	1	R6C16[0][A]	uart_byte_tx/n157_s2/I3
3.788	0.276	tINS	RF	1	R6C16[0][A]	uart_byte_tx/n157_s2/F
3.788	0.000	tNET	FF	1	R6C16[0][A]	uart_byte_tx/bps_cnt_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R6C16[0][A]	uart_byte_tx/bps_cnt_3_s1/CLK
3.263	0.000	tHld		1	R6C16[0][A]	uart_byte_tx/bps_cnt_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path24

Path Summary:

Slack	0.525
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_byte_tx/div_cnt_8_s0
To	uart_byte_tx/div_cnt_8_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C13[1][A]	uart_byte_tx/div_cnt_8_s0/CLK
3.510	0.247	tC2Q	RR	6	R8C13[1][A]	uart_byte_tx/div_cnt_8_s0/Q
3.513	0.003	tNET	RR	1	R8C13[1][A]	uart_byte_tx/n117_s4/I0
3.788	0.276	tINS	RF	1	R8C13[1][A]	uart_byte_tx/n117_s4/F
3.788	0.000	tNET	FF	1	R8C13[1][A]	uart_byte_tx/div_cnt_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C13[1][A]	uart_byte_tx/div_cnt_8_s0/CLK
3.263	0.000	tHld		1	R8C13[1][A]	uart_byte_tx/div_cnt_8_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path25

Path Summary:

Slack	0.525
Data Arrival Time	3.788
Data Required Time	3.263
From	uart_byte_tx/div_cnt_14_s0
To	uart_byte_tx/div_cnt_14_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R6C14[0][A]	uart_byte_tx/div_cnt_14_s0/CLK
3.510	0.247	tC2Q	RR	3	R6C14[0][A]	uart_byte_tx/div_cnt_14_s0/Q
3.513	0.003	tNET	RR	1	R6C14[0][A]	uart_byte_tx/n111_s2/I2
3.788	0.276	tINS	RF	1	R6C14[0][A]	uart_byte_tx/n111_s2/F
3.788	0.000	tNET	FF	1	R6C14[0][A]	uart_byte_tx/div_cnt_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	109	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R6C14[0][A]	uart_byte_tx/div_cnt_14_s0/CLK
3.263	0.000	tHld		1	R6C14[0][A]	uart_byte_tx/div_cnt_14_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	clk
Objects:	data_byte_tx_6_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	data_byte_tx_6_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	data_byte_tx_6_s0/CLK

MPW2

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	clk
Objects:	data_byte_tx_5_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	data_byte_tx_5_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	data_byte_tx_5_s0/CLK

MPW3

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	clk
Objects:	data_byte_tx_3_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	data_byte_tx_3_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	data_byte_tx_3_s0/CLK

MPW4

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	clk
Objects:	send_en_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	send_en_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	send_en_s0/CLK

MPW5

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	clk
Objects:	uart_byte_tx/data_byte_reg_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	uart_byte_tx/data_byte_reg_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	uart_byte_tx/data_byte_reg_1_s0/CLK

MPW6

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	clk
Objects:	uart_byte_tx/div_cnt_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	uart_byte_tx/div_cnt_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	uart_byte_tx/div_cnt_1_s0/CLK

MPW7

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	clk
Objects:	uart_byte_rx/START_BIT_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	uart_byte_rx/START_BIT_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	uart_byte_rx/START_BIT_0_s0/CLK

MPW8

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	clk
Objects:	uart_byte_rx/START_BIT_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	uart_byte_rx/START_BIT_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	uart_byte_rx/START_BIT_1_s0/CLK

MPW9

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	clk
Objects:	uart_byte_tx/div_cnt_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	uart_byte_tx/div_cnt_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	uart_byte_tx/div_cnt_2_s0/CLK

MPW10

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	clk
Objects:	uart_byte_rx/START_BIT_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	uart_byte_rx/START_BIT_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	uart_byte_rx/START_BIT_2_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
109	clk_d	14.315	0.195
31	uart_byte_rx/uart_rx_sync2	15.401	2.425
16	uart_byte_rx/uart_state	17.031	1.605
16	uart_byte_tx/uart_state	17.878	0.877
12	uart_byte_rx/bps_cnt[4]	14.662	1.223
12	uart_byte_rx/bps_cnt[5]	15.102	0.627
11	uart_byte_rx/bps_clk	16.607	1.698
11	uart_byte_rx/bps_cnt[6]	15.420	0.627
10	uart_byte_tx/bps_cnt[0]	15.324	0.322
10	send_en	18.285	1.079

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R2C2	100.00%
R2C3	100.00%
R2C10	100.00%
R2C11	100.00%
R3C9	100.00%
R5C5	100.00%
R8C15	100.00%
R16C13	100.00%
R18C19	100.00%
R16C12	100.00%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command