//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
//All rights reserved.


1. PnR Messages

  <Report Title>: PnR Report
  <Design File>: C:\quanggit_lab\example_code\UART_RX_1BYTE\impl\gwsynthesis\uart_rx.vg
  <Physical Constraints File>: C:\quanggit_lab\example_code\UART_RX_1BYTE\src\uart_rx.cst
  <Timing Constraints File>: ---
  <Tool Version>: V1.9.11.03 (64-bit)
  <Part Number>: GW1N-UV1P5QN48XFC7/I6
  <Device>: GW1N-1P5
  <Device Version>: C
  <Created Time>:Mon Jul 21 10:56:34 2025


2. PnR Details

  Running placement:
    Placement Phase 0: CPU time = 0h 0m 0.006s, Elapsed time = 0h 0m 0.006s
    Placement Phase 1: CPU time = 0h 0m 0.023s, Elapsed time = 0h 0m 0.023s
    Placement Phase 2: CPU time = 0h 0m 0.009s, Elapsed time = 0h 0m 0.009s
    Placement Phase 3: CPU time = 0h 0m 0.472s, Elapsed time = 0h 0m 0.471s
    Total Placement: CPU time = 0h 0m 0.51s, Elapsed time = 0h 0m 0.509s
 Running routing:
    Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
    Routing Phase 1: CPU time = 0h 0m 0.029s, Elapsed time = 0h 0m 0.029s
    Routing Phase 2: CPU time = 0h 0m 0.051s, Elapsed time = 0h 0m 0.05s
    Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
    Total Routing: CPU time = 0h 0m 0.08s, Elapsed time = 0h 0m 0.079s
 Generate output files:
    CPU time = 0h 0m 0.167s, Elapsed time = 0h 0m 0.167s

 Total Time and Memory Usage: CPU time = 0h 0m 0.757s, Elapsed time = 0h 0m 0.755s, Peak memory usage = 250MB


3. Resource Usage Summary

  --------------------------------------------------------------------------------
  Resources                   | Usage                               | Utilization
  --------------------------------------------------------------------------------
  Logic                       | 182/1584                            |  12%
    --LUT,ALU,ROM16           | 182(182 LUT, 0 ALU, 0 ROM16)        | -
    --SSRAM(RAM16)            | 0                                   | -
  Register                    | 109/1704                            |  7%
    --Logic Register as Latch | 0/1584                              |  0%
    --Logic Register as FF    | 107/1584                            |  7%
    --I/O Register as Latch   | 0/120                               |  0%
    --I/O Register as FF      | 2/120                               |  2%
  I/O Port                    | 4/40                                |  10%
  I/O Buf                     | 4                                   | -
    --Input Buf               | 3                                   | -
    --Output Buf              | 1                                   | -
    --Inout Buf               | 0                                   | -
  ================================================================================



4. I/O Bank Usage Summary

  --------------------------------------
  I/O Bank  | Usage       | Utilization 
  --------------------------------------
  bank 0   | 0/10        | 0%          
  bank 1   | 3/10        | 30%         
  bank 2   | 0/10        | 0%          
  bank 3   | 0/2         | 0%          
  bank 4   | 0/4         | 0%          
  bank 5   | 1/4         | 25%         
  ======================================


5. Clock Resource Usage Summary

  ------------------------------------------
  Clock Resource| Usage         | Utilization 
  ------------------------------------------
  PRIMARY       | 1/8           | 13%
  LW            | 1/8           | 13%
  GCLK_PIN      | 2/6           | 34%
  ==========================================


6. Global Clock Signals

  -------------------------------------------
  Signal         | Global Clock   | Location
  -------------------------------------------
  clk_d          | PRIMARY        |  LEFT RIGHT
  reset_n_d      | LW             |  -
  ===========================================


7. Pinout by Port Name

------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Port Name  | Diff Pair | Loc./Bank     | Constraint | Dir.  | Site     | CFG             | IO Type    | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref       | Single Resistor | Diff Resistor | BankVccio 
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
clk        | -         | 4/5           | Y          | in    | IOL6[A]  | GCLKT_7         | LVCMOS18   | NA    | NONE      | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8       
reset_n    | -         | 35/1          | Y          | in    | IOR1[B]  | -               | LVCMOS18   | NA    | NONE      | ON        | NONE       | NA         | NA         | OFF             | NA            | 1.8       
uart_rx    | -         | 33/1          | Y          | in    | IOR11[B] | GCLKC_2         | LVCMOS18   | NA    | NONE      | ON        | NONE       | NA         | NA         | OFF             | NA            | 1.8       
uart_tx    | -         | 34/1          | Y          | out   | IOR11[A] | GCLKT_2         | LVCMOS18   | 8     | NONE      | NA        | NA         | OFF        | NA         | NA              | NA            | 1.8       
==================================================================================================================================================================================================================




8. All Package Pins

-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Loc./Bank| Signal   | Dir.  | Site     | CFG             | IO Type  | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref       | Single Resistor | Diff Resistor | Bank Vccio
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
48/0     | -        | out   | IOT7[A]  | TDO             | LVCMOS18 | 8     | NONE      | NA        | NA         | OFF        | NA         | NA              | NA            | 1.8  
47/0     | -        | in    | IOT7[B]  | TDI             | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
45/0     | -        | in    | IOT9[A]  | TCK             | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
44/0     | -        | in    | IOT9[B]  | TMS             | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
43/0     | -        | in    | IOT14[A] | GCLKT_1         | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
42/0     | -        | in    | IOT14[B] | GCLKC_1         | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
41/0     | -        | in    | IOT15[A] | -               | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
40/0     | -        | in    | IOT15[B] | -               | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
38/0     | -        | in    | IOT18[A] | READY           | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
37/0     | -        | in    | IOT18[B] | DONE            | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
14/2     | -        | in    | IOB2[A]  | -               | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
15/2     | -        | in    | IOB2[B]  | -               | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
16/2     | -        | in    | IOB5[A]  | SCLK            | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
17/2     | -        | in    | IOB5[B]  | SO              | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
18/2     | -        | in    | IOB7[A]  | GCLKT_4         | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
19/2     | -        | in    | IOB7[B]  | GCLKC_4         | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
20/2     | -        | in    | IOB9[A]  | GCLKT_3         | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
21/2     | -        | in    | IOB9[B]  | GCLKC_3         | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
23/2     | -        | in    | IOB18[A] | SSPI_CS_N       | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
24/2     | -        | in    | IOB18[B] | SI              | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
2/5      | -        | in    | IOL4[A]  | LPLL_T_fb       | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
3/5      | -        | in    | IOL4[B]  | LPLL_C_fb       | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
4/5      | clk      | in    | IOL6[A]  | GCLKT_7         | LVCMOS18 | NA    | NONE      | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
5/5      | -        | in    | IOL6[B]  | GCLKC_7         | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
7/4      | -        | in    | IOL11[A] | -               | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
8/4      | -        | in    | IOL11[B] | -               | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
9/4      | -        | in    | IOL12[A] | GCLKT_6         | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
10/4     | -        | in    | IOL12[B] | GCLKC_6         | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
11/3     | -        | in    | IOL17[A] | -               | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
12/3     | -        | in    | IOL17[B] | -               | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
36/1     | -        | in    | IOR1[A]  | -               | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
35/1     | reset_n  | in    | IOR1[B]  | -               | LVCMOS18 | NA    | NONE      | ON        | NONE       | NA         | NA         | OFF             | NA            | 1.8  
34/1     | uart_tx  | out   | IOR11[A] | GCLKT_2         | LVCMOS18 | 8     | NONE      | NA        | NA         | OFF        | NA         | NA              | NA            | 1.8  
33/1     | uart_rx  | in    | IOR11[B] | GCLKC_2         | LVCMOS18 | NA    | NONE      | ON        | NONE       | NA         | NA         | OFF             | NA            | 1.8  
32/1     | -        | in    | IOR13[A] | -               | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
31/1     | -        | in    | IOR13[B] | -               | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
29/1     | -        | in    | IOR15[A] | -               | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
28/1     | -        | in    | IOR15[B] | -               | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
27/1     | -        | in    | IOR17[A] | -               | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
26/1     | -        | in    | IOR17[B] | -               | LVCMOS18 | NA    | UP        | ON        | NONE       | NA         | NA         | NA              | NA            | 1.8  
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
=====================================================================================================================================================================================


