Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\quanggit_lab\example_code\UART_RX_1BYTE\src\uart_byte_rx.v
C:\quanggit_lab\example_code\UART_RX_1BYTE\src\uart_byte_tx.v
C:\quanggit_lab\example_code\UART_RX_1BYTE\src\uart_rx_test.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.03 (64-bit)
Part Number GW1N-UV1P5QN48XFC7/I6
Device GW1N-1P5
Device Version C
Created Time Mon Jul 21 10:56:33 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module uart_rx_test
Synthesis Process Running parser:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.046s, Peak memory usage = 250.586MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 250.586MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 250.586MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 250.586MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 250.586MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 250.586MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 250.586MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 250.586MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 250.586MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 250.586MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 250.586MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.351s, Peak memory usage = 250.586MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.045s, Peak memory usage = 250.586MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 250.586MB
Total Time and Memory Usage CPU time = 0h 0m 0.418s, Elapsed time = 0h 0m 0.471s, Peak memory usage = 250.586MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 4
I/O Buf 4
    IBUF 3
    OBUF 1
Register 109
    DFFP 1
    DFFC 42
    DFFCE 66
LUT 182
    LUT2 37
    LUT3 44
    LUT4 101
INV 1
    INV 1

Resource Utilization Summary

Resource Usage Utilization
Logic 183(183 LUT, 0 ALU) / 1584 12%
Register 109 / 1704 7%
  --Register as Latch 0 / 1704 0%
  --Register as FF 109 / 1704 7%
BSRAM 0 / 4 0%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk Base 20.000 50.000 0.000 10.000 clk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 50.000(MHz) 136.739(MHz) 4 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 12.687
Data Arrival Time 7.555
Data Required Time 20.242
From uart_byte_tx/data_byte_reg_5_s0
To uart_byte_tx/uart_tx_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 109 clk_ibuf/O
0.538 0.538 tNET RR 1 uart_byte_tx/data_byte_reg_5_s0/CLK
0.878 0.340 tC2Q RF 1 uart_byte_tx/data_byte_reg_5_s0/Q
1.589 0.711 tNET FF 1 uart_byte_tx/n177_s34/I1
2.403 0.814 tINS FF 1 uart_byte_tx/n177_s34/F
3.115 0.711 tNET FF 1 uart_byte_tx/n177_s22/I1
3.225 0.110 tINS FF 1 uart_byte_tx/n177_s22/O
3.936 0.711 tNET FF 1 uart_byte_tx/n177_s35/I0
4.701 0.765 tINS FF 1 uart_byte_tx/n177_s35/F
5.413 0.711 tNET FF 1 uart_byte_tx/n177_s26/I0
5.523 0.110 tINS FF 1 uart_byte_tx/n177_s26/O
6.234 0.711 tNET FF 1 uart_byte_tx/n177_s28/I2
6.843 0.609 tINS FF 1 uart_byte_tx/n177_s28/F
7.555 0.711 tNET FF 1 uart_byte_tx/uart_tx_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 109 clk_ibuf/O
20.538 0.538 tNET RR 1 uart_byte_tx/uart_tx_s0/CLK
20.242 -0.296 tSu 1 uart_byte_tx/uart_tx_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 2.409, 34.332%; route: 4.268, 60.828%; tC2Q: 0.340, 4.840%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 2

Path Summary:
Slack 14.075
Data Arrival Time 6.166
Data Required Time 20.242
From uart_byte_rx/bps_cnt_7_s1
To uart_byte_rx/bps_cnt_0_s1
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 109 clk_ibuf/O
0.538 0.538 tNET RR 1 uart_byte_rx/bps_cnt_7_s1/CLK
0.878 0.340 tC2Q RF 9 uart_byte_rx/bps_cnt_7_s1/Q
1.589 0.711 tNET FF 1 uart_byte_rx/bps_cnt_7_s6/I1
2.403 0.814 tINS FF 5 uart_byte_rx/bps_cnt_7_s6/F
3.115 0.711 tNET FF 1 uart_byte_rx/bps_cnt_7_s4/I1
3.929 0.814 tINS FF 5 uart_byte_rx/bps_cnt_7_s4/F
4.640 0.711 tNET FF 1 uart_byte_rx/n156_s3/I1
5.455 0.814 tINS FF 1 uart_byte_rx/n156_s3/F
6.166 0.711 tNET FF 1 uart_byte_rx/bps_cnt_0_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 109 clk_ibuf/O
20.538 0.538 tNET RR 1 uart_byte_rx/bps_cnt_0_s1/CLK
20.242 -0.296 tSu 1 uart_byte_rx/bps_cnt_0_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 2.443, 43.408%; route: 2.845, 50.558%; tC2Q: 0.340, 6.034%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 3

Path Summary:
Slack 14.075
Data Arrival Time 6.166
Data Required Time 20.242
From uart_byte_rx/div_cnt_5_s0
To uart_byte_rx/div_cnt_9_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 109 clk_ibuf/O
0.538 0.538 tNET RR 1 uart_byte_rx/div_cnt_5_s0/CLK
0.878 0.340 tC2Q RF 5 uart_byte_rx/div_cnt_5_s0/Q
1.589 0.711 tNET FF 1 uart_byte_rx/n96_s4/I1
2.403 0.814 tINS FF 3 uart_byte_rx/n96_s4/F
3.115 0.711 tNET FF 1 uart_byte_rx/n96_s3/I1
3.929 0.814 tINS FF 2 uart_byte_rx/n96_s3/F
4.640 0.711 tNET FF 1 uart_byte_rx/n95_s2/I1
5.455 0.814 tINS FF 1 uart_byte_rx/n95_s2/F
6.166 0.711 tNET FF 1 uart_byte_rx/div_cnt_9_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 109 clk_ibuf/O
20.538 0.538 tNET RR 1 uart_byte_rx/div_cnt_9_s0/CLK
20.242 -0.296 tSu 1 uart_byte_rx/div_cnt_9_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 2.443, 43.408%; route: 2.845, 50.558%; tC2Q: 0.340, 6.034%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 4

Path Summary:
Slack 14.075
Data Arrival Time 6.166
Data Required Time 20.242
From uart_byte_rx/div_cnt_1_s0
To uart_byte_rx/div_cnt_11_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 109 clk_ibuf/O
0.538 0.538 tNET RR 1 uart_byte_rx/div_cnt_1_s0/CLK
0.878 0.340 tC2Q RF 6 uart_byte_rx/div_cnt_1_s0/Q
1.589 0.711 tNET FF 1 uart_byte_rx/n100_s3/I1
2.403 0.814 tINS FF 7 uart_byte_rx/n100_s3/F
3.115 0.711 tNET FF 1 uart_byte_rx/n93_s3/I1
3.929 0.814 tINS FF 5 uart_byte_rx/n93_s3/F
4.640 0.711 tNET FF 1 uart_byte_rx/n93_s2/I1
5.455 0.814 tINS FF 1 uart_byte_rx/n93_s2/F
6.166 0.711 tNET FF 1 uart_byte_rx/div_cnt_11_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 109 clk_ibuf/O
20.538 0.538 tNET RR 1 uart_byte_rx/div_cnt_11_s0/CLK
20.242 -0.296 tSu 1 uart_byte_rx/div_cnt_11_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 2.443, 43.408%; route: 2.845, 50.558%; tC2Q: 0.340, 6.034%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 5

Path Summary:
Slack 14.075
Data Arrival Time 6.166
Data Required Time 20.242
From uart_byte_rx/div_cnt_1_s0
To uart_byte_rx/div_cnt_12_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 109 clk_ibuf/O
0.538 0.538 tNET RR 1 uart_byte_rx/div_cnt_1_s0/CLK
0.878 0.340 tC2Q RF 6 uart_byte_rx/div_cnt_1_s0/Q
1.589 0.711 tNET FF 1 uart_byte_rx/n100_s3/I1
2.403 0.814 tINS FF 7 uart_byte_rx/n100_s3/F
3.115 0.711 tNET FF 1 uart_byte_rx/n93_s3/I1
3.929 0.814 tINS FF 5 uart_byte_rx/n93_s3/F
4.640 0.711 tNET FF 1 uart_byte_rx/n92_s2/I1
5.455 0.814 tINS FF 1 uart_byte_rx/n92_s2/F
6.166 0.711 tNET FF 1 uart_byte_rx/div_cnt_12_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 109 clk_ibuf/O
20.538 0.538 tNET RR 1 uart_byte_rx/div_cnt_12_s0/CLK
20.242 -0.296 tSu 1 uart_byte_rx/div_cnt_12_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 2.443, 43.408%; route: 2.845, 50.558%; tC2Q: 0.340, 6.034%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%