Timing Messages

Report Title	Timing Analysis Report
Design File	C:\Users\phutruong\Documents\GitHub\example_code\PWM_LED\impl\gwsynthesis\pwm_gen.vg
Physical Constraints File	C:\Users\phutruong\Documents\GitHub\example_code\PWM_LED\src\pwm_gen.cst
Timing Constraint File	---
Tool Version	V1.9.11.01 (64-bit)
Part Number	GW1N-UV1P5QN48XFC7/I6
Device	GW1N-1P5
Device Version	C
Created Time	Wed Nov 19 11:01:59 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 1.71V 85C C7/I6
Hold Delay Model	Fast 3.6V 0C C7/I6
Numbers of Paths Analyzed	160
Numbers of Endpoints Analyzed	148
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	clk	Base	20.000	50.000	0.000	10.000			clk_ibuf/I

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk	50.000(MHz)	124.172(MHz)	7	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk	Setup	0.000	0
clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Data Delay
1	11.947	pwm_gen_inst/pwm_gen_cnt_0_s0/Q	pwm_gen_inst/pwm_out_s0/D	clk:[R]	clk:[R]	20.000	7.757
2	13.433	pwm_gen_inst/pwm_gen_cnt_20_s0/Q	pwm_gen_inst/pwm_gen_cnt_1_s0/D	clk:[R]	clk:[R]	20.000	6.270
3	13.433	pwm_gen_inst/pwm_gen_cnt_20_s0/Q	pwm_gen_inst/pwm_gen_cnt_10_s0/D	clk:[R]	clk:[R]	20.000	6.270
4	13.447	pwm_gen_inst/pwm_gen_cnt_20_s0/Q	pwm_gen_inst/pwm_gen_cnt_11_s0/D	clk:[R]	clk:[R]	20.000	6.257
5	13.495	pwm_gen_inst/pwm_gen_cnt_20_s0/Q	pwm_gen_inst/pwm_gen_cnt_9_s0/D	clk:[R]	clk:[R]	20.000	6.209
6	13.495	pwm_gen_inst/pwm_gen_cnt_20_s0/Q	pwm_gen_inst/pwm_gen_cnt_24_s0/D	clk:[R]	clk:[R]	20.000	6.209
7	13.496	pwm_gen_inst/pwm_gen_cnt_20_s0/Q	pwm_gen_inst/pwm_gen_cnt_8_s0/D	clk:[R]	clk:[R]	20.000	6.207
8	13.506	pwm_gen_inst/pwm_gen_cnt_20_s0/Q	pwm_gen_inst/pwm_gen_cnt_5_s0/D	clk:[R]	clk:[R]	20.000	6.197
9	13.506	pwm_gen_inst/pwm_gen_cnt_20_s0/Q	pwm_gen_inst/pwm_gen_cnt_4_s0/D	clk:[R]	clk:[R]	20.000	6.197
10	13.506	pwm_gen_inst/pwm_gen_cnt_20_s0/Q	pwm_gen_inst/pwm_gen_cnt_2_s0/D	clk:[R]	clk:[R]	20.000	6.197
11	13.762	pwm_gen_inst/pwm_gen_cnt_11_s0/Q	pwm_gen_inst/pwm_gen_cnt_29_s0/D	clk:[R]	clk:[R]	20.000	5.941
12	13.796	pwm_gen_inst/pwm_gen_cnt_20_s0/Q	pwm_gen_inst/pwm_gen_cnt_7_s0/D	clk:[R]	clk:[R]	20.000	5.908
13	13.796	pwm_gen_inst/pwm_gen_cnt_20_s0/Q	pwm_gen_inst/pwm_gen_cnt_12_s0/D	clk:[R]	clk:[R]	20.000	5.908
14	13.818	pwm_gen_inst/pwm_gen_cnt_11_s0/Q	pwm_gen_inst/pwm_gen_cnt_25_s0/D	clk:[R]	clk:[R]	20.000	5.885
15	13.845	pwm_gen_inst/pwm_gen_cnt_20_s0/Q	pwm_gen_inst/pwm_gen_cnt_6_s0/D	clk:[R]	clk:[R]	20.000	5.858
16	13.857	pwm_gen_inst/pwm_gen_cnt_20_s0/Q	pwm_gen_inst/pwm_gen_cnt_3_s0/D	clk:[R]	clk:[R]	20.000	5.847
17	13.857	pwm_gen_inst/pwm_gen_cnt_20_s0/Q	pwm_gen_inst/pwm_gen_cnt_0_s0/D	clk:[R]	clk:[R]	20.000	5.847
18	13.872	pwm_gen_inst/pwm_gen_cnt_20_s0/Q	pwm_gen_inst/pwm_gen_cnt_22_s0/D	clk:[R]	clk:[R]	20.000	5.832
19	13.872	pwm_gen_inst/pwm_gen_cnt_20_s0/Q	pwm_gen_inst/pwm_gen_cnt_18_s0/D	clk:[R]	clk:[R]	20.000	5.832
20	13.915	pwm_gen_inst/pwm_gen_cnt_11_s0/Q	pwm_gen_inst/pwm_gen_cnt_21_s0/D	clk:[R]	clk:[R]	20.000	5.789
21	13.998	pwm_gen_inst/pwm_gen_cnt_11_s0/Q	pwm_gen_inst/pwm_gen_cnt_20_s0/D	clk:[R]	clk:[R]	20.000	5.705
22	14.008	pwm_gen_inst/pwm_gen_cnt_20_s0/Q	pwm_gen_inst/pwm_gen_cnt_23_s0/D	clk:[R]	clk:[R]	20.000	5.696
23	14.008	pwm_gen_inst/pwm_gen_cnt_20_s0/Q	pwm_gen_inst/pwm_gen_cnt_16_s0/D	clk:[R]	clk:[R]	20.000	5.696
24	14.052	pwm_gen_inst/pwm_gen_cnt_20_s0/Q	pwm_gen_inst/pwm_gen_cnt_17_s0/D	clk:[R]	clk:[R]	20.000	5.652
25	14.052	pwm_gen_inst/pwm_gen_cnt_20_s0/Q	pwm_gen_inst/pwm_gen_cnt_19_s0/D	clk:[R]	clk:[R]	20.000	5.652

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Data Delay
1	0.524	pwm_gen_inst/pwm_gen_cnt_21_s0/Q	pwm_gen_inst/pwm_gen_cnt_21_s0/D	clk:[R]	clk:[R]	0.524
2	0.524	pwm_gen_inst/pwm_gen_cnt_25_s0/Q	pwm_gen_inst/pwm_gen_cnt_25_s0/D	clk:[R]	clk:[R]	0.524
3	0.524	t500ms_dly_cnt_3_s0/Q	t500ms_dly_cnt_3_s0/D	clk:[R]	clk:[R]	0.524
4	0.525	pwm_gen_inst/pwm_gen_cnt_0_s0/Q	pwm_gen_inst/pwm_gen_cnt_0_s0/D	clk:[R]	clk:[R]	0.525
5	0.525	pwm_gen_inst/pwm_gen_cnt_31_s0/Q	pwm_gen_inst/pwm_gen_cnt_31_s0/D	clk:[R]	clk:[R]	0.525
6	0.525	pwm_gen_inst/pwm_gen_cnt_2_s0/Q	pwm_gen_inst/pwm_gen_cnt_2_s0/D	clk:[R]	clk:[R]	0.525
7	0.525	pwm_gen_inst/pwm_gen_cnt_12_s0/Q	pwm_gen_inst/pwm_gen_cnt_12_s0/D	clk:[R]	clk:[R]	0.525
8	0.525	pwm_gen_inst/pwm_gen_cnt_22_s0/Q	pwm_gen_inst/pwm_gen_cnt_22_s0/D	clk:[R]	clk:[R]	0.525
9	0.525	pwm_gen_inst/pwm_gen_cnt_28_s0/Q	pwm_gen_inst/pwm_gen_cnt_28_s0/D	clk:[R]	clk:[R]	0.525
10	0.525	pwm_gen_inst/pwm_gen_cnt_30_s0/Q	pwm_gen_inst/pwm_gen_cnt_30_s0/D	clk:[R]	clk:[R]	0.525
11	0.525	t500ms_dly_cnt_0_s0/Q	t500ms_dly_cnt_0_s0/D	clk:[R]	clk:[R]	0.525
12	0.525	t500ms_dly_cnt_11_s0/Q	t500ms_dly_cnt_11_s0/D	clk:[R]	clk:[R]	0.525
13	0.525	t500ms_dly_cnt_15_s0/Q	t500ms_dly_cnt_15_s0/D	clk:[R]	clk:[R]	0.525
14	0.525	t500ms_dly_cnt_17_s0/Q	t500ms_dly_cnt_17_s0/D	clk:[R]	clk:[R]	0.525
15	0.526	pwm_gen_inst/pwm_gen_cnt_27_s0/Q	pwm_gen_inst/pwm_gen_cnt_27_s0/D	clk:[R]	clk:[R]	0.526
16	0.526	t500ms_dly_cnt_4_s0/Q	t500ms_dly_cnt_4_s0/D	clk:[R]	clk:[R]	0.526
17	0.526	t500ms_dly_cnt_8_s0/Q	t500ms_dly_cnt_8_s0/D	clk:[R]	clk:[R]	0.526
18	0.526	t500ms_dly_cnt_21_s0/Q	t500ms_dly_cnt_21_s0/D	clk:[R]	clk:[R]	0.526
19	0.527	pwm_gen_inst/pwm_gen_cnt_4_s0/Q	pwm_gen_inst/pwm_gen_cnt_4_s0/D	clk:[R]	clk:[R]	0.527
20	0.527	pwm_gen_inst/pwm_gen_cnt_9_s0/Q	pwm_gen_inst/pwm_gen_cnt_9_s0/D	clk:[R]	clk:[R]	0.527
21	0.527	t500ms_dly_cnt_20_s0/Q	t500ms_dly_cnt_20_s0/D	clk:[R]	clk:[R]	0.527
22	0.661	t500ms_dly_cnt_14_s0/Q	t500ms_dly_cnt_14_s0/D	clk:[R]	clk:[R]	0.661
23	0.662	pwm_gen_inst/pwm_gen_cnt_6_s0/Q	pwm_gen_inst/pwm_gen_cnt_6_s0/D	clk:[R]	clk:[R]	0.662
24	0.662	pwm_gen_inst/pwm_gen_cnt_10_s0/Q	pwm_gen_inst/pwm_gen_cnt_10_s0/D	clk:[R]	clk:[R]	0.662
25	0.662	pwm_gen_inst/pwm_gen_cnt_17_s0/Q	pwm_gen_inst/pwm_gen_cnt_17_s0/D	clk:[R]	clk:[R]	0.662

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	6.948	7.874	0.926	High Pulse Width	clk	t500ms_dly_cnt_23_s0
2	6.948	7.874	0.926	High Pulse Width	clk	t500ms_dly_cnt_22_s0
3	6.948	7.874	0.926	High Pulse Width	clk	t500ms_dly_cnt_20_s0
4	6.948	7.874	0.926	High Pulse Width	clk	t500ms_dly_cnt_16_s0
5	6.948	7.874	0.926	High Pulse Width	clk	t500ms_dly_cnt_8_s0
6	6.948	7.874	0.926	High Pulse Width	clk	counter_ccr_8_s0
7	6.948	7.874	0.926	High Pulse Width	clk	pwm_gen_inst/pwm_gen_cnt_6_s0
8	6.948	7.874	0.926	High Pulse Width	clk	pwm_gen_inst/pwm_gen_cnt_7_s0
9	6.948	7.874	0.926	High Pulse Width	clk	counter_ccr_9_s0
10	6.948	7.874	0.926	High Pulse Width	clk	pwm_gen_inst/pwm_gen_cnt_8_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	11.947
Data Arrival Time	12.168
Data Required Time	24.114
From	pwm_gen_inst/pwm_gen_cnt_0_s0
To	pwm_gen_inst/pwm_out_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R11C8[0][A]	pwm_gen_inst/pwm_gen_cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	5	R11C8[0][A]	pwm_gen_inst/pwm_gen_cnt_0_s0/Q
5.358	0.608	tNET	FF	1	R11C9[2][B]	pwm_gen_inst/n138_s116/I1
6.172	0.814	tINS	FF	2	R11C9[2][B]	pwm_gen_inst/n138_s116/F
6.772	0.600	tNET	FF	2	R9C9[0][B]	pwm_gen_inst/n138_s64/I0
7.482	0.710	tINS	FF	1	R9C9[0][B]	pwm_gen_inst/n138_s64/COUT
7.482	0.000	tNET	FF	2	R9C9[1][A]	pwm_gen_inst/n138_s65/CIN
7.525	0.042	tINS	FF	1	R9C9[1][A]	pwm_gen_inst/n138_s65/COUT
7.525	0.000	tNET	FF	2	R9C9[1][B]	pwm_gen_inst/n138_s66/CIN
7.567	0.042	tINS	FF	1	R9C9[1][B]	pwm_gen_inst/n138_s66/COUT
7.567	0.000	tNET	FF	2	R9C9[2][A]	pwm_gen_inst/n138_s67/CIN
7.609	0.042	tINS	FF	1	R9C9[2][A]	pwm_gen_inst/n138_s67/COUT
7.609	0.000	tNET	FF	2	R9C9[2][B]	pwm_gen_inst/n138_s68/CIN
7.651	0.042	tINS	FF	1	R9C9[2][B]	pwm_gen_inst/n138_s68/COUT
7.651	0.000	tNET	FF	2	R9C10[0][A]	pwm_gen_inst/n138_s69/CIN
7.694	0.042	tINS	FF	1	R9C10[0][A]	pwm_gen_inst/n138_s69/COUT
7.694	0.000	tNET	FF	2	R9C10[0][B]	pwm_gen_inst/n138_s70/CIN
7.736	0.042	tINS	FF	1	R9C10[0][B]	pwm_gen_inst/n138_s70/COUT
7.736	0.000	tNET	FF	2	R9C10[1][A]	pwm_gen_inst/n138_s71/CIN
7.778	0.042	tINS	FF	1	R9C10[1][A]	pwm_gen_inst/n138_s71/COUT
7.778	0.000	tNET	FF	2	R9C10[1][B]	pwm_gen_inst/n138_s72/CIN
7.820	0.042	tINS	FF	1	R9C10[1][B]	pwm_gen_inst/n138_s72/COUT
7.820	0.000	tNET	FF	2	R9C10[2][A]	pwm_gen_inst/n138_s73/CIN
7.863	0.042	tINS	FF	1	R9C10[2][A]	pwm_gen_inst/n138_s73/COUT
7.863	0.000	tNET	FF	2	R9C10[2][B]	pwm_gen_inst/n138_s74/CIN
7.905	0.042	tINS	FF	1	R9C10[2][B]	pwm_gen_inst/n138_s74/COUT
7.905	0.000	tNET	FF	2	R9C11[0][A]	pwm_gen_inst/n138_s75/CIN
7.947	0.042	tINS	FF	1	R9C11[0][A]	pwm_gen_inst/n138_s75/COUT
8.960	1.013	tNET	FF	1	R8C9[2][A]	pwm_gen_inst/n138_s122/I2
9.775	0.814	tINS	FF	1	R8C9[2][A]	pwm_gen_inst/n138_s122/F
10.024	0.249	tNET	FF	1	R8C9[2][B]	pwm_gen_inst/n138_s115/I3
10.488	0.464	tINS	FF	1	R8C9[2][B]	pwm_gen_inst/n138_s115/F
12.168	1.680	tNET	FF	1	IOR17[A]	pwm_gen_inst/pwm_out_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	IOR17[A]	pwm_gen_inst/pwm_out_s0/CLK
24.114	-0.296	tSu		1	IOR17[A]	pwm_gen_inst/pwm_out_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	7
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 3.267, 42.118%; route: 4.150, 53.504%; tC2Q: 0.340, 4.378%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path2

Path Summary:

Slack	13.433
Data Arrival Time	10.681
Data Required Time	24.114
From	pwm_gen_inst/pwm_gen_cnt_20_s0
To	pwm_gen_inst/pwm_gen_cnt_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/CLK
4.750	0.340	tC2Q	RF	3	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/Q
5.351	0.601	tNET	FF	1	R8C9[3][A]	pwm_gen_inst/n138_s118/I1
5.960	0.609	tINS	FF	4	R8C9[3][A]	pwm_gen_inst/n138_s118/F
6.817	0.857	tNET	FF	1	R7C9[3][A]	pwm_gen_inst/n103_s5/I0
7.631	0.814	tINS	FF	3	R7C9[3][A]	pwm_gen_inst/n103_s5/F
8.240	0.608	tNET	FF	1	R8C8[0][B]	pwm_gen_inst/n103_s4/I1
8.849	0.609	tINS	FF	31	R8C8[0][B]	pwm_gen_inst/n103_s4/F
9.867	1.018	tNET	FF	1	R11C10[2][B]	pwm_gen_inst/n102_s2/I0
10.681	0.814	tINS	FF	1	R11C10[2][B]	pwm_gen_inst/n102_s2/F
10.681	0.000	tNET	FF	1	R11C10[2][B]	pwm_gen_inst/pwm_gen_cnt_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R11C10[2][B]	pwm_gen_inst/pwm_gen_cnt_1_s0/CLK
24.114	-0.296	tSu		1	R11C10[2][B]	pwm_gen_inst/pwm_gen_cnt_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.847, 45.402%; route: 3.084, 49.182%; tC2Q: 0.340, 5.416%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path3

Path Summary:

Slack	13.433
Data Arrival Time	10.681
Data Required Time	24.114
From	pwm_gen_inst/pwm_gen_cnt_20_s0
To	pwm_gen_inst/pwm_gen_cnt_10_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/CLK
4.750	0.340	tC2Q	RF	3	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/Q
5.351	0.601	tNET	FF	1	R8C9[3][A]	pwm_gen_inst/n138_s118/I1
5.960	0.609	tINS	FF	4	R8C9[3][A]	pwm_gen_inst/n138_s118/F
6.817	0.857	tNET	FF	1	R7C9[3][A]	pwm_gen_inst/n103_s5/I0
7.631	0.814	tINS	FF	3	R7C9[3][A]	pwm_gen_inst/n103_s5/F
8.240	0.608	tNET	FF	1	R8C8[0][B]	pwm_gen_inst/n103_s4/I1
8.849	0.609	tINS	FF	31	R8C8[0][B]	pwm_gen_inst/n103_s4/F
9.867	1.018	tNET	FF	1	R11C10[2][A]	pwm_gen_inst/n93_s2/I2
10.681	0.814	tINS	FF	1	R11C10[2][A]	pwm_gen_inst/n93_s2/F
10.681	0.000	tNET	FF	1	R11C10[2][A]	pwm_gen_inst/pwm_gen_cnt_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R11C10[2][A]	pwm_gen_inst/pwm_gen_cnt_10_s0/CLK
24.114	-0.296	tSu		1	R11C10[2][A]	pwm_gen_inst/pwm_gen_cnt_10_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.847, 45.402%; route: 3.084, 49.182%; tC2Q: 0.340, 5.416%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path4

Path Summary:

Slack	13.447
Data Arrival Time	10.668
Data Required Time	24.114
From	pwm_gen_inst/pwm_gen_cnt_20_s0
To	pwm_gen_inst/pwm_gen_cnt_11_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/CLK
4.750	0.340	tC2Q	RF	3	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/Q
5.351	0.601	tNET	FF	1	R8C9[3][A]	pwm_gen_inst/n138_s118/I1
5.960	0.609	tINS	FF	4	R8C9[3][A]	pwm_gen_inst/n138_s118/F
6.817	0.857	tNET	FF	1	R7C9[3][A]	pwm_gen_inst/n103_s5/I0
7.631	0.814	tINS	FF	3	R7C9[3][A]	pwm_gen_inst/n103_s5/F
8.240	0.608	tNET	FF	1	R8C8[0][B]	pwm_gen_inst/n103_s4/I1
8.849	0.609	tINS	FF	31	R8C8[0][B]	pwm_gen_inst/n103_s4/F
9.853	1.004	tNET	FF	1	R11C10[1][B]	pwm_gen_inst/n92_s1/I0
10.668	0.814	tINS	FF	1	R11C10[1][B]	pwm_gen_inst/n92_s1/F
10.668	0.000	tNET	FF	1	R11C10[1][B]	pwm_gen_inst/pwm_gen_cnt_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R11C10[1][B]	pwm_gen_inst/pwm_gen_cnt_11_s0/CLK
24.114	-0.296	tSu		1	R11C10[1][B]	pwm_gen_inst/pwm_gen_cnt_11_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.847, 45.500%; route: 3.070, 49.072%; tC2Q: 0.340, 5.428%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path5

Path Summary:

Slack	13.495
Data Arrival Time	10.620
Data Required Time	24.114
From	pwm_gen_inst/pwm_gen_cnt_20_s0
To	pwm_gen_inst/pwm_gen_cnt_9_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/CLK
4.750	0.340	tC2Q	RF	3	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/Q
5.351	0.601	tNET	FF	1	R8C9[3][A]	pwm_gen_inst/n138_s118/I1
5.960	0.609	tINS	FF	4	R8C9[3][A]	pwm_gen_inst/n138_s118/F
6.817	0.857	tNET	FF	1	R7C9[3][A]	pwm_gen_inst/n103_s5/I0
7.631	0.814	tINS	FF	3	R7C9[3][A]	pwm_gen_inst/n103_s5/F
8.240	0.608	tNET	FF	1	R8C8[0][B]	pwm_gen_inst/n103_s4/I1
8.849	0.609	tINS	FF	31	R8C8[0][B]	pwm_gen_inst/n103_s4/F
9.855	1.006	tNET	FF	1	R11C10[1][A]	pwm_gen_inst/n94_s2/I0
10.620	0.765	tINS	FF	1	R11C10[1][A]	pwm_gen_inst/n94_s2/F
10.620	0.000	tNET	FF	1	R11C10[1][A]	pwm_gen_inst/pwm_gen_cnt_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R11C10[1][A]	pwm_gen_inst/pwm_gen_cnt_9_s0/CLK
24.114	-0.296	tSu		1	R11C10[1][A]	pwm_gen_inst/pwm_gen_cnt_9_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.797, 45.051%; route: 3.072, 49.479%; tC2Q: 0.340, 5.470%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path6

Path Summary:

Slack	13.495
Data Arrival Time	10.620
Data Required Time	24.114
From	pwm_gen_inst/pwm_gen_cnt_20_s0
To	pwm_gen_inst/pwm_gen_cnt_24_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/CLK
4.750	0.340	tC2Q	RF	3	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/Q
5.351	0.601	tNET	FF	1	R8C9[3][A]	pwm_gen_inst/n138_s118/I1
5.960	0.609	tINS	FF	4	R8C9[3][A]	pwm_gen_inst/n138_s118/F
6.817	0.857	tNET	FF	1	R7C9[3][A]	pwm_gen_inst/n103_s5/I0
7.631	0.814	tINS	FF	3	R7C9[3][A]	pwm_gen_inst/n103_s5/F
8.240	0.608	tNET	FF	1	R8C8[0][B]	pwm_gen_inst/n103_s4/I1
8.849	0.609	tINS	FF	31	R8C8[0][B]	pwm_gen_inst/n103_s4/F
9.855	1.006	tNET	FF	1	R11C10[0][B]	pwm_gen_inst/n79_s2/I0
10.620	0.765	tINS	FF	1	R11C10[0][B]	pwm_gen_inst/n79_s2/F
10.620	0.000	tNET	FF	1	R11C10[0][B]	pwm_gen_inst/pwm_gen_cnt_24_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R11C10[0][B]	pwm_gen_inst/pwm_gen_cnt_24_s0/CLK
24.114	-0.296	tSu		1	R11C10[0][B]	pwm_gen_inst/pwm_gen_cnt_24_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.797, 45.051%; route: 3.072, 49.479%; tC2Q: 0.340, 5.470%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path7

Path Summary:

Slack	13.496
Data Arrival Time	10.618
Data Required Time	24.114
From	pwm_gen_inst/pwm_gen_cnt_20_s0
To	pwm_gen_inst/pwm_gen_cnt_8_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/CLK
4.750	0.340	tC2Q	RF	3	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/Q
5.351	0.601	tNET	FF	1	R8C9[3][A]	pwm_gen_inst/n138_s118/I1
5.960	0.609	tINS	FF	4	R8C9[3][A]	pwm_gen_inst/n138_s118/F
6.817	0.857	tNET	FF	1	R7C9[3][A]	pwm_gen_inst/n103_s5/I0
7.631	0.814	tINS	FF	3	R7C9[3][A]	pwm_gen_inst/n103_s5/F
8.240	0.608	tNET	FF	1	R8C8[0][B]	pwm_gen_inst/n103_s4/I1
8.849	0.609	tINS	FF	31	R8C8[0][B]	pwm_gen_inst/n103_s4/F
9.853	1.004	tNET	FF	1	R11C9[2][A]	pwm_gen_inst/n95_s2/I0
10.618	0.765	tINS	FF	1	R11C9[2][A]	pwm_gen_inst/n95_s2/F
10.618	0.000	tNET	FF	1	R11C9[2][A]	pwm_gen_inst/pwm_gen_cnt_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R11C9[2][A]	pwm_gen_inst/pwm_gen_cnt_8_s0/CLK
24.114	-0.296	tSu		1	R11C9[2][A]	pwm_gen_inst/pwm_gen_cnt_8_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.797, 45.064%; route: 3.070, 49.465%; tC2Q: 0.340, 5.471%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path8

Path Summary:

Slack	13.506
Data Arrival Time	10.608
Data Required Time	24.114
From	pwm_gen_inst/pwm_gen_cnt_20_s0
To	pwm_gen_inst/pwm_gen_cnt_5_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/CLK
4.750	0.340	tC2Q	RF	3	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/Q
5.351	0.601	tNET	FF	1	R8C9[3][A]	pwm_gen_inst/n138_s118/I1
5.960	0.609	tINS	FF	4	R8C9[3][A]	pwm_gen_inst/n138_s118/F
6.817	0.857	tNET	FF	1	R7C9[3][A]	pwm_gen_inst/n103_s5/I0
7.631	0.814	tINS	FF	3	R7C9[3][A]	pwm_gen_inst/n103_s5/F
8.240	0.608	tNET	FF	1	R8C8[0][B]	pwm_gen_inst/n103_s4/I1
8.849	0.609	tINS	FF	31	R8C8[0][B]	pwm_gen_inst/n103_s4/F
9.843	0.994	tNET	FF	1	R11C9[1][B]	pwm_gen_inst/n98_s3/I0
10.608	0.765	tINS	FF	1	R11C9[1][B]	pwm_gen_inst/n98_s3/F
10.608	0.000	tNET	FF	1	R11C9[1][B]	pwm_gen_inst/pwm_gen_cnt_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R11C9[1][B]	pwm_gen_inst/pwm_gen_cnt_5_s0/CLK
24.114	-0.296	tSu		1	R11C9[1][B]	pwm_gen_inst/pwm_gen_cnt_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.797, 45.137%; route: 3.060, 49.383%; tC2Q: 0.340, 5.480%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path9

Path Summary:

Slack	13.506
Data Arrival Time	10.608
Data Required Time	24.114
From	pwm_gen_inst/pwm_gen_cnt_20_s0
To	pwm_gen_inst/pwm_gen_cnt_4_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/CLK
4.750	0.340	tC2Q	RF	3	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/Q
5.351	0.601	tNET	FF	1	R8C9[3][A]	pwm_gen_inst/n138_s118/I1
5.960	0.609	tINS	FF	4	R8C9[3][A]	pwm_gen_inst/n138_s118/F
6.817	0.857	tNET	FF	1	R7C9[3][A]	pwm_gen_inst/n103_s5/I0
7.631	0.814	tINS	FF	3	R7C9[3][A]	pwm_gen_inst/n103_s5/F
8.240	0.608	tNET	FF	1	R8C8[0][B]	pwm_gen_inst/n103_s4/I1
8.849	0.609	tINS	FF	31	R8C8[0][B]	pwm_gen_inst/n103_s4/F
9.843	0.994	tNET	FF	1	R11C9[1][A]	pwm_gen_inst/n99_s1/I0
10.608	0.765	tINS	FF	1	R11C9[1][A]	pwm_gen_inst/n99_s1/F
10.608	0.000	tNET	FF	1	R11C9[1][A]	pwm_gen_inst/pwm_gen_cnt_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R11C9[1][A]	pwm_gen_inst/pwm_gen_cnt_4_s0/CLK
24.114	-0.296	tSu		1	R11C9[1][A]	pwm_gen_inst/pwm_gen_cnt_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.797, 45.137%; route: 3.060, 49.383%; tC2Q: 0.340, 5.480%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path10

Path Summary:

Slack	13.506
Data Arrival Time	10.608
Data Required Time	24.114
From	pwm_gen_inst/pwm_gen_cnt_20_s0
To	pwm_gen_inst/pwm_gen_cnt_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/CLK
4.750	0.340	tC2Q	RF	3	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/Q
5.351	0.601	tNET	FF	1	R8C9[3][A]	pwm_gen_inst/n138_s118/I1
5.960	0.609	tINS	FF	4	R8C9[3][A]	pwm_gen_inst/n138_s118/F
6.817	0.857	tNET	FF	1	R7C9[3][A]	pwm_gen_inst/n103_s5/I0
7.631	0.814	tINS	FF	3	R7C9[3][A]	pwm_gen_inst/n103_s5/F
8.240	0.608	tNET	FF	1	R8C8[0][B]	pwm_gen_inst/n103_s4/I1
8.849	0.609	tINS	FF	31	R8C8[0][B]	pwm_gen_inst/n103_s4/F
9.843	0.994	tNET	FF	1	R11C9[0][A]	pwm_gen_inst/n101_s3/I0
10.608	0.765	tINS	FF	1	R11C9[0][A]	pwm_gen_inst/n101_s3/F
10.608	0.000	tNET	FF	1	R11C9[0][A]	pwm_gen_inst/pwm_gen_cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R11C9[0][A]	pwm_gen_inst/pwm_gen_cnt_2_s0/CLK
24.114	-0.296	tSu		1	R11C9[0][A]	pwm_gen_inst/pwm_gen_cnt_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.797, 45.137%; route: 3.060, 49.383%; tC2Q: 0.340, 5.480%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path11

Path Summary:

Slack	13.762
Data Arrival Time	10.352
Data Required Time	24.114
From	pwm_gen_inst/pwm_gen_cnt_11_s0
To	pwm_gen_inst/pwm_gen_cnt_29_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R11C10[1][B]	pwm_gen_inst/pwm_gen_cnt_11_s0/CLK
4.750	0.340	tC2Q	RF	3	R11C10[1][B]	pwm_gen_inst/pwm_gen_cnt_11_s0/Q
5.357	0.606	tNET	FF	1	R9C10[3][A]	pwm_gen_inst/n91_s3/I0
6.171	0.814	tINS	FF	3	R9C10[3][A]	pwm_gen_inst/n91_s3/F
6.775	0.604	tNET	FF	1	R11C9[3][B]	pwm_gen_inst/n86_s4/I1
7.540	0.765	tINS	FF	11	R11C9[3][B]	pwm_gen_inst/n86_s4/F
8.523	0.983	tNET	FF	1	R8C9[1][B]	pwm_gen_inst/n74_s3/I2
8.987	0.464	tINS	FF	3	R8C9[1][B]	pwm_gen_inst/n74_s3/F
9.587	0.600	tNET	FF	1	R7C10[1][B]	pwm_gen_inst/n74_s2/I2
10.352	0.765	tINS	FF	1	R7C10[1][B]	pwm_gen_inst/n74_s2/F
10.352	0.000	tNET	FF	1	R7C10[1][B]	pwm_gen_inst/pwm_gen_cnt_29_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R7C10[1][B]	pwm_gen_inst/pwm_gen_cnt_29_s0/CLK
24.114	-0.296	tSu		1	R7C10[1][B]	pwm_gen_inst/pwm_gen_cnt_29_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.808, 47.257%; route: 2.794, 47.027%; tC2Q: 0.340, 5.716%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path12

Path Summary:

Slack	13.796
Data Arrival Time	10.319
Data Required Time	24.114
From	pwm_gen_inst/pwm_gen_cnt_20_s0
To	pwm_gen_inst/pwm_gen_cnt_7_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/CLK
4.750	0.340	tC2Q	RF	3	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/Q
5.351	0.601	tNET	FF	1	R8C9[3][A]	pwm_gen_inst/n138_s118/I1
5.960	0.609	tINS	FF	4	R8C9[3][A]	pwm_gen_inst/n138_s118/F
6.817	0.857	tNET	FF	1	R7C9[3][A]	pwm_gen_inst/n103_s5/I0
7.631	0.814	tINS	FF	3	R7C9[3][A]	pwm_gen_inst/n103_s5/F
8.240	0.608	tNET	FF	1	R8C8[0][B]	pwm_gen_inst/n103_s4/I1
8.849	0.609	tINS	FF	31	R8C8[0][B]	pwm_gen_inst/n103_s4/F
9.504	0.655	tNET	FF	1	R11C8[1][B]	pwm_gen_inst/n96_s2/I0
10.319	0.814	tINS	FF	1	R11C8[1][B]	pwm_gen_inst/n96_s2/F
10.319	0.000	tNET	FF	1	R11C8[1][B]	pwm_gen_inst/pwm_gen_cnt_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R11C8[1][B]	pwm_gen_inst/pwm_gen_cnt_7_s0/CLK
24.114	-0.296	tSu		1	R11C8[1][B]	pwm_gen_inst/pwm_gen_cnt_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.847, 48.187%; route: 2.722, 46.064%; tC2Q: 0.340, 5.749%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path13

Path Summary:

Slack	13.796
Data Arrival Time	10.319
Data Required Time	24.114
From	pwm_gen_inst/pwm_gen_cnt_20_s0
To	pwm_gen_inst/pwm_gen_cnt_12_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/CLK
4.750	0.340	tC2Q	RF	3	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/Q
5.351	0.601	tNET	FF	1	R8C9[3][A]	pwm_gen_inst/n138_s118/I1
5.960	0.609	tINS	FF	4	R8C9[3][A]	pwm_gen_inst/n138_s118/F
6.817	0.857	tNET	FF	1	R7C9[3][A]	pwm_gen_inst/n103_s5/I0
7.631	0.814	tINS	FF	3	R7C9[3][A]	pwm_gen_inst/n103_s5/F
8.240	0.608	tNET	FF	1	R8C8[0][B]	pwm_gen_inst/n103_s4/I1
8.849	0.609	tINS	FF	31	R8C8[0][B]	pwm_gen_inst/n103_s4/F
9.504	0.655	tNET	FF	1	R11C8[1][A]	pwm_gen_inst/n91_s2/I2
10.319	0.814	tINS	FF	1	R11C8[1][A]	pwm_gen_inst/n91_s2/F
10.319	0.000	tNET	FF	1	R11C8[1][A]	pwm_gen_inst/pwm_gen_cnt_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R11C8[1][A]	pwm_gen_inst/pwm_gen_cnt_12_s0/CLK
24.114	-0.296	tSu		1	R11C8[1][A]	pwm_gen_inst/pwm_gen_cnt_12_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.847, 48.187%; route: 2.722, 46.064%; tC2Q: 0.340, 5.749%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path14

Path Summary:

Slack	13.818
Data Arrival Time	10.296
Data Required Time	24.114
From	pwm_gen_inst/pwm_gen_cnt_11_s0
To	pwm_gen_inst/pwm_gen_cnt_25_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R11C10[1][B]	pwm_gen_inst/pwm_gen_cnt_11_s0/CLK
4.750	0.340	tC2Q	RF	3	R11C10[1][B]	pwm_gen_inst/pwm_gen_cnt_11_s0/Q
5.357	0.606	tNET	FF	1	R9C10[3][A]	pwm_gen_inst/n91_s3/I0
6.171	0.814	tINS	FF	3	R9C10[3][A]	pwm_gen_inst/n91_s3/F
6.775	0.604	tNET	FF	1	R11C9[3][B]	pwm_gen_inst/n86_s4/I1
7.540	0.765	tINS	FF	11	R11C9[3][B]	pwm_gen_inst/n86_s4/F
8.164	0.624	tNET	FF	1	R8C9[3][B]	pwm_gen_inst/n79_s4/I3
8.628	0.464	tINS	FF	4	R8C9[3][B]	pwm_gen_inst/n79_s4/F
9.481	0.853	tNET	FF	1	R7C10[0][A]	pwm_gen_inst/n78_s2/I1
10.296	0.814	tINS	FF	1	R7C10[0][A]	pwm_gen_inst/n78_s2/F
10.296	0.000	tNET	FF	1	R7C10[0][A]	pwm_gen_inst/pwm_gen_cnt_25_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R7C10[0][A]	pwm_gen_inst/pwm_gen_cnt_25_s0/CLK
24.114	-0.296	tSu		1	R7C10[0][A]	pwm_gen_inst/pwm_gen_cnt_25_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.857, 48.551%; route: 2.688, 45.678%; tC2Q: 0.340, 5.771%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path15

Path Summary:

Slack	13.845
Data Arrival Time	10.269
Data Required Time	24.114
From	pwm_gen_inst/pwm_gen_cnt_20_s0
To	pwm_gen_inst/pwm_gen_cnt_6_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/CLK
4.750	0.340	tC2Q	RF	3	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/Q
5.351	0.601	tNET	FF	1	R8C9[3][A]	pwm_gen_inst/n138_s118/I1
5.960	0.609	tINS	FF	4	R8C9[3][A]	pwm_gen_inst/n138_s118/F
6.817	0.857	tNET	FF	1	R7C9[3][A]	pwm_gen_inst/n103_s5/I0
7.631	0.814	tINS	FF	3	R7C9[3][A]	pwm_gen_inst/n103_s5/F
8.240	0.608	tNET	FF	1	R8C8[0][B]	pwm_gen_inst/n103_s4/I1
8.849	0.609	tINS	FF	31	R8C8[0][B]	pwm_gen_inst/n103_s4/F
9.504	0.655	tNET	FF	1	R11C8[2][A]	pwm_gen_inst/n97_s1/I2
10.269	0.765	tINS	FF	1	R11C8[2][A]	pwm_gen_inst/n97_s1/F
10.269	0.000	tNET	FF	1	R11C8[2][A]	pwm_gen_inst/pwm_gen_cnt_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R11C8[2][A]	pwm_gen_inst/pwm_gen_cnt_6_s0/CLK
24.114	-0.296	tSu		1	R11C8[2][A]	pwm_gen_inst/pwm_gen_cnt_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.797, 47.748%; route: 2.722, 46.455%; tC2Q: 0.340, 5.797%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path16

Path Summary:

Slack	13.857
Data Arrival Time	10.257
Data Required Time	24.114
From	pwm_gen_inst/pwm_gen_cnt_20_s0
To	pwm_gen_inst/pwm_gen_cnt_3_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/CLK
4.750	0.340	tC2Q	RF	3	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/Q
5.351	0.601	tNET	FF	1	R8C9[3][A]	pwm_gen_inst/n138_s118/I1
5.960	0.609	tINS	FF	4	R8C9[3][A]	pwm_gen_inst/n138_s118/F
6.817	0.857	tNET	FF	1	R7C9[3][A]	pwm_gen_inst/n103_s5/I0
7.631	0.814	tINS	FF	3	R7C9[3][A]	pwm_gen_inst/n103_s5/F
8.240	0.608	tNET	FF	1	R8C8[0][B]	pwm_gen_inst/n103_s4/I1
8.849	0.609	tINS	FF	31	R8C8[0][B]	pwm_gen_inst/n103_s4/F
9.493	0.644	tNET	FF	1	R11C8[0][B]	pwm_gen_inst/n100_s1/I2
10.257	0.765	tINS	FF	1	R11C8[0][B]	pwm_gen_inst/n100_s1/F
10.257	0.000	tNET	FF	1	R11C8[0][B]	pwm_gen_inst/pwm_gen_cnt_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R11C8[0][B]	pwm_gen_inst/pwm_gen_cnt_3_s0/CLK
24.114	-0.296	tSu		1	R11C8[0][B]	pwm_gen_inst/pwm_gen_cnt_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.797, 47.844%; route: 2.710, 46.347%; tC2Q: 0.340, 5.809%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path17

Path Summary:

Slack	13.857
Data Arrival Time	10.257
Data Required Time	24.114
From	pwm_gen_inst/pwm_gen_cnt_20_s0
To	pwm_gen_inst/pwm_gen_cnt_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/CLK
4.750	0.340	tC2Q	RF	3	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/Q
5.351	0.601	tNET	FF	1	R8C9[3][A]	pwm_gen_inst/n138_s118/I1
5.960	0.609	tINS	FF	4	R8C9[3][A]	pwm_gen_inst/n138_s118/F
6.817	0.857	tNET	FF	1	R7C9[3][A]	pwm_gen_inst/n103_s5/I0
7.631	0.814	tINS	FF	3	R7C9[3][A]	pwm_gen_inst/n103_s5/F
8.240	0.608	tNET	FF	1	R8C8[0][B]	pwm_gen_inst/n103_s4/I1
8.849	0.609	tINS	FF	31	R8C8[0][B]	pwm_gen_inst/n103_s4/F
9.493	0.644	tNET	FF	1	R11C8[0][A]	pwm_gen_inst/n103_s3/I1
10.257	0.765	tINS	FF	1	R11C8[0][A]	pwm_gen_inst/n103_s3/F
10.257	0.000	tNET	FF	1	R11C8[0][A]	pwm_gen_inst/pwm_gen_cnt_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R11C8[0][A]	pwm_gen_inst/pwm_gen_cnt_0_s0/CLK
24.114	-0.296	tSu		1	R11C8[0][A]	pwm_gen_inst/pwm_gen_cnt_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.797, 47.844%; route: 2.710, 46.347%; tC2Q: 0.340, 5.809%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path18

Path Summary:

Slack	13.872
Data Arrival Time	10.242
Data Required Time	24.114
From	pwm_gen_inst/pwm_gen_cnt_20_s0
To	pwm_gen_inst/pwm_gen_cnt_22_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/CLK
4.750	0.340	tC2Q	RF	3	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/Q
5.351	0.601	tNET	FF	1	R8C9[3][A]	pwm_gen_inst/n138_s118/I1
5.960	0.609	tINS	FF	4	R8C9[3][A]	pwm_gen_inst/n138_s118/F
6.817	0.857	tNET	FF	1	R7C9[3][A]	pwm_gen_inst/n103_s5/I0
7.631	0.814	tINS	FF	3	R7C9[3][A]	pwm_gen_inst/n103_s5/F
8.240	0.608	tNET	FF	1	R8C8[0][B]	pwm_gen_inst/n103_s4/I1
8.849	0.609	tINS	FF	31	R8C8[0][B]	pwm_gen_inst/n103_s4/F
9.477	0.629	tNET	FF	1	R7C10[1][A]	pwm_gen_inst/n81_s2/I0
10.242	0.765	tINS	FF	1	R7C10[1][A]	pwm_gen_inst/n81_s2/F
10.242	0.000	tNET	FF	1	R7C10[1][A]	pwm_gen_inst/pwm_gen_cnt_22_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R7C10[1][A]	pwm_gen_inst/pwm_gen_cnt_22_s0/CLK
24.114	-0.296	tSu		1	R7C10[1][A]	pwm_gen_inst/pwm_gen_cnt_22_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.797, 47.968%; route: 2.695, 46.208%; tC2Q: 0.340, 5.824%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path19

Path Summary:

Slack	13.872
Data Arrival Time	10.242
Data Required Time	24.114
From	pwm_gen_inst/pwm_gen_cnt_20_s0
To	pwm_gen_inst/pwm_gen_cnt_18_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/CLK
4.750	0.340	tC2Q	RF	3	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/Q
5.351	0.601	tNET	FF	1	R8C9[3][A]	pwm_gen_inst/n138_s118/I1
5.960	0.609	tINS	FF	4	R8C9[3][A]	pwm_gen_inst/n138_s118/F
6.817	0.857	tNET	FF	1	R7C9[3][A]	pwm_gen_inst/n103_s5/I0
7.631	0.814	tINS	FF	3	R7C9[3][A]	pwm_gen_inst/n103_s5/F
8.240	0.608	tNET	FF	1	R8C8[0][B]	pwm_gen_inst/n103_s4/I1
8.849	0.609	tINS	FF	31	R8C8[0][B]	pwm_gen_inst/n103_s4/F
9.477	0.629	tNET	FF	1	R8C10[1][B]	pwm_gen_inst/n85_s2/I2
10.242	0.765	tINS	FF	1	R8C10[1][B]	pwm_gen_inst/n85_s2/F
10.242	0.000	tNET	FF	1	R8C10[1][B]	pwm_gen_inst/pwm_gen_cnt_18_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R8C10[1][B]	pwm_gen_inst/pwm_gen_cnt_18_s0/CLK
24.114	-0.296	tSu		1	R8C10[1][B]	pwm_gen_inst/pwm_gen_cnt_18_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.797, 47.968%; route: 2.695, 46.208%; tC2Q: 0.340, 5.824%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path20

Path Summary:

Slack	13.915
Data Arrival Time	10.200
Data Required Time	24.114
From	pwm_gen_inst/pwm_gen_cnt_11_s0
To	pwm_gen_inst/pwm_gen_cnt_21_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R11C10[1][B]	pwm_gen_inst/pwm_gen_cnt_11_s0/CLK
4.750	0.340	tC2Q	RF	3	R11C10[1][B]	pwm_gen_inst/pwm_gen_cnt_11_s0/Q
5.357	0.606	tNET	FF	1	R9C10[3][A]	pwm_gen_inst/n91_s3/I0
6.171	0.814	tINS	FF	3	R9C10[3][A]	pwm_gen_inst/n91_s3/F
6.775	0.604	tNET	FF	1	R11C9[3][B]	pwm_gen_inst/n86_s4/I1
7.540	0.765	tINS	FF	11	R11C9[3][B]	pwm_gen_inst/n86_s4/F
8.527	0.987	tNET	FF	1	R8C10[1][A]	pwm_gen_inst/n83_s3/I2
8.990	0.464	tINS	FF	2	R8C10[1][A]	pwm_gen_inst/n83_s3/F
9.591	0.600	tNET	FF	1	R8C9[0][A]	pwm_gen_inst/n82_s2/I1
10.200	0.609	tINS	FF	1	R8C9[0][A]	pwm_gen_inst/n82_s2/F
10.200	0.000	tNET	FF	1	R8C9[0][A]	pwm_gen_inst/pwm_gen_cnt_21_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R8C9[0][A]	pwm_gen_inst/pwm_gen_cnt_21_s0/CLK
24.114	-0.296	tSu		1	R8C9[0][A]	pwm_gen_inst/pwm_gen_cnt_21_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.652, 45.811%; route: 2.797, 48.322%; tC2Q: 0.340, 5.867%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path21

Path Summary:

Slack	13.998
Data Arrival Time	10.116
Data Required Time	24.114
From	pwm_gen_inst/pwm_gen_cnt_11_s0
To	pwm_gen_inst/pwm_gen_cnt_20_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R11C10[1][B]	pwm_gen_inst/pwm_gen_cnt_11_s0/CLK
4.750	0.340	tC2Q	RF	3	R11C10[1][B]	pwm_gen_inst/pwm_gen_cnt_11_s0/Q
5.357	0.606	tNET	FF	1	R9C10[3][A]	pwm_gen_inst/n91_s3/I0
6.171	0.814	tINS	FF	3	R9C10[3][A]	pwm_gen_inst/n91_s3/F
6.775	0.604	tNET	FF	1	R11C9[3][B]	pwm_gen_inst/n86_s4/I1
7.540	0.765	tINS	FF	11	R11C9[3][B]	pwm_gen_inst/n86_s4/F
8.527	0.987	tNET	FF	1	R8C10[1][A]	pwm_gen_inst/n83_s3/I2
8.990	0.463	tINS	FR	2	R8C10[1][A]	pwm_gen_inst/n83_s3/F
9.302	0.312	tNET	RR	1	R7C10[2][B]	pwm_gen_inst/n83_s2/I2
10.116	0.814	tINS	RF	1	R7C10[2][B]	pwm_gen_inst/n83_s2/F
10.116	0.000	tNET	FF	1	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/CLK
24.114	-0.296	tSu		1	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.857, 50.068%; route: 2.509, 43.979%; tC2Q: 0.340, 5.953%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path22

Path Summary:

Slack	14.008
Data Arrival Time	10.107
Data Required Time	24.114
From	pwm_gen_inst/pwm_gen_cnt_20_s0
To	pwm_gen_inst/pwm_gen_cnt_23_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/CLK
4.750	0.340	tC2Q	RF	3	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/Q
5.351	0.601	tNET	FF	1	R8C9[3][A]	pwm_gen_inst/n138_s118/I1
5.960	0.609	tINS	FF	4	R8C9[3][A]	pwm_gen_inst/n138_s118/F
6.817	0.857	tNET	FF	1	R7C9[3][A]	pwm_gen_inst/n103_s5/I0
7.631	0.814	tINS	FF	3	R7C9[3][A]	pwm_gen_inst/n103_s5/F
8.240	0.608	tNET	FF	1	R8C8[0][B]	pwm_gen_inst/n103_s4/I1
8.849	0.609	tINS	FF	31	R8C8[0][B]	pwm_gen_inst/n103_s4/F
9.498	0.649	tNET	FF	1	R7C9[1][B]	pwm_gen_inst/n80_s2/I2
10.107	0.609	tINS	FF	1	R7C9[1][B]	pwm_gen_inst/n80_s2/F
10.107	0.000	tNET	FF	1	R7C9[1][B]	pwm_gen_inst/pwm_gen_cnt_23_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R7C9[1][B]	pwm_gen_inst/pwm_gen_cnt_23_s0/CLK
24.114	-0.296	tSu		1	R7C9[1][B]	pwm_gen_inst/pwm_gen_cnt_23_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.642, 46.377%; route: 2.715, 47.660%; tC2Q: 0.340, 5.962%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path23

Path Summary:

Slack	14.008
Data Arrival Time	10.107
Data Required Time	24.114
From	pwm_gen_inst/pwm_gen_cnt_20_s0
To	pwm_gen_inst/pwm_gen_cnt_16_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/CLK
4.750	0.340	tC2Q	RF	3	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/Q
5.351	0.601	tNET	FF	1	R8C9[3][A]	pwm_gen_inst/n138_s118/I1
5.960	0.609	tINS	FF	4	R8C9[3][A]	pwm_gen_inst/n138_s118/F
6.817	0.857	tNET	FF	1	R7C9[3][A]	pwm_gen_inst/n103_s5/I0
7.631	0.814	tINS	FF	3	R7C9[3][A]	pwm_gen_inst/n103_s5/F
8.240	0.608	tNET	FF	1	R8C8[0][B]	pwm_gen_inst/n103_s4/I1
8.849	0.609	tINS	FF	31	R8C8[0][B]	pwm_gen_inst/n103_s4/F
9.498	0.649	tNET	FF	1	R7C9[0][A]	pwm_gen_inst/n87_s2/I2
10.107	0.609	tINS	FF	1	R7C9[0][A]	pwm_gen_inst/n87_s2/F
10.107	0.000	tNET	FF	1	R7C9[0][A]	pwm_gen_inst/pwm_gen_cnt_16_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R7C9[0][A]	pwm_gen_inst/pwm_gen_cnt_16_s0/CLK
24.114	-0.296	tSu		1	R7C9[0][A]	pwm_gen_inst/pwm_gen_cnt_16_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.642, 46.377%; route: 2.715, 47.660%; tC2Q: 0.340, 5.962%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path24

Path Summary:

Slack	14.052
Data Arrival Time	10.062
Data Required Time	24.114
From	pwm_gen_inst/pwm_gen_cnt_20_s0
To	pwm_gen_inst/pwm_gen_cnt_17_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/CLK
4.750	0.340	tC2Q	RF	3	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/Q
5.351	0.601	tNET	FF	1	R8C9[3][A]	pwm_gen_inst/n138_s118/I1
5.960	0.609	tINS	FF	4	R8C9[3][A]	pwm_gen_inst/n138_s118/F
6.817	0.857	tNET	FF	1	R7C9[3][A]	pwm_gen_inst/n103_s5/I0
7.631	0.814	tINS	FF	3	R7C9[3][A]	pwm_gen_inst/n103_s5/F
8.240	0.608	tNET	FF	1	R8C8[0][B]	pwm_gen_inst/n103_s4/I1
8.849	0.609	tINS	FF	31	R8C8[0][B]	pwm_gen_inst/n103_s4/F
9.248	0.399	tNET	FF	1	R8C10[2][A]	pwm_gen_inst/n86_s2/I2
10.062	0.814	tINS	FF	1	R8C10[2][A]	pwm_gen_inst/n86_s2/F
10.062	0.000	tNET	FF	1	R8C10[2][A]	pwm_gen_inst/pwm_gen_cnt_17_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R8C10[2][A]	pwm_gen_inst/pwm_gen_cnt_17_s0/CLK
24.114	-0.296	tSu		1	R8C10[2][A]	pwm_gen_inst/pwm_gen_cnt_17_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.847, 50.373%; route: 2.465, 43.617%; tC2Q: 0.340, 6.009%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path25

Path Summary:

Slack	14.052
Data Arrival Time	10.062
Data Required Time	24.114
From	pwm_gen_inst/pwm_gen_cnt_20_s0
To	pwm_gen_inst/pwm_gen_cnt_19_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
4.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/CLK
4.750	0.340	tC2Q	RF	3	R7C10[2][B]	pwm_gen_inst/pwm_gen_cnt_20_s0/Q
5.351	0.601	tNET	FF	1	R8C9[3][A]	pwm_gen_inst/n138_s118/I1
5.960	0.609	tINS	FF	4	R8C9[3][A]	pwm_gen_inst/n138_s118/F
6.817	0.857	tNET	FF	1	R7C9[3][A]	pwm_gen_inst/n103_s5/I0
7.631	0.814	tINS	FF	3	R7C9[3][A]	pwm_gen_inst/n103_s5/F
8.240	0.608	tNET	FF	1	R8C8[0][B]	pwm_gen_inst/n103_s4/I1
8.849	0.609	tINS	FF	31	R8C8[0][B]	pwm_gen_inst/n103_s4/F
9.248	0.399	tNET	FF	1	R8C10[2][B]	pwm_gen_inst/n84_s2/I2
10.062	0.814	tINS	FF	1	R8C10[2][B]	pwm_gen_inst/n84_s2/F
10.062	0.000	tNET	FF	1	R8C10[2][B]	pwm_gen_inst/pwm_gen_cnt_19_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk
20.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
24.230	4.230	tINS	RR	72	IOL6[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R8C10[2][B]	pwm_gen_inst/pwm_gen_cnt_19_s0/CLK
24.114	-0.296	tSu		1	R8C10[2][B]	pwm_gen_inst/pwm_gen_cnt_19_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.847, 50.373%; route: 2.465, 43.617%; tC2Q: 0.340, 6.009%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	pwm_gen_inst/pwm_gen_cnt_21_s0
To	pwm_gen_inst/pwm_gen_cnt_21_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C9[0][A]	pwm_gen_inst/pwm_gen_cnt_21_s0/CLK
3.510	0.247	tC2Q	RR	2	R8C9[0][A]	pwm_gen_inst/pwm_gen_cnt_21_s0/Q
3.512	0.002	tNET	RR	1	R8C9[0][A]	pwm_gen_inst/n82_s2/I3
3.788	0.276	tINS	RF	1	R8C9[0][A]	pwm_gen_inst/n82_s2/F
3.788	0.000	tNET	FF	1	R8C9[0][A]	pwm_gen_inst/pwm_gen_cnt_21_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C9[0][A]	pwm_gen_inst/pwm_gen_cnt_21_s0/CLK
3.263	0.000	tHld		1	R8C9[0][A]	pwm_gen_inst/pwm_gen_cnt_21_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path2

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	pwm_gen_inst/pwm_gen_cnt_25_s0
To	pwm_gen_inst/pwm_gen_cnt_25_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C10[0][A]	pwm_gen_inst/pwm_gen_cnt_25_s0/CLK
3.510	0.247	tC2Q	RR	4	R7C10[0][A]	pwm_gen_inst/pwm_gen_cnt_25_s0/Q
3.512	0.002	tNET	RR	1	R7C10[0][A]	pwm_gen_inst/n78_s2/I3
3.788	0.276	tINS	RF	1	R7C10[0][A]	pwm_gen_inst/n78_s2/F
3.788	0.000	tNET	FF	1	R7C10[0][A]	pwm_gen_inst/pwm_gen_cnt_25_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C10[0][A]	pwm_gen_inst/pwm_gen_cnt_25_s0/CLK
3.263	0.000	tHld		1	R7C10[0][A]	pwm_gen_inst/pwm_gen_cnt_25_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path3

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	t500ms_dly_cnt_3_s0
To	t500ms_dly_cnt_3_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C11[0][A]	t500ms_dly_cnt_3_s0/CLK
3.510	0.247	tC2Q	RR	2	R7C11[0][A]	t500ms_dly_cnt_3_s0/Q
3.512	0.002	tNET	RR	1	R7C11[0][A]	n73_s2/I3
3.788	0.276	tINS	RF	1	R7C11[0][A]	n73_s2/F
3.788	0.000	tNET	FF	1	R7C11[0][A]	t500ms_dly_cnt_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C11[0][A]	t500ms_dly_cnt_3_s0/CLK
3.263	0.000	tHld		1	R7C11[0][A]	t500ms_dly_cnt_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path4

Path Summary:

Slack	0.525
Data Arrival Time	3.788
Data Required Time	3.263
From	pwm_gen_inst/pwm_gen_cnt_0_s0
To	pwm_gen_inst/pwm_gen_cnt_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C8[0][A]	pwm_gen_inst/pwm_gen_cnt_0_s0/CLK
3.510	0.247	tC2Q	RR	5	R11C8[0][A]	pwm_gen_inst/pwm_gen_cnt_0_s0/Q
3.513	0.003	tNET	RR	1	R11C8[0][A]	pwm_gen_inst/n103_s3/I0
3.788	0.276	tINS	RF	1	R11C8[0][A]	pwm_gen_inst/n103_s3/F
3.788	0.000	tNET	FF	1	R11C8[0][A]	pwm_gen_inst/pwm_gen_cnt_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C8[0][A]	pwm_gen_inst/pwm_gen_cnt_0_s0/CLK
3.263	0.000	tHld		1	R11C8[0][A]	pwm_gen_inst/pwm_gen_cnt_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path5

Path Summary:

Slack	0.525
Data Arrival Time	3.788
Data Required Time	3.263
From	pwm_gen_inst/pwm_gen_cnt_31_s0
To	pwm_gen_inst/pwm_gen_cnt_31_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C8[0][A]	pwm_gen_inst/pwm_gen_cnt_31_s0/CLK
3.510	0.247	tC2Q	RR	3	R8C8[0][A]	pwm_gen_inst/pwm_gen_cnt_31_s0/Q
3.513	0.003	tNET	RR	1	R8C8[0][A]	pwm_gen_inst/n72_s2/I3
3.788	0.276	tINS	RF	1	R8C8[0][A]	pwm_gen_inst/n72_s2/F
3.788	0.000	tNET	FF	1	R8C8[0][A]	pwm_gen_inst/pwm_gen_cnt_31_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C8[0][A]	pwm_gen_inst/pwm_gen_cnt_31_s0/CLK
3.263	0.000	tHld		1	R8C8[0][A]	pwm_gen_inst/pwm_gen_cnt_31_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path6

Path Summary:

Slack	0.525
Data Arrival Time	3.788
Data Required Time	3.263
From	pwm_gen_inst/pwm_gen_cnt_2_s0
To	pwm_gen_inst/pwm_gen_cnt_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C9[0][A]	pwm_gen_inst/pwm_gen_cnt_2_s0/CLK
3.510	0.247	tC2Q	RR	5	R11C9[0][A]	pwm_gen_inst/pwm_gen_cnt_2_s0/Q
3.513	0.003	tNET	RR	1	R11C9[0][A]	pwm_gen_inst/n101_s3/I1
3.788	0.276	tINS	RF	1	R11C9[0][A]	pwm_gen_inst/n101_s3/F
3.788	0.000	tNET	FF	1	R11C9[0][A]	pwm_gen_inst/pwm_gen_cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C9[0][A]	pwm_gen_inst/pwm_gen_cnt_2_s0/CLK
3.263	0.000	tHld		1	R11C9[0][A]	pwm_gen_inst/pwm_gen_cnt_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path7

Path Summary:

Slack	0.525
Data Arrival Time	3.788
Data Required Time	3.263
From	pwm_gen_inst/pwm_gen_cnt_12_s0
To	pwm_gen_inst/pwm_gen_cnt_12_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C8[1][A]	pwm_gen_inst/pwm_gen_cnt_12_s0/CLK
3.510	0.247	tC2Q	RR	4	R11C8[1][A]	pwm_gen_inst/pwm_gen_cnt_12_s0/Q
3.513	0.003	tNET	RR	1	R11C8[1][A]	pwm_gen_inst/n91_s2/I3
3.788	0.276	tINS	RF	1	R11C8[1][A]	pwm_gen_inst/n91_s2/F
3.788	0.000	tNET	FF	1	R11C8[1][A]	pwm_gen_inst/pwm_gen_cnt_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C8[1][A]	pwm_gen_inst/pwm_gen_cnt_12_s0/CLK
3.263	0.000	tHld		1	R11C8[1][A]	pwm_gen_inst/pwm_gen_cnt_12_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path8

Path Summary:

Slack	0.525
Data Arrival Time	3.788
Data Required Time	3.263
From	pwm_gen_inst/pwm_gen_cnt_22_s0
To	pwm_gen_inst/pwm_gen_cnt_22_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C10[1][A]	pwm_gen_inst/pwm_gen_cnt_22_s0/CLK
3.510	0.247	tC2Q	RR	3	R7C10[1][A]	pwm_gen_inst/pwm_gen_cnt_22_s0/Q
3.513	0.003	tNET	RR	1	R7C10[1][A]	pwm_gen_inst/n81_s2/I1
3.788	0.276	tINS	RF	1	R7C10[1][A]	pwm_gen_inst/n81_s2/F
3.788	0.000	tNET	FF	1	R7C10[1][A]	pwm_gen_inst/pwm_gen_cnt_22_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C10[1][A]	pwm_gen_inst/pwm_gen_cnt_22_s0/CLK
3.263	0.000	tHld		1	R7C10[1][A]	pwm_gen_inst/pwm_gen_cnt_22_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path9

Path Summary:

Slack	0.525
Data Arrival Time	3.788
Data Required Time	3.263
From	pwm_gen_inst/pwm_gen_cnt_28_s0
To	pwm_gen_inst/pwm_gen_cnt_28_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C9[1][A]	pwm_gen_inst/pwm_gen_cnt_28_s0/CLK
3.510	0.247	tC2Q	RR	3	R8C9[1][A]	pwm_gen_inst/pwm_gen_cnt_28_s0/Q
3.513	0.003	tNET	RR	1	R8C9[1][A]	pwm_gen_inst/n75_s2/I3
3.788	0.276	tINS	RF	1	R8C9[1][A]	pwm_gen_inst/n75_s2/F
3.788	0.000	tNET	FF	1	R8C9[1][A]	pwm_gen_inst/pwm_gen_cnt_28_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C9[1][A]	pwm_gen_inst/pwm_gen_cnt_28_s0/CLK
3.263	0.000	tHld		1	R8C9[1][A]	pwm_gen_inst/pwm_gen_cnt_28_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path10

Path Summary:

Slack	0.525
Data Arrival Time	3.788
Data Required Time	3.263
From	pwm_gen_inst/pwm_gen_cnt_30_s0
To	pwm_gen_inst/pwm_gen_cnt_30_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C8[1][A]	pwm_gen_inst/pwm_gen_cnt_30_s0/CLK
3.510	0.247	tC2Q	RR	3	R8C8[1][A]	pwm_gen_inst/pwm_gen_cnt_30_s0/Q
3.513	0.003	tNET	RR	1	R8C8[1][A]	pwm_gen_inst/n73_s2/I3
3.788	0.276	tINS	RF	1	R8C8[1][A]	pwm_gen_inst/n73_s2/F
3.788	0.000	tNET	FF	1	R8C8[1][A]	pwm_gen_inst/pwm_gen_cnt_30_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C8[1][A]	pwm_gen_inst/pwm_gen_cnt_30_s0/CLK
3.263	0.000	tHld		1	R8C8[1][A]	pwm_gen_inst/pwm_gen_cnt_30_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path11

Path Summary:

Slack	0.525
Data Arrival Time	3.788
Data Required Time	3.263
From	t500ms_dly_cnt_0_s0
To	t500ms_dly_cnt_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C11[1][A]	t500ms_dly_cnt_0_s0/CLK
3.510	0.247	tC2Q	RR	5	R7C11[1][A]	t500ms_dly_cnt_0_s0/Q
3.513	0.003	tNET	RR	1	R7C11[1][A]	n76_s4/I0
3.788	0.276	tINS	RF	1	R7C11[1][A]	n76_s4/F
3.788	0.000	tNET	FF	1	R7C11[1][A]	t500ms_dly_cnt_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C11[1][A]	t500ms_dly_cnt_0_s0/CLK
3.263	0.000	tHld		1	R7C11[1][A]	t500ms_dly_cnt_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path12

Path Summary:

Slack	0.525
Data Arrival Time	3.788
Data Required Time	3.263
From	t500ms_dly_cnt_11_s0
To	t500ms_dly_cnt_11_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C12[1][A]	t500ms_dly_cnt_11_s0/CLK
3.510	0.247	tC2Q	RR	3	R7C12[1][A]	t500ms_dly_cnt_11_s0/Q
3.513	0.003	tNET	RR	1	R7C12[1][A]	n65_s2/I3
3.788	0.276	tINS	RF	1	R7C12[1][A]	n65_s2/F
3.788	0.000	tNET	FF	1	R7C12[1][A]	t500ms_dly_cnt_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C12[1][A]	t500ms_dly_cnt_11_s0/CLK
3.263	0.000	tHld		1	R7C12[1][A]	t500ms_dly_cnt_11_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path13

Path Summary:

Slack	0.525
Data Arrival Time	3.788
Data Required Time	3.263
From	t500ms_dly_cnt_15_s0
To	t500ms_dly_cnt_15_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C13[1][A]	t500ms_dly_cnt_15_s0/CLK
3.510	0.247	tC2Q	RR	3	R7C13[1][A]	t500ms_dly_cnt_15_s0/Q
3.513	0.003	tNET	RR	1	R7C13[1][A]	n61_s2/I3
3.788	0.276	tINS	RF	1	R7C13[1][A]	n61_s2/F
3.788	0.000	tNET	FF	1	R7C13[1][A]	t500ms_dly_cnt_15_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C13[1][A]	t500ms_dly_cnt_15_s0/CLK
3.263	0.000	tHld		1	R7C13[1][A]	t500ms_dly_cnt_15_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path14

Path Summary:

Slack	0.525
Data Arrival Time	3.788
Data Required Time	3.263
From	t500ms_dly_cnt_17_s0
To	t500ms_dly_cnt_17_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C12[1][A]	t500ms_dly_cnt_17_s0/CLK
3.510	0.247	tC2Q	RR	4	R8C12[1][A]	t500ms_dly_cnt_17_s0/Q
3.513	0.003	tNET	RR	1	R8C12[1][A]	n59_s2/I2
3.788	0.276	tINS	RF	1	R8C12[1][A]	n59_s2/F
3.788	0.000	tNET	FF	1	R8C12[1][A]	t500ms_dly_cnt_17_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C12[1][A]	t500ms_dly_cnt_17_s0/CLK
3.263	0.000	tHld		1	R8C12[1][A]	t500ms_dly_cnt_17_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path15

Path Summary:

Slack	0.526
Data Arrival Time	3.789
Data Required Time	3.263
From	pwm_gen_inst/pwm_gen_cnt_27_s0
To	pwm_gen_inst/pwm_gen_cnt_27_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C8[0][A]	pwm_gen_inst/pwm_gen_cnt_27_s0/CLK
3.510	0.247	tC2Q	RR	4	R7C8[0][A]	pwm_gen_inst/pwm_gen_cnt_27_s0/Q
3.514	0.003	tNET	RR	1	R7C8[0][A]	pwm_gen_inst/n76_s2/I3
3.789	0.276	tINS	RF	1	R7C8[0][A]	pwm_gen_inst/n76_s2/F
3.789	0.000	tNET	FF	1	R7C8[0][A]	pwm_gen_inst/pwm_gen_cnt_27_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C8[0][A]	pwm_gen_inst/pwm_gen_cnt_27_s0/CLK
3.263	0.000	tHld		1	R7C8[0][A]	pwm_gen_inst/pwm_gen_cnt_27_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path16

Path Summary:

Slack	0.526
Data Arrival Time	3.789
Data Required Time	3.263
From	t500ms_dly_cnt_4_s0
To	t500ms_dly_cnt_4_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C11[1][A]	t500ms_dly_cnt_4_s0/CLK
3.510	0.247	tC2Q	RR	5	R8C11[1][A]	t500ms_dly_cnt_4_s0/Q
3.514	0.003	tNET	RR	1	R8C11[1][A]	n72_s2/I0
3.789	0.276	tINS	RF	1	R8C11[1][A]	n72_s2/F
3.789	0.000	tNET	FF	1	R8C11[1][A]	t500ms_dly_cnt_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C11[1][A]	t500ms_dly_cnt_4_s0/CLK
3.263	0.000	tHld		1	R8C11[1][A]	t500ms_dly_cnt_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path17

Path Summary:

Slack	0.526
Data Arrival Time	3.789
Data Required Time	3.263
From	t500ms_dly_cnt_8_s0
To	t500ms_dly_cnt_8_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C13[0][A]	t500ms_dly_cnt_8_s0/CLK
3.510	0.247	tC2Q	RR	5	R7C13[0][A]	t500ms_dly_cnt_8_s0/Q
3.514	0.003	tNET	RR	1	R7C13[0][A]	n68_s3/I0
3.789	0.276	tINS	RF	1	R7C13[0][A]	n68_s3/F
3.789	0.000	tNET	FF	1	R7C13[0][A]	t500ms_dly_cnt_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C13[0][A]	t500ms_dly_cnt_8_s0/CLK
3.263	0.000	tHld		1	R7C13[0][A]	t500ms_dly_cnt_8_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path18

Path Summary:

Slack	0.526
Data Arrival Time	3.789
Data Required Time	3.263
From	t500ms_dly_cnt_21_s0
To	t500ms_dly_cnt_21_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C13[0][A]	t500ms_dly_cnt_21_s0/CLK
3.510	0.247	tC2Q	RR	4	R11C13[0][A]	t500ms_dly_cnt_21_s0/Q
3.514	0.003	tNET	RR	1	R11C13[0][A]	n55_s2/I3
3.789	0.276	tINS	RF	1	R11C13[0][A]	n55_s2/F
3.789	0.000	tNET	FF	1	R11C13[0][A]	t500ms_dly_cnt_21_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C13[0][A]	t500ms_dly_cnt_21_s0/CLK
3.263	0.000	tHld		1	R11C13[0][A]	t500ms_dly_cnt_21_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path19

Path Summary:

Slack	0.527
Data Arrival Time	3.790
Data Required Time	3.263
From	pwm_gen_inst/pwm_gen_cnt_4_s0
To	pwm_gen_inst/pwm_gen_cnt_4_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C9[1][A]	pwm_gen_inst/pwm_gen_cnt_4_s0/CLK
3.510	0.247	tC2Q	RR	5	R11C9[1][A]	pwm_gen_inst/pwm_gen_cnt_4_s0/Q
3.515	0.004	tNET	RR	1	R11C9[1][A]	pwm_gen_inst/n99_s1/I1
3.790	0.276	tINS	RF	1	R11C9[1][A]	pwm_gen_inst/n99_s1/F
3.790	0.000	tNET	FF	1	R11C9[1][A]	pwm_gen_inst/pwm_gen_cnt_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C9[1][A]	pwm_gen_inst/pwm_gen_cnt_4_s0/CLK
3.263	0.000	tHld		1	R11C9[1][A]	pwm_gen_inst/pwm_gen_cnt_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.303%; route: 0.004, 0.830%; tC2Q: 0.247, 46.867%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path20

Path Summary:

Slack	0.527
Data Arrival Time	3.790
Data Required Time	3.263
From	pwm_gen_inst/pwm_gen_cnt_9_s0
To	pwm_gen_inst/pwm_gen_cnt_9_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C10[1][A]	pwm_gen_inst/pwm_gen_cnt_9_s0/CLK
3.510	0.247	tC2Q	RR	5	R11C10[1][A]	pwm_gen_inst/pwm_gen_cnt_9_s0/Q
3.515	0.004	tNET	RR	1	R11C10[1][A]	pwm_gen_inst/n94_s2/I1
3.790	0.276	tINS	RF	1	R11C10[1][A]	pwm_gen_inst/n94_s2/F
3.790	0.000	tNET	FF	1	R11C10[1][A]	pwm_gen_inst/pwm_gen_cnt_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C10[1][A]	pwm_gen_inst/pwm_gen_cnt_9_s0/CLK
3.263	0.000	tHld		1	R11C10[1][A]	pwm_gen_inst/pwm_gen_cnt_9_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.303%; route: 0.004, 0.830%; tC2Q: 0.247, 46.867%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path21

Path Summary:

Slack	0.527
Data Arrival Time	3.790
Data Required Time	3.263
From	t500ms_dly_cnt_20_s0
To	t500ms_dly_cnt_20_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C13[1][A]	t500ms_dly_cnt_20_s0/CLK
3.510	0.247	tC2Q	RR	5	R11C13[1][A]	t500ms_dly_cnt_20_s0/Q
3.515	0.004	tNET	RR	1	R11C13[1][A]	n56_s3/I3
3.790	0.276	tINS	RF	1	R11C13[1][A]	n56_s3/F
3.790	0.000	tNET	FF	1	R11C13[1][A]	t500ms_dly_cnt_20_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C13[1][A]	t500ms_dly_cnt_20_s0/CLK
3.263	0.000	tHld		1	R11C13[1][A]	t500ms_dly_cnt_20_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.303%; route: 0.004, 0.830%; tC2Q: 0.247, 46.867%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path22

Path Summary:

Slack	0.661
Data Arrival Time	3.924
Data Required Time	3.263
From	t500ms_dly_cnt_14_s0
To	t500ms_dly_cnt_14_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C13[2][A]	t500ms_dly_cnt_14_s0/CLK
3.510	0.247	tC2Q	RR	4	R7C13[2][A]	t500ms_dly_cnt_14_s0/Q
3.512	0.002	tNET	RR	1	R7C13[2][A]	n62_s2/I3
3.924	0.412	tINS	RR	1	R7C13[2][A]	n62_s2/F
3.924	0.000	tNET	RR	1	R7C13[2][A]	t500ms_dly_cnt_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C13[2][A]	t500ms_dly_cnt_14_s0/CLK
3.263	0.000	tHld		1	R7C13[2][A]	t500ms_dly_cnt_14_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.412, 62.353%; route: 0.002, 0.265%; tC2Q: 0.247, 37.382%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path23

Path Summary:

Slack	0.662
Data Arrival Time	3.925
Data Required Time	3.263
From	pwm_gen_inst/pwm_gen_cnt_6_s0
To	pwm_gen_inst/pwm_gen_cnt_6_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C8[2][A]	pwm_gen_inst/pwm_gen_cnt_6_s0/CLK
3.510	0.247	tC2Q	RR	4	R11C8[2][A]	pwm_gen_inst/pwm_gen_cnt_6_s0/Q
3.513	0.003	tNET	RR	1	R11C8[2][A]	pwm_gen_inst/n97_s1/I3
3.925	0.412	tINS	RR	1	R11C8[2][A]	pwm_gen_inst/n97_s1/F
3.925	0.000	tNET	RR	1	R11C8[2][A]	pwm_gen_inst/pwm_gen_cnt_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C8[2][A]	pwm_gen_inst/pwm_gen_cnt_6_s0/CLK
3.263	0.000	tHld		1	R11C8[2][A]	pwm_gen_inst/pwm_gen_cnt_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.412, 62.271%; route: 0.003, 0.397%; tC2Q: 0.247, 37.333%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path24

Path Summary:

Slack	0.662
Data Arrival Time	3.925
Data Required Time	3.263
From	pwm_gen_inst/pwm_gen_cnt_10_s0
To	pwm_gen_inst/pwm_gen_cnt_10_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C10[2][A]	pwm_gen_inst/pwm_gen_cnt_10_s0/CLK
3.510	0.247	tC2Q	RR	4	R11C10[2][A]	pwm_gen_inst/pwm_gen_cnt_10_s0/Q
3.513	0.003	tNET	RR	1	R11C10[2][A]	pwm_gen_inst/n93_s2/I3
3.925	0.412	tINS	RR	1	R11C10[2][A]	pwm_gen_inst/n93_s2/F
3.925	0.000	tNET	RR	1	R11C10[2][A]	pwm_gen_inst/pwm_gen_cnt_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C10[2][A]	pwm_gen_inst/pwm_gen_cnt_10_s0/CLK
3.263	0.000	tHld		1	R11C10[2][A]	pwm_gen_inst/pwm_gen_cnt_10_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.412, 62.271%; route: 0.003, 0.397%; tC2Q: 0.247, 37.333%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path25

Path Summary:

Slack	0.662
Data Arrival Time	3.925
Data Required Time	3.263
From	pwm_gen_inst/pwm_gen_cnt_17_s0
To	pwm_gen_inst/pwm_gen_cnt_17_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C10[2][A]	pwm_gen_inst/pwm_gen_cnt_17_s0/CLK
3.510	0.247	tC2Q	RR	5	R8C10[2][A]	pwm_gen_inst/pwm_gen_cnt_17_s0/Q
3.513	0.003	tNET	RR	1	R8C10[2][A]	pwm_gen_inst/n86_s2/I3
3.925	0.412	tINS	RR	1	R8C10[2][A]	pwm_gen_inst/n86_s2/F
3.925	0.000	tNET	RR	1	R8C10[2][A]	pwm_gen_inst/pwm_gen_cnt_17_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOL6[A]	clk_ibuf/I
3.126	3.126	tINS	RR	72	IOL6[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C10[2][A]	pwm_gen_inst/pwm_gen_cnt_17_s0/CLK
3.263	0.000	tHld		1	R8C10[2][A]	pwm_gen_inst/pwm_gen_cnt_17_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.412, 62.271%; route: 0.003, 0.397%; tC2Q: 0.247, 37.333%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	clk
Objects:	t500ms_dly_cnt_23_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	t500ms_dly_cnt_23_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	t500ms_dly_cnt_23_s0/CLK

MPW2

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	clk
Objects:	t500ms_dly_cnt_22_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	t500ms_dly_cnt_22_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	t500ms_dly_cnt_22_s0/CLK

MPW3

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	clk
Objects:	t500ms_dly_cnt_20_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	t500ms_dly_cnt_20_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	t500ms_dly_cnt_20_s0/CLK

MPW4

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	clk
Objects:	t500ms_dly_cnt_16_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	t500ms_dly_cnt_16_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	t500ms_dly_cnt_16_s0/CLK

MPW5

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	clk
Objects:	t500ms_dly_cnt_8_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	t500ms_dly_cnt_8_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	t500ms_dly_cnt_8_s0/CLK

MPW6

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	clk
Objects:	counter_ccr_8_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	counter_ccr_8_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	counter_ccr_8_s0/CLK

MPW7

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	clk
Objects:	pwm_gen_inst/pwm_gen_cnt_6_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	pwm_gen_inst/pwm_gen_cnt_6_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	pwm_gen_inst/pwm_gen_cnt_6_s0/CLK

MPW8

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	clk
Objects:	pwm_gen_inst/pwm_gen_cnt_7_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	pwm_gen_inst/pwm_gen_cnt_7_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	pwm_gen_inst/pwm_gen_cnt_7_s0/CLK

MPW9

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	clk
Objects:	counter_ccr_9_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	counter_ccr_9_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	counter_ccr_9_s0/CLK

MPW10

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	clk
Objects:	pwm_gen_inst/pwm_gen_cnt_8_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	pwm_gen_inst/pwm_gen_cnt_8_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	pwm_gen_inst/pwm_gen_cnt_8_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
72	clk_d	11.947	0.195
31	n103_8	13.433	1.018
17	n53_14	14.064	0.753
13	level_num[2]	17.923	0.627
13	level_num[0]	18.018	0.737
13	level_num[1]	18.175	0.630
11	n86_8	13.762	0.987
8	n72_7	14.597	0.612
7	n53_7	14.597	0.987
7	n99_6	14.496	0.383

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R9C12	86.11%
R7C10	77.78%
R11C13	77.78%
R11C8	69.44%
R11C9	66.67%
R11C10	63.89%
R7C13	63.89%
R9C13	61.11%
R7C12	59.72%
R8C9	59.72%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command