Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\quanggit_lab\example_code\LED_BLINK\src\led_flash.v
C:\quanggit_lab\example_code\LED_BLINK\src\led_flash_tb.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.03 (64-bit)
Part Number GW1N-UV1P5QN48XFC7/I6
Device GW1N-1P5
Device Version C
Created Time Tue Jul 29 15:36:49 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module led_flash
Synthesis Process Running parser:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.038s, Peak memory usage = 191.574MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 191.574MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 191.574MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 191.574MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 191.574MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 191.574MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 191.574MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 191.574MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 191.574MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 191.574MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 191.574MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.233s, Peak memory usage = 208.918MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.039s, Peak memory usage = 208.918MB
Generate output files:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 208.918MB
Total Time and Memory Usage CPU time = 0h 0m 0.217s, Elapsed time = 0h 0m 0.314s, Peak memory usage = 208.918MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 4
I/O Buf 4
    IBUF 2
    OBUF 2
Register 27
    DFFPE 1
    DFFC 25
    DFFCE 1
LUT 56
    LUT2 10
    LUT3 11
    LUT4 35
INV 3
    INV 3

Resource Utilization Summary

Resource Usage Utilization
Logic 59(59 LUT, 0 ALU) / 1584 4%
Register 27 / 1704 2%
  --Register as Latch 0 / 1704 0%
  --Register as FF 27 / 1704 2%
BSRAM 0 / 4 0%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk Base 20.000 50.000 0.000 10.000 clk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 50.000(MHz) 135.124(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 12.599
Data Arrival Time 7.642
Data Required Time 20.242
From cnt_5_s0
To cnt_0_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 27 clk_ibuf/O
0.538 0.538 tNET RR 1 cnt_5_s0/CLK
0.878 0.340 tC2Q RF 4 cnt_5_s0/Q
1.589 0.711 tNET FF 1 n112_s26/I1
2.403 0.814 tINS FF 1 n112_s26/F
3.115 0.711 tNET FF 1 n38_s5/I1
3.929 0.814 tINS FF 1 n38_s5/F
4.640 0.711 tNET FF 1 n38_s3/I0
5.405 0.765 tINS FF 22 n38_s3/F
6.116 0.711 tNET FF 1 n62_s2/I1
6.931 0.814 tINS FF 1 n62_s2/F
7.642 0.711 tNET FF 1 cnt_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 27 clk_ibuf/O
20.538 0.538 tNET RR 1 cnt_0_s0/CLK
20.242 -0.296 tSu 1 cnt_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.208, 45.153%; route: 3.557, 50.066%; tC2Q: 0.340, 4.781%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 2

Path Summary:
Slack 12.599
Data Arrival Time 7.642
Data Required Time 20.242
From cnt_5_s0
To cnt_12_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 27 clk_ibuf/O
0.538 0.538 tNET RR 1 cnt_5_s0/CLK
0.878 0.340 tC2Q RF 4 cnt_5_s0/Q
1.589 0.711 tNET FF 1 n112_s26/I1
2.403 0.814 tINS FF 1 n112_s26/F
3.115 0.711 tNET FF 1 n38_s5/I1
3.929 0.814 tINS FF 1 n38_s5/F
4.640 0.711 tNET FF 1 n38_s3/I0
5.405 0.765 tINS FF 22 n38_s3/F
6.116 0.711 tNET FF 1 n50_s1/I1
6.931 0.814 tINS FF 1 n50_s1/F
7.642 0.711 tNET FF 1 cnt_12_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 27 clk_ibuf/O
20.538 0.538 tNET RR 1 cnt_12_s0/CLK
20.242 -0.296 tSu 1 cnt_12_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.208, 45.153%; route: 3.557, 50.066%; tC2Q: 0.340, 4.781%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 3

Path Summary:
Slack 12.599
Data Arrival Time 7.642
Data Required Time 20.242
From cnt_1_s0
To cnt_24_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 27 clk_ibuf/O
0.538 0.538 tNET RR 1 cnt_1_s0/CLK
0.878 0.340 tC2Q RF 4 cnt_1_s0/Q
1.589 0.711 tNET FF 1 n57_s2/I1
2.403 0.814 tINS FF 8 n57_s2/F
3.115 0.711 tNET FF 1 n40_s2/I1
3.929 0.814 tINS FF 10 n40_s2/F
4.640 0.711 tNET FF 1 n38_s2/I0
5.405 0.765 tINS FF 2 n38_s2/F
6.116 0.711 tNET FF 1 n38_s1/I1
6.931 0.814 tINS FF 1 n38_s1/F
7.642 0.711 tNET FF 1 cnt_24_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 27 clk_ibuf/O
20.538 0.538 tNET RR 1 cnt_24_s0/CLK
20.242 -0.296 tSu 1 cnt_24_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.208, 45.153%; route: 3.557, 50.066%; tC2Q: 0.340, 4.781%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 4

Path Summary:
Slack 12.649
Data Arrival Time 7.593
Data Required Time 20.242
From cnt_5_s0
To cnt_1_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 27 clk_ibuf/O
0.538 0.538 tNET RR 1 cnt_5_s0/CLK
0.878 0.340 tC2Q RF 4 cnt_5_s0/Q
1.589 0.711 tNET FF 1 n112_s26/I1
2.403 0.814 tINS FF 1 n112_s26/F
3.115 0.711 tNET FF 1 n38_s5/I1
3.929 0.814 tINS FF 1 n38_s5/F
4.640 0.711 tNET FF 1 n38_s3/I0
5.405 0.765 tINS FF 22 n38_s3/F
6.116 0.711 tNET FF 1 n61_s1/I0
6.881 0.765 tINS FF 1 n61_s1/F
7.593 0.711 tNET FF 1 cnt_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 27 clk_ibuf/O
20.538 0.538 tNET RR 1 cnt_1_s0/CLK
20.242 -0.296 tSu 1 cnt_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.158, 44.767%; route: 3.557, 50.419%; tC2Q: 0.340, 4.814%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 5

Path Summary:
Slack 12.649
Data Arrival Time 7.593
Data Required Time 20.242
From cnt_5_s0
To cnt_2_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 27 clk_ibuf/O
0.538 0.538 tNET RR 1 cnt_5_s0/CLK
0.878 0.340 tC2Q RF 4 cnt_5_s0/Q
1.589 0.711 tNET FF 1 n112_s26/I1
2.403 0.814 tINS FF 1 n112_s26/F
3.115 0.711 tNET FF 1 n38_s5/I1
3.929 0.814 tINS FF 1 n38_s5/F
4.640 0.711 tNET FF 1 n38_s3/I0
5.405 0.765 tINS FF 22 n38_s3/F
6.116 0.711 tNET FF 1 n60_s2/I0
6.881 0.765 tINS FF 1 n60_s2/F
7.593 0.711 tNET FF 1 cnt_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 27 clk_ibuf/O
20.538 0.538 tNET RR 1 cnt_2_s0/CLK
20.242 -0.296 tSu 1 cnt_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.158, 44.767%; route: 3.557, 50.419%; tC2Q: 0.340, 4.814%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%