Timing Messages

Report Title	Timing Analysis Report
Design File	/home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_1P5/EXAMPLE CODE/Button_filtering_counterl_Led/impl/gwsynthesis/key_led.vg
Physical Constraints File	/home/quang1806/Desktop/USING FOR UPDATE CODE GITLAB/onekiwi_fpga_board/fpga_1P5/EXAMPLE CODE/Button_filtering_counterl_Led/src/key_led.cst
Timing Constraint File	---
Tool Version	V1.9.11
Part Number	GW1N-UV1P5QN48XFC7/I6
Device	GW1N-1P5
Device Version	C
Created Time	Fri Mar 7 22:44:31 2025
Legal Announcement	Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 1.71V 85C C7/I6
Hold Delay Model	Fast 3.6V 0C C7/I6
Numbers of Paths Analyzed	142
Numbers of Endpoints Analyzed	142
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	Clk	Base	20.000	50.000	0.000	10.000			Clk_ibuf/I

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	Clk	50.000(MHz)	206.103(MHz)	4	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
Clk	Setup	0.000	0
Clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	15.148	key_filter0/cnt_4_s0/Q	key_filter0/cnt_10_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	4.556
2	15.278	key_filter0/cnt_4_s0/Q	key_filter0/cnt_17_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	4.425
3	15.278	key_filter0/cnt_4_s0/Q	key_filter0/cnt_19_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	4.425
4	15.382	key_filter1/cnt_1_s0/Q	key_filter1/cnt_13_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	4.321
5	15.382	key_filter1/cnt_1_s0/Q	key_filter1/cnt_18_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	4.321
6	15.499	key_filter1/cnt_1_s0/Q	key_filter1/cnt_full_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	4.205
7	15.577	key_filter0/cnt_4_s0/Q	key_filter0/cnt_15_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	4.127
8	15.577	key_filter0/cnt_4_s0/Q	key_filter0/cnt_13_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	4.127
9	15.580	key_filter0/cnt_4_s0/Q	key_filter0/cnt_18_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	4.123
10	15.728	key_filter1/cnt_1_s0/Q	key_filter1/cnt_14_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	3.976
11	15.754	key_filter1/cnt_1_s0/Q	key_filter1/cnt_16_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	3.949
12	15.910	key_filter1/cnt_1_s0/Q	key_filter1/cnt_15_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	3.794
13	15.910	key_filter1/cnt_1_s0/Q	key_filter1/cnt_17_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	3.794
14	15.913	key_filter1/cnt_1_s0/Q	key_filter1/cnt_19_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	3.791
15	15.939	key_filter0/cnt_4_s0/Q	key_filter0/cnt_16_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	3.764
16	15.939	key_filter0/cnt_4_s0/Q	key_filter0/cnt_14_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	3.764
17	15.950	key_filter1/cnt_full_s0/Q	key_filter1/en_cnt_s2/CE	Clk:[R]	Clk:[R]	20.000	0.000	4.018
18	15.956	key_filter0/cnt_4_s0/Q	key_filter0/cnt_9_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	3.748
19	15.956	key_filter0/cnt_4_s0/Q	key_filter0/cnt_11_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	3.748
20	15.964	key_filter0/cnt_4_s0/Q	key_filter0/cnt_12_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	3.740
21	16.027	key_filter1/cnt_1_s0/Q	key_filter1/cnt_12_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	3.677
22	16.190	key_filter1/cnt_1_s0/Q	key_filter1/cnt_6_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	3.513
23	16.190	key_filter1/cnt_1_s0/Q	key_filter1/cnt_7_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	3.513
24	16.191	key_filter1/cnt_1_s0/Q	key_filter1/cnt_10_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	3.513
25	16.191	key_filter1/cnt_1_s0/Q	key_filter1/cnt_11_s0/D	Clk:[R]	Clk:[R]	20.000	0.000	3.513

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.524	key_filter1/key_state_s5/Q	key_filter1/key_state_s5/D	Clk:[R]	Clk:[R]	0.000	0.000	0.524
2	0.524	key_filter1/cnt_3_s0/Q	key_filter1/cnt_3_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.524
3	0.524	key_filter1/cnt_16_s0/Q	key_filter1/cnt_16_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.524
4	0.524	key_filter1/cnt_18_s0/Q	key_filter1/cnt_18_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.524
5	0.524	key_filter0/cnt_3_s0/Q	key_filter0/cnt_3_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.524
6	0.524	key_filter0/cnt_12_s0/Q	key_filter0/cnt_12_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.524
7	0.524	key_filter0/cnt_19_s0/Q	key_filter0/cnt_19_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.524
8	0.525	led_ctrl0/led_r_0_s1/Q	led_ctrl0/led_r_0_s1/D	Clk:[R]	Clk:[R]	0.000	0.000	0.525
9	0.525	key_filter1/cnt_4_s0/Q	key_filter1/cnt_4_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.525
10	0.525	key_filter1/cnt_6_s0/Q	key_filter1/cnt_6_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.525
11	0.525	key_filter1/cnt_13_s0/Q	key_filter1/cnt_13_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.525
12	0.525	key_filter0/state.IDEL_s0/Q	key_filter0/state.IDEL_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.525
13	0.525	key_filter0/cnt_4_s0/Q	key_filter0/cnt_4_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.525
14	0.525	key_filter0/cnt_8_s0/Q	key_filter0/cnt_8_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.525
15	0.525	key_filter0/cnt_10_s0/Q	key_filter0/cnt_10_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.525
16	0.525	key_filter0/cnt_11_s0/Q	key_filter0/cnt_11_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.525
17	0.525	key_filter0/cnt_15_s0/Q	key_filter0/cnt_15_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.525
18	0.525	key_filter0/cnt_17_s0/Q	key_filter0/cnt_17_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.525
19	0.526	key_filter1/state.IDEL_s0/Q	key_filter1/state.IDEL_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.526
20	0.526	key_filter0/cnt_6_s0/Q	key_filter0/cnt_6_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.526
21	0.661	key_filter1/key_flag_s5/Q	key_filter1/key_flag_s5/D	Clk:[R]	Clk:[R]	0.000	0.000	0.661
22	0.661	key_filter1/cnt_12_s0/Q	key_filter1/cnt_12_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.661
23	0.661	key_filter0/cnt_5_s0/Q	key_filter0/cnt_5_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.661
24	0.662	key_filter1/cnt_1_s0/Q	key_filter1/cnt_1_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.662
25	0.662	key_filter1/cnt_8_s0/Q	key_filter1/cnt_8_s0/D	Clk:[R]	Clk:[R]	0.000	0.000	0.662

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	6.948	7.874	0.926	High Pulse Width	Clk	key_filter0/key_in_sb_s0
2	6.948	7.874	0.926	High Pulse Width	Clk	key_filter0/key_tmpa_s0
3	6.948	7.874	0.926	High Pulse Width	Clk	key_filter0/state.DOWN_s0
4	6.948	7.874	0.926	High Pulse Width	Clk	key_filter0/cnt_16_s0
5	6.948	7.874	0.926	High Pulse Width	Clk	key_filter0/cnt_8_s0
6	6.948	7.874	0.926	High Pulse Width	Clk	key_filter0/key_state_s5
7	6.948	7.874	0.926	High Pulse Width	Clk	key_filter1/key_state_s5
8	6.948	7.874	0.926	High Pulse Width	Clk	key_filter1/key_flag_s5
9	6.948	7.874	0.926	High Pulse Width	Clk	key_filter0/key_flag_s5
10	6.948	7.874	0.926	High Pulse Width	Clk	key_filter1/state.FILTER1_s1

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	15.148
Data Arrival Time	8.966
Data Required Time	24.114
From	key_filter0/cnt_4_s0
To	key_filter0/cnt_10_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R9C9[1][A]	key_filter0/cnt_4_s0/CLK
4.750	0.340	tC2Q	RF	4	R9C9[1][A]	key_filter0/cnt_4_s0/Q
5.355	0.604	tNET	FF	1	R9C9[3][B]	key_filter0/n92_s5/I0
6.169	0.814	tINS	FF	4	R9C9[3][B]	key_filter0/n92_s5/F
6.772	0.603	tNET	FF	1	R11C10[3][B]	key_filter0/n100_s3/I1
7.382	0.609	tINS	FF	3	R11C10[3][B]	key_filter0/n100_s3/F
8.357	0.975	tNET	FF	1	R11C7[0][A]	key_filter0/n101_s1/I1
8.966	0.609	tINS	FF	1	R11C7[0][A]	key_filter0/n101_s1/F
8.966	0.000	tNET	FF	1	R11C7[0][A]	key_filter0/cnt_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R11C7[0][A]	key_filter0/cnt_10_s0/CLK
24.114	-0.296	tSu		1	R11C7[0][A]	key_filter0/cnt_10_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.033, 44.617%; route: 2.183, 47.927%; tC2Q: 0.340, 7.455%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path2

Path Summary:

Slack	15.278
Data Arrival Time	8.836
Data Required Time	24.114
From	key_filter0/cnt_4_s0
To	key_filter0/cnt_17_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R9C9[1][A]	key_filter0/cnt_4_s0/CLK
4.750	0.340	tC2Q	RF	4	R9C9[1][A]	key_filter0/cnt_4_s0/Q
5.355	0.604	tNET	FF	1	R9C9[3][B]	key_filter0/n92_s5/I0
6.169	0.814	tINS	FF	4	R9C9[3][B]	key_filter0/n92_s5/F
6.785	0.616	tNET	FF	1	R11C9[3][B]	key_filter0/n92_s2/I2
7.394	0.609	tINS	FF	7	R11C9[3][B]	key_filter0/n92_s2/F
8.022	0.628	tNET	FF	1	R11C8[1][A]	key_filter0/n94_s1/I0
8.836	0.814	tINS	FF	1	R11C8[1][A]	key_filter0/n94_s1/F
8.836	0.000	tNET	FF	1	R11C8[1][A]	key_filter0/cnt_17_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R11C8[1][A]	key_filter0/cnt_17_s0/CLK
24.114	-0.296	tSu		1	R11C8[1][A]	key_filter0/cnt_17_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.238, 50.569%; route: 1.848, 41.757%; tC2Q: 0.340, 7.675%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path3

Path Summary:

Slack	15.278
Data Arrival Time	8.836
Data Required Time	24.114
From	key_filter0/cnt_4_s0
To	key_filter0/cnt_19_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R9C9[1][A]	key_filter0/cnt_4_s0/CLK
4.750	0.340	tC2Q	RF	4	R9C9[1][A]	key_filter0/cnt_4_s0/Q
5.355	0.604	tNET	FF	1	R9C9[3][B]	key_filter0/n92_s5/I0
6.169	0.814	tINS	FF	4	R9C9[3][B]	key_filter0/n92_s5/F
6.785	0.616	tNET	FF	1	R11C9[3][B]	key_filter0/n92_s2/I2
7.394	0.609	tINS	FF	7	R11C9[3][B]	key_filter0/n92_s2/F
8.022	0.628	tNET	FF	1	R11C8[0][A]	key_filter0/n92_s1/I0
8.836	0.814	tINS	FF	1	R11C8[0][A]	key_filter0/n92_s1/F
8.836	0.000	tNET	FF	1	R11C8[0][A]	key_filter0/cnt_19_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R11C8[0][A]	key_filter0/cnt_19_s0/CLK
24.114	-0.296	tSu		1	R11C8[0][A]	key_filter0/cnt_19_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.238, 50.569%; route: 1.848, 41.757%; tC2Q: 0.340, 7.675%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path4

Path Summary:

Slack	15.382
Data Arrival Time	8.732
Data Required Time	24.114
From	key_filter1/cnt_1_s0
To	key_filter1/cnt_13_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R9C12[2][A]	key_filter1/cnt_1_s0/CLK
4.750	0.340	tC2Q	RR	4	R9C12[2][A]	key_filter1/cnt_1_s0/Q
5.066	0.315	tNET	RR	1	R9C13[2][B]	key_filter1/n107_s2/I1
5.880	0.814	tINS	RF	7	R9C13[2][B]	key_filter1/n107_s2/F
6.492	0.612	tNET	FF	1	R8C12[1][A]	key_filter1/n98_s2/I1
7.306	0.814	tINS	FF	7	R8C12[1][A]	key_filter1/n98_s2/F
7.918	0.612	tNET	FF	1	R9C11[1][A]	key_filter1/n98_s1/I1
8.732	0.814	tINS	FF	1	R9C11[1][A]	key_filter1/n98_s1/F
8.732	0.000	tNET	FF	1	R9C11[1][A]	key_filter1/cnt_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R9C11[1][A]	key_filter1/cnt_13_s0/CLK
24.114	-0.296	tSu		1	R9C11[1][A]	key_filter1/cnt_13_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.443, 56.536%; route: 1.539, 35.604%; tC2Q: 0.340, 7.859%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path5

Path Summary:

Slack	15.382
Data Arrival Time	8.732
Data Required Time	24.114
From	key_filter1/cnt_1_s0
To	key_filter1/cnt_18_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R9C12[2][A]	key_filter1/cnt_1_s0/CLK
4.750	0.340	tC2Q	RR	4	R9C12[2][A]	key_filter1/cnt_1_s0/Q
5.066	0.315	tNET	RR	1	R9C13[2][B]	key_filter1/n107_s2/I1
5.880	0.814	tINS	RF	7	R9C13[2][B]	key_filter1/n107_s2/F
6.492	0.612	tNET	FF	1	R8C12[1][A]	key_filter1/n98_s2/I1
7.306	0.814	tINS	FF	7	R8C12[1][A]	key_filter1/n98_s2/F
7.918	0.612	tNET	FF	1	R9C11[0][A]	key_filter1/n93_s1/I0
8.732	0.814	tINS	FF	1	R9C11[0][A]	key_filter1/n93_s1/F
8.732	0.000	tNET	FF	1	R9C11[0][A]	key_filter1/cnt_18_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R9C11[0][A]	key_filter1/cnt_18_s0/CLK
24.114	-0.296	tSu		1	R9C11[0][A]	key_filter1/cnt_18_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.443, 56.536%; route: 1.539, 35.604%; tC2Q: 0.340, 7.859%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path6

Path Summary:

Slack	15.499
Data Arrival Time	8.616
Data Required Time	24.114
From	key_filter1/cnt_1_s0
To	key_filter1/cnt_full_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R9C12[2][A]	key_filter1/cnt_1_s0/CLK
4.750	0.340	tC2Q	RR	4	R9C12[2][A]	key_filter1/cnt_1_s0/Q
5.066	0.315	tNET	RR	1	R9C13[2][B]	key_filter1/n107_s2/I1
5.880	0.814	tINS	RF	7	R9C13[2][B]	key_filter1/n107_s2/F
6.488	0.608	tNET	FF	1	R8C11[3][A]	key_filter1/n148_s3/I2
7.303	0.814	tINS	FF	3	R8C11[3][A]	key_filter1/n148_s3/F
8.152	0.849	tNET	FF	1	R8C12[0][A]	key_filter1/n148_s1/I2
8.616	0.464	tINS	FF	1	R8C12[0][A]	key_filter1/n148_s1/F
8.616	0.000	tNET	FF	1	R8C12[0][A]	key_filter1/cnt_full_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R8C12[0][A]	key_filter1/cnt_full_s0/CLK
24.114	-0.296	tSu		1	R8C12[0][A]	key_filter1/cnt_full_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.093, 49.763%; route: 1.773, 42.160%; tC2Q: 0.340, 8.077%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path7

Path Summary:

Slack	15.577
Data Arrival Time	8.537
Data Required Time	24.114
From	key_filter0/cnt_4_s0
To	key_filter0/cnt_15_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R9C9[1][A]	key_filter0/cnt_4_s0/CLK
4.750	0.340	tC2Q	RF	4	R9C9[1][A]	key_filter0/cnt_4_s0/Q
5.355	0.604	tNET	FF	1	R9C9[3][B]	key_filter0/n92_s5/I0
6.169	0.814	tINS	FF	4	R9C9[3][B]	key_filter0/n92_s5/F
6.785	0.616	tNET	FF	1	R11C9[3][B]	key_filter0/n92_s2/I2
7.394	0.609	tINS	FF	7	R11C9[3][B]	key_filter0/n92_s2/F
7.773	0.379	tNET	FF	1	R11C7[1][A]	key_filter0/n96_s1/I0
8.537	0.765	tINS	FF	1	R11C7[1][A]	key_filter0/n96_s1/F
8.537	0.000	tNET	FF	1	R11C7[1][A]	key_filter0/cnt_15_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R11C7[1][A]	key_filter0/cnt_15_s0/CLK
24.114	-0.296	tSu		1	R11C7[1][A]	key_filter0/cnt_15_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.188, 53.026%; route: 1.599, 38.744%; tC2Q: 0.340, 8.230%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path8

Path Summary:

Slack	15.577
Data Arrival Time	8.537
Data Required Time	24.114
From	key_filter0/cnt_4_s0
To	key_filter0/cnt_13_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R9C9[1][A]	key_filter0/cnt_4_s0/CLK
4.750	0.340	tC2Q	RF	4	R9C9[1][A]	key_filter0/cnt_4_s0/Q
5.355	0.604	tNET	FF	1	R9C9[3][B]	key_filter0/n92_s5/I0
6.169	0.814	tINS	FF	4	R9C9[3][B]	key_filter0/n92_s5/F
6.785	0.616	tNET	FF	1	R11C9[3][B]	key_filter0/n92_s2/I2
7.394	0.609	tINS	FF	7	R11C9[3][B]	key_filter0/n92_s2/F
7.773	0.379	tNET	FF	1	R11C7[2][A]	key_filter0/n98_s1/I1
8.537	0.765	tINS	FF	1	R11C7[2][A]	key_filter0/n98_s1/F
8.537	0.000	tNET	FF	1	R11C7[2][A]	key_filter0/cnt_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R11C7[2][A]	key_filter0/cnt_13_s0/CLK
24.114	-0.296	tSu		1	R11C7[2][A]	key_filter0/cnt_13_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.188, 53.026%; route: 1.599, 38.744%; tC2Q: 0.340, 8.230%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path9

Path Summary:

Slack	15.580
Data Arrival Time	8.534
Data Required Time	24.114
From	key_filter0/cnt_4_s0
To	key_filter0/cnt_18_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R9C9[1][A]	key_filter0/cnt_4_s0/CLK
4.750	0.340	tC2Q	RF	4	R9C9[1][A]	key_filter0/cnt_4_s0/Q
5.355	0.604	tNET	FF	1	R9C9[3][B]	key_filter0/n92_s5/I0
6.169	0.814	tINS	FF	4	R9C9[3][B]	key_filter0/n92_s5/F
6.785	0.616	tNET	FF	1	R11C9[3][B]	key_filter0/n92_s2/I2
7.394	0.609	tINS	FF	7	R11C9[3][B]	key_filter0/n92_s2/F
7.769	0.375	tNET	FF	1	R11C10[0][B]	key_filter0/n93_s1/I0
8.534	0.765	tINS	FF	1	R11C10[0][B]	key_filter0/n93_s1/F
8.534	0.000	tNET	FF	1	R11C10[0][B]	key_filter0/cnt_18_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R11C10[0][B]	key_filter0/cnt_18_s0/CLK
24.114	-0.296	tSu		1	R11C10[0][B]	key_filter0/cnt_18_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.188, 53.069%; route: 1.595, 38.694%; tC2Q: 0.340, 8.237%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path10

Path Summary:

Slack	15.728
Data Arrival Time	8.386
Data Required Time	24.114
From	key_filter1/cnt_1_s0
To	key_filter1/cnt_14_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R9C12[2][A]	key_filter1/cnt_1_s0/CLK
4.750	0.340	tC2Q	RR	4	R9C12[2][A]	key_filter1/cnt_1_s0/Q
5.066	0.315	tNET	RR	1	R9C13[2][B]	key_filter1/n107_s2/I1
5.880	0.814	tINS	RF	7	R9C13[2][B]	key_filter1/n107_s2/F
6.492	0.612	tNET	FF	1	R8C12[1][A]	key_filter1/n98_s2/I1
7.306	0.814	tINS	FF	7	R8C12[1][A]	key_filter1/n98_s2/F
7.923	0.617	tNET	FF	1	R9C11[0][B]	key_filter1/n97_s1/I1
8.386	0.464	tINS	FF	1	R9C11[0][B]	key_filter1/n97_s1/F
8.386	0.000	tNET	FF	1	R9C11[0][B]	key_filter1/cnt_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R9C11[0][B]	key_filter1/cnt_14_s0/CLK
24.114	-0.296	tSu		1	R9C11[0][B]	key_filter1/cnt_14_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.093, 52.633%; route: 1.544, 38.824%; tC2Q: 0.340, 8.542%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path11

Path Summary:

Slack	15.754
Data Arrival Time	8.360
Data Required Time	24.114
From	key_filter1/cnt_1_s0
To	key_filter1/cnt_16_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R9C12[2][A]	key_filter1/cnt_1_s0/CLK
4.750	0.340	tC2Q	RR	4	R9C12[2][A]	key_filter1/cnt_1_s0/Q
5.066	0.315	tNET	RR	1	R9C13[2][B]	key_filter1/n107_s2/I1
5.880	0.814	tINS	RF	7	R9C13[2][B]	key_filter1/n107_s2/F
6.492	0.612	tNET	FF	1	R8C12[1][A]	key_filter1/n98_s2/I1
7.278	0.786	tINS	FR	7	R8C12[1][A]	key_filter1/n98_s2/F
7.595	0.318	tNET	RR	1	R9C12[0][A]	key_filter1/n95_s1/I0
8.360	0.765	tINS	RF	1	R9C12[0][A]	key_filter1/n95_s1/F
8.360	0.000	tNET	FF	1	R9C12[0][A]	key_filter1/cnt_16_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R9C12[0][A]	key_filter1/cnt_16_s0/CLK
24.114	-0.296	tSu		1	R9C12[0][A]	key_filter1/cnt_16_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.365, 59.888%; route: 1.245, 31.513%; tC2Q: 0.340, 8.599%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path12

Path Summary:

Slack	15.910
Data Arrival Time	8.204
Data Required Time	24.114
From	key_filter1/cnt_1_s0
To	key_filter1/cnt_15_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R9C12[2][A]	key_filter1/cnt_1_s0/CLK
4.750	0.340	tC2Q	RR	4	R9C12[2][A]	key_filter1/cnt_1_s0/Q
5.066	0.315	tNET	RR	1	R9C13[2][B]	key_filter1/n107_s2/I1
5.880	0.814	tINS	RF	7	R9C13[2][B]	key_filter1/n107_s2/F
6.492	0.612	tNET	FF	1	R8C12[1][A]	key_filter1/n98_s2/I1
7.278	0.786	tINS	FR	7	R8C12[1][A]	key_filter1/n98_s2/F
7.595	0.318	tNET	RR	1	R9C12[0][B]	key_filter1/n96_s1/I0
8.204	0.609	tINS	RF	1	R9C12[0][B]	key_filter1/n96_s1/F
8.204	0.000	tNET	FF	1	R9C12[0][B]	key_filter1/cnt_15_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R9C12[0][B]	key_filter1/cnt_15_s0/CLK
24.114	-0.296	tSu		1	R9C12[0][B]	key_filter1/cnt_15_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.210, 58.243%; route: 1.245, 32.805%; tC2Q: 0.340, 8.952%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path13

Path Summary:

Slack	15.910
Data Arrival Time	8.204
Data Required Time	24.114
From	key_filter1/cnt_1_s0
To	key_filter1/cnt_17_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R9C12[2][A]	key_filter1/cnt_1_s0/CLK
4.750	0.340	tC2Q	RR	4	R9C12[2][A]	key_filter1/cnt_1_s0/Q
5.066	0.315	tNET	RR	1	R9C13[2][B]	key_filter1/n107_s2/I1
5.880	0.814	tINS	RF	7	R9C13[2][B]	key_filter1/n107_s2/F
6.492	0.612	tNET	FF	1	R8C12[1][A]	key_filter1/n98_s2/I1
7.278	0.786	tINS	FR	7	R8C12[1][A]	key_filter1/n98_s2/F
7.595	0.318	tNET	RR	1	R9C12[2][B]	key_filter1/n94_s1/I0
8.204	0.609	tINS	RF	1	R9C12[2][B]	key_filter1/n94_s1/F
8.204	0.000	tNET	FF	1	R9C12[2][B]	key_filter1/cnt_17_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R9C12[2][B]	key_filter1/cnt_17_s0/CLK
24.114	-0.296	tSu		1	R9C12[2][B]	key_filter1/cnt_17_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.210, 58.243%; route: 1.245, 32.805%; tC2Q: 0.340, 8.952%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path14

Path Summary:

Slack	15.913
Data Arrival Time	8.202
Data Required Time	24.114
From	key_filter1/cnt_1_s0
To	key_filter1/cnt_19_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R9C12[2][A]	key_filter1/cnt_1_s0/CLK
4.750	0.340	tC2Q	RR	4	R9C12[2][A]	key_filter1/cnt_1_s0/Q
5.066	0.315	tNET	RR	1	R9C13[2][B]	key_filter1/n107_s2/I1
5.880	0.814	tINS	RF	7	R9C13[2][B]	key_filter1/n107_s2/F
6.492	0.612	tNET	FF	1	R8C12[1][A]	key_filter1/n98_s2/I1
7.278	0.786	tINS	FR	7	R8C12[1][A]	key_filter1/n98_s2/F
7.592	0.315	tNET	RR	1	R8C11[1][B]	key_filter1/n92_s1/I0
8.202	0.609	tINS	RF	1	R8C11[1][B]	key_filter1/n92_s1/F
8.202	0.000	tNET	FF	1	R8C11[1][B]	key_filter1/cnt_19_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R8C11[1][B]	key_filter1/cnt_19_s0/CLK
24.114	-0.296	tSu		1	R8C11[1][B]	key_filter1/cnt_19_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.210, 58.288%; route: 1.242, 32.753%; tC2Q: 0.340, 8.959%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path15

Path Summary:

Slack	15.939
Data Arrival Time	8.175
Data Required Time	24.114
From	key_filter0/cnt_4_s0
To	key_filter0/cnt_16_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R9C9[1][A]	key_filter0/cnt_4_s0/CLK
4.750	0.340	tC2Q	RF	4	R9C9[1][A]	key_filter0/cnt_4_s0/Q
5.355	0.604	tNET	FF	1	R9C9[3][B]	key_filter0/n92_s5/I0
6.169	0.814	tINS	FF	4	R9C9[3][B]	key_filter0/n92_s5/F
6.785	0.616	tNET	FF	1	R11C9[3][B]	key_filter0/n92_s2/I2
7.394	0.609	tINS	FF	7	R11C9[3][B]	key_filter0/n92_s2/F
7.410	0.016	tNET	FF	1	R11C9[0][B]	key_filter0/n95_s1/I0
8.175	0.765	tINS	FF	1	R11C9[0][B]	key_filter0/n95_s1/F
8.175	0.000	tNET	FF	1	R11C9[0][B]	key_filter0/cnt_16_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R11C9[0][B]	key_filter0/cnt_16_s0/CLK
24.114	-0.296	tSu		1	R11C9[0][B]	key_filter0/cnt_16_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.188, 58.131%; route: 1.236, 32.846%; tC2Q: 0.340, 9.023%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path16

Path Summary:

Slack	15.939
Data Arrival Time	8.175
Data Required Time	24.114
From	key_filter0/cnt_4_s0
To	key_filter0/cnt_14_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R9C9[1][A]	key_filter0/cnt_4_s0/CLK
4.750	0.340	tC2Q	RF	4	R9C9[1][A]	key_filter0/cnt_4_s0/Q
5.355	0.604	tNET	FF	1	R9C9[3][B]	key_filter0/n92_s5/I0
6.169	0.814	tINS	FF	4	R9C9[3][B]	key_filter0/n92_s5/F
6.785	0.616	tNET	FF	1	R11C9[3][B]	key_filter0/n92_s2/I2
7.394	0.609	tINS	FF	7	R11C9[3][B]	key_filter0/n92_s2/F
7.410	0.016	tNET	FF	1	R11C9[2][A]	key_filter0/n97_s1/I1
8.175	0.765	tINS	FF	1	R11C9[2][A]	key_filter0/n97_s1/F
8.175	0.000	tNET	FF	1	R11C9[2][A]	key_filter0/cnt_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R11C9[2][A]	key_filter0/cnt_14_s0/CLK
24.114	-0.296	tSu		1	R11C9[2][A]	key_filter0/cnt_14_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.188, 58.131%; route: 1.236, 32.846%; tC2Q: 0.340, 9.023%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path17

Path Summary:

Slack	15.950
Data Arrival Time	8.429
Data Required Time	24.378
From	key_filter1/cnt_full_s0
To	key_filter1/en_cnt_s2
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R8C12[0][A]	key_filter1/cnt_full_s0/CLK
4.750	0.340	tC2Q	RF	8	R8C12[0][A]	key_filter1/cnt_full_s0/Q
5.363	0.612	tNET	FF	1	R7C13[1][B]	key_filter1/en_cnt_s6/I1
6.149	0.786	tINS	FR	1	R7C13[1][B]	key_filter1/en_cnt_s6/F
6.459	0.310	tNET	RR	1	R8C13[1][B]	key_filter1/en_cnt_s4/I2
7.054	0.594	tINS	RR	1	R8C13[1][B]	key_filter1/en_cnt_s4/F
8.429	1.375	tNET	RR	1	R8C13[1][A]	key_filter1/en_cnt_s2/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R8C13[1][A]	key_filter1/en_cnt_s2/CLK
24.378	-0.032	tSu		1	R8C13[1][A]	key_filter1/en_cnt_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	3
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 1.380, 34.355%; route: 2.298, 57.193%; tC2Q: 0.340, 8.452%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path18

Path Summary:

Slack	15.956
Data Arrival Time	8.158
Data Required Time	24.114
From	key_filter0/cnt_4_s0
To	key_filter0/cnt_9_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R9C9[1][A]	key_filter0/cnt_4_s0/CLK
4.750	0.340	tC2Q	RF	4	R9C9[1][A]	key_filter0/cnt_4_s0/Q
5.355	0.604	tNET	FF	1	R9C9[3][B]	key_filter0/n92_s5/I0
6.169	0.814	tINS	FF	4	R9C9[3][B]	key_filter0/n92_s5/F
6.772	0.603	tNET	FF	1	R11C10[3][B]	key_filter0/n100_s3/I1
7.382	0.609	tINS	FF	3	R11C10[3][B]	key_filter0/n100_s3/F
7.394	0.012	tNET	FF	1	R11C10[2][A]	key_filter0/n102_s1/I1
8.159	0.765	tINS	FF	1	R11C10[2][A]	key_filter0/n102_s1/F
8.159	0.000	tNET	FF	1	R11C10[2][A]	key_filter0/cnt_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R11C10[2][A]	key_filter0/cnt_9_s0/CLK
24.114	-0.296	tSu		1	R11C10[2][A]	key_filter0/cnt_9_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.188, 58.384%; route: 1.220, 32.554%; tC2Q: 0.340, 9.062%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path19

Path Summary:

Slack	15.956
Data Arrival Time	8.158
Data Required Time	24.114
From	key_filter0/cnt_4_s0
To	key_filter0/cnt_11_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R9C9[1][A]	key_filter0/cnt_4_s0/CLK
4.750	0.340	tC2Q	RF	4	R9C9[1][A]	key_filter0/cnt_4_s0/Q
5.355	0.604	tNET	FF	1	R9C9[3][B]	key_filter0/n92_s5/I0
6.169	0.814	tINS	FF	4	R9C9[3][B]	key_filter0/n92_s5/F
6.772	0.603	tNET	FF	1	R11C10[3][B]	key_filter0/n100_s3/I1
7.382	0.609	tINS	FF	3	R11C10[3][B]	key_filter0/n100_s3/F
7.394	0.012	tNET	FF	1	R11C10[1][A]	key_filter0/n100_s1/I1
8.159	0.765	tINS	FF	1	R11C10[1][A]	key_filter0/n100_s1/F
8.159	0.000	tNET	FF	1	R11C10[1][A]	key_filter0/cnt_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R11C10[1][A]	key_filter0/cnt_11_s0/CLK
24.114	-0.296	tSu		1	R11C10[1][A]	key_filter0/cnt_11_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.188, 58.384%; route: 1.220, 32.554%; tC2Q: 0.340, 9.062%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path20

Path Summary:

Slack	15.964
Data Arrival Time	8.150
Data Required Time	24.114
From	key_filter0/cnt_4_s0
To	key_filter0/cnt_12_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R9C9[1][A]	key_filter0/cnt_4_s0/CLK
4.750	0.340	tC2Q	RF	4	R9C9[1][A]	key_filter0/cnt_4_s0/Q
5.355	0.604	tNET	FF	1	R9C9[3][B]	key_filter0/n92_s5/I0
6.169	0.814	tINS	FF	4	R9C9[3][B]	key_filter0/n92_s5/F
6.772	0.603	tNET	FF	1	R11C10[2][B]	key_filter0/n99_s2/I2
7.382	0.609	tINS	FF	1	R11C10[2][B]	key_filter0/n99_s2/F
7.386	0.004	tNET	FF	1	R11C10[0][A]	key_filter0/n99_s1/I0
8.150	0.765	tINS	FF	1	R11C10[0][A]	key_filter0/n99_s1/F
8.150	0.000	tNET	FF	1	R11C10[0][A]	key_filter0/cnt_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R11C10[0][A]	key_filter0/cnt_12_s0/CLK
24.114	-0.296	tSu		1	R11C10[0][A]	key_filter0/cnt_12_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.188, 58.511%; route: 1.212, 32.408%; tC2Q: 0.340, 9.081%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path21

Path Summary:

Slack	16.027
Data Arrival Time	8.087
Data Required Time	24.114
From	key_filter1/cnt_1_s0
To	key_filter1/cnt_12_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R9C12[2][A]	key_filter1/cnt_1_s0/CLK
4.750	0.340	tC2Q	RR	4	R9C12[2][A]	key_filter1/cnt_1_s0/Q
5.066	0.315	tNET	RR	1	R9C13[2][B]	key_filter1/n107_s2/I1
5.880	0.814	tINS	RF	7	R9C13[2][B]	key_filter1/n107_s2/F
6.259	0.379	tNET	FF	1	R9C11[3][A]	key_filter1/n103_s2/I0
7.023	0.765	tINS	FF	2	R9C11[3][A]	key_filter1/n103_s2/F
7.623	0.600	tNET	FF	1	R8C12[2][A]	key_filter1/n99_s1/I0
8.087	0.464	tINS	FF	1	R8C12[2][A]	key_filter1/n99_s1/F
8.087	0.000	tNET	FF	1	R8C12[2][A]	key_filter1/cnt_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R8C12[2][A]	key_filter1/cnt_12_s0/CLK
24.114	-0.296	tSu		1	R8C12[2][A]	key_filter1/cnt_12_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.043, 55.564%; route: 1.294, 35.199%; tC2Q: 0.340, 9.237%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path22

Path Summary:

Slack	16.190
Data Arrival Time	7.924
Data Required Time	24.114
From	key_filter1/cnt_1_s0
To	key_filter1/cnt_6_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R9C12[2][A]	key_filter1/cnt_1_s0/CLK
4.750	0.340	tC2Q	RR	4	R9C12[2][A]	key_filter1/cnt_1_s0/Q
5.066	0.315	tNET	RR	1	R9C13[2][B]	key_filter1/n107_s2/I1
5.880	0.814	tINS	RF	7	R9C13[2][B]	key_filter1/n107_s2/F
6.488	0.608	tNET	FF	1	R8C11[3][A]	key_filter1/n148_s3/I2
7.303	0.814	tINS	FF	3	R8C11[3][A]	key_filter1/n148_s3/F
7.315	0.012	tNET	FF	1	R8C11[1][A]	key_filter1/n105_s1/I1
7.924	0.609	tINS	FF	1	R8C11[1][A]	key_filter1/n105_s1/F
7.924	0.000	tNET	FF	1	R8C11[1][A]	key_filter1/cnt_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R8C11[1][A]	key_filter1/cnt_6_s0/CLK
24.114	-0.296	tSu		1	R8C11[1][A]	key_filter1/cnt_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.238, 63.697%; route: 0.936, 26.636%; tC2Q: 0.340, 9.667%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path23

Path Summary:

Slack	16.190
Data Arrival Time	7.924
Data Required Time	24.114
From	key_filter1/cnt_1_s0
To	key_filter1/cnt_7_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R9C12[2][A]	key_filter1/cnt_1_s0/CLK
4.750	0.340	tC2Q	RR	4	R9C12[2][A]	key_filter1/cnt_1_s0/Q
5.066	0.315	tNET	RR	1	R9C13[2][B]	key_filter1/n107_s2/I1
5.880	0.814	tINS	RF	7	R9C13[2][B]	key_filter1/n107_s2/F
6.488	0.608	tNET	FF	1	R8C11[3][A]	key_filter1/n148_s3/I2
7.303	0.814	tINS	FF	3	R8C11[3][A]	key_filter1/n148_s3/F
7.315	0.012	tNET	FF	1	R8C11[0][B]	key_filter1/n104_s1/I1
7.924	0.609	tINS	FF	1	R8C11[0][B]	key_filter1/n104_s1/F
7.924	0.000	tNET	FF	1	R8C11[0][B]	key_filter1/cnt_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R8C11[0][B]	key_filter1/cnt_7_s0/CLK
24.114	-0.296	tSu		1	R8C11[0][B]	key_filter1/cnt_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.238, 63.697%; route: 0.936, 26.636%; tC2Q: 0.340, 9.667%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path24

Path Summary:

Slack	16.191
Data Arrival Time	7.923
Data Required Time	24.114
From	key_filter1/cnt_1_s0
To	key_filter1/cnt_10_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R9C12[2][A]	key_filter1/cnt_1_s0/CLK
4.750	0.340	tC2Q	RR	4	R9C12[2][A]	key_filter1/cnt_1_s0/Q
5.066	0.315	tNET	RR	1	R9C13[2][B]	key_filter1/n107_s2/I1
5.880	0.814	tINS	RF	7	R9C13[2][B]	key_filter1/n107_s2/F
6.492	0.612	tNET	FF	1	R8C12[3][A]	key_filter1/n101_s2/I2
7.306	0.814	tINS	FF	2	R8C12[3][A]	key_filter1/n101_s2/F
7.314	0.008	tNET	FF	1	R8C12[1][B]	key_filter1/n101_s1/I1
7.923	0.609	tINS	FF	1	R8C12[1][B]	key_filter1/n101_s1/F
7.923	0.000	tNET	FF	1	R8C12[1][B]	key_filter1/cnt_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R8C12[1][B]	key_filter1/cnt_10_s0/CLK
24.114	-0.296	tSu		1	R8C12[1][B]	key_filter1/cnt_10_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.238, 63.710%; route: 0.935, 26.622%; tC2Q: 0.340, 9.669%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path25

Path Summary:

Slack	16.191
Data Arrival Time	7.923
Data Required Time	24.114
From	key_filter1/cnt_1_s0
To	key_filter1/cnt_11_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
4.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
4.411	0.181	tNET	RR	1	R9C12[2][A]	key_filter1/cnt_1_s0/CLK
4.750	0.340	tC2Q	RR	4	R9C12[2][A]	key_filter1/cnt_1_s0/Q
5.066	0.315	tNET	RR	1	R9C13[2][B]	key_filter1/n107_s2/I1
5.880	0.814	tINS	RF	7	R9C13[2][B]	key_filter1/n107_s2/F
6.492	0.612	tNET	FF	1	R8C12[3][A]	key_filter1/n101_s2/I2
7.306	0.814	tINS	FF	2	R8C12[3][A]	key_filter1/n101_s2/F
7.314	0.008	tNET	FF	1	R8C12[0][B]	key_filter1/n100_s1/I1
7.923	0.609	tINS	FF	1	R8C12[0][B]	key_filter1/n100_s1/F
7.923	0.000	tNET	FF	1	R8C12[0][B]	key_filter1/cnt_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					Clk
20.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
24.230	4.230	tINS	RR	66	IOL6[A]	Clk_ibuf/O
24.411	0.181	tNET	RR	1	R8C12[0][B]	key_filter1/cnt_11_s0/CLK
24.114	-0.296	tSu		1	R8C12[0][B]	key_filter1/cnt_11_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.238, 63.710%; route: 0.935, 26.622%; tC2Q: 0.340, 9.669%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	key_filter1/key_state_s5
To	key_filter1/key_state_s5
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C11[0][A]	key_filter1/key_state_s5/CLK
3.510	0.247	tC2Q	RR	2	R7C11[0][A]	key_filter1/key_state_s5/Q
3.512	0.002	tNET	RR	1	R7C11[0][A]	key_filter1/n52_s9/I3
3.788	0.276	tINS	RF	1	R7C11[0][A]	key_filter1/n52_s9/F
3.788	0.000	tNET	FF	1	R7C11[0][A]	key_filter1/key_state_s5/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C11[0][A]	key_filter1/key_state_s5/CLK
3.263	0.000	tHld		1	R7C11[0][A]	key_filter1/key_state_s5

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path2

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	key_filter1/cnt_3_s0
To	key_filter1/cnt_3_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C13[0][A]	key_filter1/cnt_3_s0/CLK
3.510	0.247	tC2Q	RR	2	R9C13[0][A]	key_filter1/cnt_3_s0/Q
3.512	0.002	tNET	RR	1	R9C13[0][A]	key_filter1/n108_s1/I1
3.788	0.276	tINS	RF	1	R9C13[0][A]	key_filter1/n108_s1/F
3.788	0.000	tNET	FF	1	R9C13[0][A]	key_filter1/cnt_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C13[0][A]	key_filter1/cnt_3_s0/CLK
3.263	0.000	tHld		1	R9C13[0][A]	key_filter1/cnt_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path3

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	key_filter1/cnt_16_s0
To	key_filter1/cnt_16_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C12[0][A]	key_filter1/cnt_16_s0/CLK
3.510	0.247	tC2Q	RR	3	R9C12[0][A]	key_filter1/cnt_16_s0/Q
3.512	0.002	tNET	RR	1	R9C12[0][A]	key_filter1/n95_s1/I2
3.788	0.276	tINS	RF	1	R9C12[0][A]	key_filter1/n95_s1/F
3.788	0.000	tNET	FF	1	R9C12[0][A]	key_filter1/cnt_16_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C12[0][A]	key_filter1/cnt_16_s0/CLK
3.263	0.000	tHld		1	R9C12[0][A]	key_filter1/cnt_16_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path4

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	key_filter1/cnt_18_s0
To	key_filter1/cnt_18_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C11[0][A]	key_filter1/cnt_18_s0/CLK
3.510	0.247	tC2Q	RR	3	R9C11[0][A]	key_filter1/cnt_18_s0/Q
3.512	0.002	tNET	RR	1	R9C11[0][A]	key_filter1/n93_s1/I2
3.788	0.276	tINS	RF	1	R9C11[0][A]	key_filter1/n93_s1/F
3.788	0.000	tNET	FF	1	R9C11[0][A]	key_filter1/cnt_18_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C11[0][A]	key_filter1/cnt_18_s0/CLK
3.263	0.000	tHld		1	R9C11[0][A]	key_filter1/cnt_18_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path5

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	key_filter0/cnt_3_s0
To	key_filter0/cnt_3_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C10[1][A]	key_filter0/cnt_3_s0/CLK
3.510	0.247	tC2Q	RR	2	R9C10[1][A]	key_filter0/cnt_3_s0/Q
3.512	0.002	tNET	RR	1	R9C10[1][A]	key_filter0/n108_s1/I1
3.788	0.276	tINS	RF	1	R9C10[1][A]	key_filter0/n108_s1/F
3.788	0.000	tNET	FF	1	R9C10[1][A]	key_filter0/cnt_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C10[1][A]	key_filter0/cnt_3_s0/CLK
3.263	0.000	tHld		1	R9C10[1][A]	key_filter0/cnt_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path6

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	key_filter0/cnt_12_s0
To	key_filter0/cnt_12_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C10[0][A]	key_filter0/cnt_12_s0/CLK
3.510	0.247	tC2Q	RR	3	R11C10[0][A]	key_filter0/cnt_12_s0/Q
3.512	0.002	tNET	RR	1	R11C10[0][A]	key_filter0/n99_s1/I1
3.788	0.276	tINS	RF	1	R11C10[0][A]	key_filter0/n99_s1/F
3.788	0.000	tNET	FF	1	R11C10[0][A]	key_filter0/cnt_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C10[0][A]	key_filter0/cnt_12_s0/CLK
3.263	0.000	tHld		1	R11C10[0][A]	key_filter0/cnt_12_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path7

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	key_filter0/cnt_19_s0
To	key_filter0/cnt_19_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C8[0][A]	key_filter0/cnt_19_s0/CLK
3.510	0.247	tC2Q	RR	2	R11C8[0][A]	key_filter0/cnt_19_s0/Q
3.512	0.002	tNET	RR	1	R11C8[0][A]	key_filter0/n92_s1/I2
3.788	0.276	tINS	RF	1	R11C8[0][A]	key_filter0/n92_s1/F
3.788	0.000	tNET	FF	1	R11C8[0][A]	key_filter0/cnt_19_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C8[0][A]	key_filter0/cnt_19_s0/CLK
3.263	0.000	tHld		1	R11C8[0][A]	key_filter0/cnt_19_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path8

Path Summary:

Slack	0.525
Data Arrival Time	3.788
Data Required Time	3.263
From	led_ctrl0/led_r_0_s1
To	led_ctrl0/led_r_0_s1
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C13[0][A]	led_ctrl0/led_r_0_s1/CLK
3.510	0.247	tC2Q	RR	3	R11C13[0][A]	led_ctrl0/led_r_0_s1/Q
3.513	0.003	tNET	RR	1	R11C13[0][A]	led_ctrl0/n18_s1/I0
3.788	0.276	tINS	RF	1	R11C13[0][A]	led_ctrl0/n18_s1/F
3.788	0.000	tNET	FF	1	R11C13[0][A]	led_ctrl0/led_r_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C13[0][A]	led_ctrl0/led_r_0_s1/CLK
3.263	0.000	tHld		1	R11C13[0][A]	led_ctrl0/led_r_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path9

Path Summary:

Slack	0.525
Data Arrival Time	3.788
Data Required Time	3.263
From	key_filter1/cnt_4_s0
To	key_filter1/cnt_4_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C13[1][A]	key_filter1/cnt_4_s0/CLK
3.510	0.247	tC2Q	RR	4	R9C13[1][A]	key_filter1/cnt_4_s0/Q
3.513	0.003	tNET	RR	1	R9C13[1][A]	key_filter1/n107_s1/I0
3.788	0.276	tINS	RF	1	R9C13[1][A]	key_filter1/n107_s1/F
3.788	0.000	tNET	FF	1	R9C13[1][A]	key_filter1/cnt_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C13[1][A]	key_filter1/cnt_4_s0/CLK
3.263	0.000	tHld		1	R9C13[1][A]	key_filter1/cnt_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path10

Path Summary:

Slack	0.525
Data Arrival Time	3.788
Data Required Time	3.263
From	key_filter1/cnt_6_s0
To	key_filter1/cnt_6_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C11[1][A]	key_filter1/cnt_6_s0/CLK
3.510	0.247	tC2Q	RR	4	R8C11[1][A]	key_filter1/cnt_6_s0/Q
3.513	0.003	tNET	RR	1	R8C11[1][A]	key_filter1/n105_s1/I0
3.788	0.276	tINS	RF	1	R8C11[1][A]	key_filter1/n105_s1/F
3.788	0.000	tNET	FF	1	R8C11[1][A]	key_filter1/cnt_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C11[1][A]	key_filter1/cnt_6_s0/CLK
3.263	0.000	tHld		1	R8C11[1][A]	key_filter1/cnt_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path11

Path Summary:

Slack	0.525
Data Arrival Time	3.788
Data Required Time	3.263
From	key_filter1/cnt_13_s0
To	key_filter1/cnt_13_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C11[1][A]	key_filter1/cnt_13_s0/CLK
3.510	0.247	tC2Q	RR	6	R9C11[1][A]	key_filter1/cnt_13_s0/Q
3.513	0.003	tNET	RR	1	R9C11[1][A]	key_filter1/n98_s1/I0
3.788	0.276	tINS	RF	1	R9C11[1][A]	key_filter1/n98_s1/F
3.788	0.000	tNET	FF	1	R9C11[1][A]	key_filter1/cnt_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C11[1][A]	key_filter1/cnt_13_s0/CLK
3.263	0.000	tHld		1	R9C11[1][A]	key_filter1/cnt_13_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path12

Path Summary:

Slack	0.525
Data Arrival Time	3.788
Data Required Time	3.263
From	key_filter0/state.IDEL_s0
To	key_filter0/state.IDEL_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C10[0][A]	key_filter0/state.IDEL_s0/CLK
3.510	0.247	tC2Q	RR	7	R9C10[0][A]	key_filter0/state.IDEL_s0/Q
3.513	0.003	tNET	RR	1	R9C10[0][A]	key_filter0/n52_s6/I1
3.788	0.276	tINS	RF	1	R9C10[0][A]	key_filter0/n52_s6/F
3.788	0.000	tNET	FF	1	R9C10[0][A]	key_filter0/state.IDEL_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C10[0][A]	key_filter0/state.IDEL_s0/CLK
3.263	0.000	tHld		1	R9C10[0][A]	key_filter0/state.IDEL_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path13

Path Summary:

Slack	0.525
Data Arrival Time	3.788
Data Required Time	3.263
From	key_filter0/cnt_4_s0
To	key_filter0/cnt_4_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C9[1][A]	key_filter0/cnt_4_s0/CLK
3.510	0.247	tC2Q	RR	4	R9C9[1][A]	key_filter0/cnt_4_s0/Q
3.513	0.003	tNET	RR	1	R9C9[1][A]	key_filter0/n107_s1/I0
3.788	0.276	tINS	RF	1	R9C9[1][A]	key_filter0/n107_s1/F
3.788	0.000	tNET	FF	1	R9C9[1][A]	key_filter0/cnt_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C9[1][A]	key_filter0/cnt_4_s0/CLK
3.263	0.000	tHld		1	R9C9[1][A]	key_filter0/cnt_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path14

Path Summary:

Slack	0.525
Data Arrival Time	3.788
Data Required Time	3.263
From	key_filter0/cnt_8_s0
To	key_filter0/cnt_8_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C9[0][A]	key_filter0/cnt_8_s0/CLK
3.510	0.247	tC2Q	RR	5	R11C9[0][A]	key_filter0/cnt_8_s0/Q
3.513	0.003	tNET	RR	1	R11C9[0][A]	key_filter0/n103_s2/I0
3.788	0.276	tINS	RF	1	R11C9[0][A]	key_filter0/n103_s2/F
3.788	0.000	tNET	FF	1	R11C9[0][A]	key_filter0/cnt_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C9[0][A]	key_filter0/cnt_8_s0/CLK
3.263	0.000	tHld		1	R11C9[0][A]	key_filter0/cnt_8_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path15

Path Summary:

Slack	0.525
Data Arrival Time	3.788
Data Required Time	3.263
From	key_filter0/cnt_10_s0
To	key_filter0/cnt_10_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C7[0][A]	key_filter0/cnt_10_s0/CLK
3.510	0.247	tC2Q	RR	3	R11C7[0][A]	key_filter0/cnt_10_s0/Q
3.513	0.003	tNET	RR	1	R11C7[0][A]	key_filter0/n101_s1/I2
3.788	0.276	tINS	RF	1	R11C7[0][A]	key_filter0/n101_s1/F
3.788	0.000	tNET	FF	1	R11C7[0][A]	key_filter0/cnt_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C7[0][A]	key_filter0/cnt_10_s0/CLK
3.263	0.000	tHld		1	R11C7[0][A]	key_filter0/cnt_10_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path16

Path Summary:

Slack	0.525
Data Arrival Time	3.788
Data Required Time	3.263
From	key_filter0/cnt_11_s0
To	key_filter0/cnt_11_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C10[1][A]	key_filter0/cnt_11_s0/CLK
3.510	0.247	tC2Q	RR	4	R11C10[1][A]	key_filter0/cnt_11_s0/Q
3.513	0.003	tNET	RR	1	R11C10[1][A]	key_filter0/n100_s1/I2
3.788	0.276	tINS	RF	1	R11C10[1][A]	key_filter0/n100_s1/F
3.788	0.000	tNET	FF	1	R11C10[1][A]	key_filter0/cnt_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C10[1][A]	key_filter0/cnt_11_s0/CLK
3.263	0.000	tHld		1	R11C10[1][A]	key_filter0/cnt_11_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path17

Path Summary:

Slack	0.525
Data Arrival Time	3.788
Data Required Time	3.263
From	key_filter0/cnt_15_s0
To	key_filter0/cnt_15_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C7[1][A]	key_filter0/cnt_15_s0/CLK
3.510	0.247	tC2Q	RR	4	R11C7[1][A]	key_filter0/cnt_15_s0/Q
3.513	0.003	tNET	RR	1	R11C7[1][A]	key_filter0/n96_s1/I2
3.788	0.276	tINS	RF	1	R11C7[1][A]	key_filter0/n96_s1/F
3.788	0.000	tNET	FF	1	R11C7[1][A]	key_filter0/cnt_15_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C7[1][A]	key_filter0/cnt_15_s0/CLK
3.263	0.000	tHld		1	R11C7[1][A]	key_filter0/cnt_15_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path18

Path Summary:

Slack	0.525
Data Arrival Time	3.788
Data Required Time	3.263
From	key_filter0/cnt_17_s0
To	key_filter0/cnt_17_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C8[1][A]	key_filter0/cnt_17_s0/CLK
3.510	0.247	tC2Q	RR	4	R11C8[1][A]	key_filter0/cnt_17_s0/Q
3.513	0.003	tNET	RR	1	R11C8[1][A]	key_filter0/n94_s1/I2
3.788	0.276	tINS	RF	1	R11C8[1][A]	key_filter0/n94_s1/F
3.788	0.000	tNET	FF	1	R11C8[1][A]	key_filter0/cnt_17_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R11C8[1][A]	key_filter0/cnt_17_s0/CLK
3.263	0.000	tHld		1	R11C8[1][A]	key_filter0/cnt_17_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path19

Path Summary:

Slack	0.526
Data Arrival Time	3.789
Data Required Time	3.263
From	key_filter1/state.IDEL_s0
To	key_filter1/state.IDEL_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C11[1][A]	key_filter1/state.IDEL_s0/CLK
3.510	0.247	tC2Q	RR	7	R7C11[1][A]	key_filter1/state.IDEL_s0/Q
3.514	0.003	tNET	RR	1	R7C11[1][A]	key_filter1/n52_s6/I1
3.789	0.276	tINS	RF	1	R7C11[1][A]	key_filter1/n52_s6/F
3.789	0.000	tNET	FF	1	R7C11[1][A]	key_filter1/state.IDEL_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R7C11[1][A]	key_filter1/state.IDEL_s0/CLK
3.263	0.000	tHld		1	R7C11[1][A]	key_filter1/state.IDEL_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path20

Path Summary:

Slack	0.526
Data Arrival Time	3.789
Data Required Time	3.263
From	key_filter0/cnt_6_s0
To	key_filter0/cnt_6_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C9[0][A]	key_filter0/cnt_6_s0/CLK
3.510	0.247	tC2Q	RR	4	R9C9[0][A]	key_filter0/cnt_6_s0/Q
3.514	0.003	tNET	RR	1	R9C9[0][A]	key_filter0/n105_s1/I0
3.789	0.276	tINS	RF	1	R9C9[0][A]	key_filter0/n105_s1/F
3.789	0.000	tNET	FF	1	R9C9[0][A]	key_filter0/cnt_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C9[0][A]	key_filter0/cnt_6_s0/CLK
3.263	0.000	tHld		1	R9C9[0][A]	key_filter0/cnt_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path21

Path Summary:

Slack	0.661
Data Arrival Time	3.924
Data Required Time	3.263
From	key_filter1/key_flag_s5
To	key_filter1/key_flag_s5
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C13[2][A]	key_filter1/key_flag_s5/CLK
3.510	0.247	tC2Q	RR	2	R8C13[2][A]	key_filter1/key_flag_s5/Q
3.512	0.002	tNET	RR	1	R8C13[2][A]	key_filter1/n27_s4/I1
3.924	0.412	tINS	RR	1	R8C13[2][A]	key_filter1/n27_s4/F
3.924	0.000	tNET	RR	1	R8C13[2][A]	key_filter1/key_flag_s5/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C13[2][A]	key_filter1/key_flag_s5/CLK
3.263	0.000	tHld		1	R8C13[2][A]	key_filter1/key_flag_s5

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.412, 62.353%; route: 0.002, 0.265%; tC2Q: 0.247, 37.382%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path22

Path Summary:

Slack	0.661
Data Arrival Time	3.924
Data Required Time	3.263
From	key_filter1/cnt_12_s0
To	key_filter1/cnt_12_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C12[2][A]	key_filter1/cnt_12_s0/CLK
3.510	0.247	tC2Q	RR	3	R8C12[2][A]	key_filter1/cnt_12_s0/Q
3.512	0.002	tNET	RR	1	R8C12[2][A]	key_filter1/n99_s1/I2
3.924	0.412	tINS	RR	1	R8C12[2][A]	key_filter1/n99_s1/F
3.924	0.000	tNET	RR	1	R8C12[2][A]	key_filter1/cnt_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R8C12[2][A]	key_filter1/cnt_12_s0/CLK
3.263	0.000	tHld		1	R8C12[2][A]	key_filter1/cnt_12_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.412, 62.353%; route: 0.002, 0.265%; tC2Q: 0.247, 37.382%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path23

Path Summary:

Slack	0.661
Data Arrival Time	3.924
Data Required Time	3.263
From	key_filter0/cnt_5_s0
To	key_filter0/cnt_5_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C9[2][A]	key_filter0/cnt_5_s0/CLK
3.510	0.247	tC2Q	RR	3	R9C9[2][A]	key_filter0/cnt_5_s0/Q
3.512	0.002	tNET	RR	1	R9C9[2][A]	key_filter0/n106_s1/I2
3.924	0.412	tINS	RR	1	R9C9[2][A]	key_filter0/n106_s1/F
3.924	0.000	tNET	RR	1	R9C9[2][A]	key_filter0/cnt_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C9[2][A]	key_filter0/cnt_5_s0/CLK
3.263	0.000	tHld		1	R9C9[2][A]	key_filter0/cnt_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.412, 62.353%; route: 0.002, 0.265%; tC2Q: 0.247, 37.382%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path24

Path Summary:

Slack	0.662
Data Arrival Time	3.925
Data Required Time	3.263
From	key_filter1/cnt_1_s0
To	key_filter1/cnt_1_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C12[2][A]	key_filter1/cnt_1_s0/CLK
3.510	0.247	tC2Q	RR	4	R9C12[2][A]	key_filter1/cnt_1_s0/Q
3.513	0.003	tNET	RR	1	R9C12[2][A]	key_filter1/n110_s1/I1
3.925	0.412	tINS	RR	1	R9C12[2][A]	key_filter1/n110_s1/F
3.925	0.000	tNET	RR	1	R9C12[2][A]	key_filter1/cnt_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C12[2][A]	key_filter1/cnt_1_s0/CLK
3.263	0.000	tHld		1	R9C12[2][A]	key_filter1/cnt_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.412, 62.271%; route: 0.003, 0.397%; tC2Q: 0.247, 37.333%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path25

Path Summary:

Slack	0.662
Data Arrival Time	3.925
Data Required Time	3.263
From	key_filter1/cnt_8_s0
To	key_filter1/cnt_8_s0
Launch Clk	Clk:[R]
Latch Clk	Clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C11[2][A]	key_filter1/cnt_8_s0/CLK
3.510	0.247	tC2Q	RR	5	R9C11[2][A]	key_filter1/cnt_8_s0/Q
3.513	0.003	tNET	RR	1	R9C11[2][A]	key_filter1/n103_s4/I0
3.925	0.412	tINS	RR	1	R9C11[2][A]	key_filter1/n103_s4/F
3.925	0.000	tNET	RR	1	R9C11[2][A]	key_filter1/cnt_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					Clk
0.000	0.000	tCL	RR	1	IOL6[A]	Clk_ibuf/I
3.126	3.126	tINS	RR	66	IOL6[A]	Clk_ibuf/O
3.263	0.137	tNET	RR	1	R9C11[2][A]	key_filter1/cnt_8_s0/CLK
3.263	0.000	tHld		1	R9C11[2][A]	key_filter1/cnt_8_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.412, 62.271%; route: 0.003, 0.397%; tC2Q: 0.247, 37.333%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	Clk
Objects:	key_filter0/key_in_sb_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
4.411	0.181	tNET	RR	key_filter0/key_in_sb_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
12.285	0.145	tNET	FF	key_filter0/key_in_sb_s0/CLK

MPW2

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	Clk
Objects:	key_filter0/key_tmpa_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
4.411	0.181	tNET	RR	key_filter0/key_tmpa_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
12.285	0.145	tNET	FF	key_filter0/key_tmpa_s0/CLK

MPW3

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	Clk
Objects:	key_filter0/state.DOWN_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
4.411	0.181	tNET	RR	key_filter0/state.DOWN_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
12.285	0.145	tNET	FF	key_filter0/state.DOWN_s0/CLK

MPW4

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	Clk
Objects:	key_filter0/cnt_16_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
4.411	0.181	tNET	RR	key_filter0/cnt_16_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
12.285	0.145	tNET	FF	key_filter0/cnt_16_s0/CLK

MPW5

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	Clk
Objects:	key_filter0/cnt_8_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
4.411	0.181	tNET	RR	key_filter0/cnt_8_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
12.285	0.145	tNET	FF	key_filter0/cnt_8_s0/CLK

MPW6

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	Clk
Objects:	key_filter0/key_state_s5

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
4.411	0.181	tNET	RR	key_filter0/key_state_s5/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
12.285	0.145	tNET	FF	key_filter0/key_state_s5/CLK

MPW7

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	Clk
Objects:	key_filter1/key_state_s5

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
4.411	0.181	tNET	RR	key_filter1/key_state_s5/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
12.285	0.145	tNET	FF	key_filter1/key_state_s5/CLK

MPW8

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	Clk
Objects:	key_filter1/key_flag_s5

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
4.411	0.181	tNET	RR	key_filter1/key_flag_s5/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
12.285	0.145	tNET	FF	key_filter1/key_flag_s5/CLK

MPW9

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	Clk
Objects:	key_filter0/key_flag_s5

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
4.411	0.181	tNET	RR	key_filter0/key_flag_s5/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
12.285	0.145	tNET	FF	key_filter0/key_flag_s5/CLK

MPW10

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	Clk
Objects:	key_filter1/state.FILTER1_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			Clk
0.000	0.000	tCL	RR	Clk_ibuf/I
4.230	4.230	tINS	RR	Clk_ibuf/O
4.411	0.181	tNET	RR	key_filter1/state.FILTER1_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			Clk
10.000	0.000	tCL	FF	Clk_ibuf/I
12.140	2.140	tINS	FF	Clk_ibuf/O
12.285	0.145	tNET	FF	key_filter1/state.FILTER1_s1/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
66	Clk_d	15.148	0.195
20	en_cnt	17.254	1.346
20	en_cnt	17.919	0.634
9	key_tmpa	16.758	1.071
9	key_tmpa	16.873	1.798
8	key_tmpb	16.856	0.611
8	cnt_full	15.950	0.621
8	key_tmpb	16.816	0.618
8	cnt_full	16.796	0.983
7	n92_6	15.278	0.628

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R9C9	81.94%
R9C12	73.61%
R9C11	70.83%
R9C10	68.06%
R11C9	63.89%
R11C10	63.89%
R7C11	62.50%
R8C12	62.50%
R9C13	59.72%
R8C13	54.17%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command